2020-06-16 13:38:43 +00:00
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/*-*- mode:unix-assembly; indent-tabs-mode:t; tab-width:8; coding:utf-8 -*-│
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2020-06-15 14:18:57 +00:00
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│vi: set et ft=asm ts=8 sw=8 fenc=utf-8 :vi│
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╞══════════════════════════════════════════════════════════════════════════════╡
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│ Copyright 2020 Justine Alexandra Roberts Tunney │
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│ │
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2020-12-28 01:18:44 +00:00
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│ Permission to use, copy, modify, and/or distribute this software for │
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│ any purpose with or without fee is hereby granted, provided that the │
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│ above copyright notice and this permission notice appear in all copies. │
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2020-06-15 14:18:57 +00:00
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│ │
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2020-12-28 01:18:44 +00:00
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│ THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL │
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│ WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED │
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│ WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE │
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│ AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL │
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│ DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR │
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│ PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER │
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│ TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR │
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│ PERFORMANCE OF THIS SOFTWARE. │
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2020-06-15 14:18:57 +00:00
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╚─────────────────────────────────────────────────────────────────────────────*/
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2021-02-08 17:19:00 +00:00
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// Documentation for Intel(R)'s “Most Complicated Instruction”(TM)
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//
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// mnemonic op1 op2 op3 op4 modif f description, notes
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// ═══════════ ════ ════ ════ ═══ ════════ ═════════════════════════════
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// PCMPESTRM XMM0 Vdq Wdq ... o..szapc Explicit Length, Return Mask
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// PCMPESTRI rCX Vdq Wdq ... o..szapc Explicit Length, Return Index
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// PCMPISTRM XMM0 Vdq Wdq Ib o..szapc Implicit Length, Return Mask
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// PCMPISTRI rCX Vdq Wdq Ib o..szapc Implicit Length, Return Index
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//
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// CF ← Reset if IntRes2 is equal to zero, set otherwise
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// ZF ← Set if any byte/word of xmm2/mem128 is null, reset otherwise
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// SF ← Set if any byte/word of xmm1 is null, reset otherwise
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// OF ← IntRes2[0]
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// AF ← Reset
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// PF ← Reset
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//
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// PCMP{E,I}STR{I,M} Control Byte
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// @see Intel Manual V.2B §4.1.7
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//
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// ┌─0:index of the LEAST significant, set, bit is used
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// │ regardless of corresponding input element validity
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// │ intres2 is returned in least significant bits of xmm0
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// ├─1:index of the MOST significant, set, bit is used
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// │ regardless of corresponding input element validity
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// │ each bit of intres2 is expanded to byte/word
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// │┌─0:negation of intres1 is for all 16 (8) bits
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// │├─1:negation of intres1 is masked by reg/mem validity
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// ││┌─intres1 is negated (1’s complement)
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// │││┌─mode{equalany,ranges,equaleach,equalordered}
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// ││││ ┌─issigned
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// ││││ │┌─is16bit
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// u│││├┐││
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2020-06-15 14:18:57 +00:00
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.Lequalordered = 0b00001100
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.Lequalorder16 = 0b00001101
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.Lequalranges8 = 0b00000100
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