2023-11-17 00:34:53 +00:00
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//===-- clear_cache.c - Implement __clear_cache ---------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "int_lib.h"
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2023-11-17 10:33:14 +00:00
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#include "libc/dce.h"
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#include "libc/runtime/syslib.internal.h"
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2023-11-17 00:34:53 +00:00
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// The compiler generates calls to __clear_cache() when creating
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// trampoline functions on the stack for use with nested functions.
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// It is expected to invalidate the instruction cache for the
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// specified range.
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void __clear_cache(void *start, void *end) {
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2023-11-17 10:33:14 +00:00
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#ifdef __aarch64__
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if (IsXnu()) {
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__syslib->__sys_icache_invalidate((char *)start,
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(char *)end - (char *)start);
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return;
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}
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2023-11-17 00:34:53 +00:00
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uint64_t xstart = (uint64_t)(uintptr_t)start;
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uint64_t xend = (uint64_t)(uintptr_t)end;
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uint64_t addr;
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// Get Cache Type Info
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uint64_t ctr_el0;
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__asm __volatile("mrs %0, ctr_el0" : "=r"(ctr_el0));
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// dc & ic instructions must use 64bit registers so we don't use
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// uintptr_t in case this runs in an IPL32 environment.
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const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15);
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for (addr = xstart & ~(dcache_line_size - 1); addr < xend;
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addr += dcache_line_size)
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__asm __volatile("dc cvau, %0" ::"r"(addr));
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__asm __volatile("dsb ish");
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const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15);
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for (addr = xstart & ~(icache_line_size - 1); addr < xend;
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addr += icache_line_size)
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__asm __volatile("ic ivau, %0" ::"r"(addr));
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__asm __volatile("isb sy");
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2023-11-17 10:33:14 +00:00
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2023-11-17 00:34:53 +00:00
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#elif defined(__powerpc64__)
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const size_t line_size = 32;
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const size_t len = (uintptr_t)end - (uintptr_t)start;
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const uintptr_t mask = ~(line_size - 1);
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const uintptr_t start_line = ((uintptr_t)start) & mask;
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const uintptr_t end_line = ((uintptr_t)start + len + line_size - 1) & mask;
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2023-11-17 10:33:14 +00:00
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for (uintptr_t line = start_line; line < end_line; line += line_size) {
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2023-11-17 00:34:53 +00:00
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__asm__ volatile("dcbf 0, %0" : : "r"(line));
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2023-11-17 10:33:14 +00:00
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}
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2023-11-17 00:34:53 +00:00
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__asm__ volatile("sync");
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2023-11-17 10:33:14 +00:00
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for (uintptr_t line = start_line; line < end_line; line += line_size) {
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2023-11-17 00:34:53 +00:00
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__asm__ volatile("icbi 0, %0" : : "r"(line));
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2023-11-17 10:33:14 +00:00
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}
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2023-11-17 00:34:53 +00:00
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__asm__ volatile("isync");
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#else
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compilerrt_abort();
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#endif
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}
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