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Improve locks and signals
- Introduce fast spinlock API - Double rand64() perf w/ spinlock - Improve raise() on New Technology - Support gettid() across platforms - Implement SA_NODEFER on New Technology - Move the lock intrinsics into LIBC_INTRIN - Make SIGTRAP recoverable on New Technology - Block SIGCHLD in wait4() on New Technology - Add threading prototypes for XNU and FreeBSD - Rewrite abort() fixing its minor bugs on XNU/NT - Shave down a lot of the content in libc/bits/bits.h - Let signal handlers modify CPU registers on New Technology
This commit is contained in:
Justine Tunney
parent
f68f1789bd
commit
046c7ebd4a
110 changed files with 1514 additions and 876 deletions
181
libc/bits/bits.h
181
libc/bits/bits.h
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@ -21,11 +21,6 @@ unsigned long roundup2pow(unsigned long) libcesque pureconst;
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unsigned long roundup2log(unsigned long) libcesque pureconst;
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unsigned long rounddown2pow(unsigned long) libcesque pureconst;
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unsigned long hamming(unsigned long, unsigned long) pureconst;
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intptr_t lockxchg(void *, void *, size_t);
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bool cmpxchg(void *, intptr_t, intptr_t, size_t);
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bool lockcmpxchg(void *, intptr_t, intptr_t, size_t);
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intptr_t atomic_load(void *, size_t);
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intptr_t atomic_store(void *, intptr_t, size_t);
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unsigned bextra(const unsigned *, size_t, char);
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/*───────────────────────────────────────────────────────────────────────────│─╗
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@ -136,84 +131,6 @@ unsigned bextra(const unsigned *, size_t, char);
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╚────────────────────────────────────────────────────────────────────────────│*/
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#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
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/*
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* Constraints for virtual machine flags.
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* @note we beseech clang devs for flag constraints
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*/
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#ifdef __GCC_ASM_FLAG_OUTPUTS__ /* GCC6+ CLANG10+ */
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#define CFLAG_CONSTRAINT "=@ccc"
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#define CFLAG_ASM(OP) OP
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#define ZFLAG_CONSTRAINT "=@ccz"
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#define ZFLAG_ASM(OP) OP
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#define OFLAG_CONSTRAINT "=@cco"
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#define OFLAG_ASM(OP) OP
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#define SFLAG_CONSTRAINT "=@ccs"
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#define SFLAG_ASM(SP) SP
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#define ABOVE_CONSTRAINT "=@cca" /* i.e. !ZF && !CF */
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#define ABOVEFLAG_ASM(OP) OP
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#else
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#define CFLAG_CONSTRAINT "=q"
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#define CFLAG_ASM(OP) OP "\n\tsetc\t%b0"
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#define ZFLAG_CONSTRAINT "=q"
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#define ZFLAG_ASM(OP) OP "\n\tsetz\t%b0"
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#define OFLAG_CONSTRAINT "=q"
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#define OFLAG_ASM(OP) OP "\n\tseto\t%b0"
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#define SFLAG_CONSTRAINT "=q"
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#define SFLAG_ASM(SP) OP "\n\tsets\t%b0"
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#define ABOVE_CONSTRAINT "=@cca"
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#define ABOVEFLAG_ASM(OP) OP "\n\tseta\t%b0"
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#endif
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/**
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* Reads scalar from memory w/ one operation.
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*
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* @param MEM is alignas(𝑘) uint𝑘_t[hasatleast 1] where 𝑘 ∈ {8,16,32,64}
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* @return *(MEM)
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* @note defeats compiler load tearing optimizations
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* @note alignas(𝑘) is implied if compiler knows type
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* @note alignas(𝑘) only avoids multi-core / cross-page edge cases
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* @see Intel's Six-Thousand Page Manual V.3A §8.2.3.1
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* @see atomic_store()
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*/
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#define atomic_load(MEM) \
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({ \
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autotype(MEM) Mem = (MEM); \
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typeof(*Mem) Reg; \
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asm("mov\t%1,%0" : "=r"(Reg) : "m"(*Mem)); \
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Reg; \
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})
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/**
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* Saves scalar to memory w/ one operation.
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*
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* This is guaranteed to happen in either one or zero operations,
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* depending on whether or not it's possible for *(MEM) to be read
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* afterwards. This macro only forbids compiler from using >1 ops.
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*
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* @param MEM is alignas(𝑘) uint𝑘_t[hasatleast 1] where 𝑘 ∈ {8,16,32,64}
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* @param VAL is uint𝑘_t w/ better encoding for immediates (constexpr)
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* @return VAL
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* @note alignas(𝑘) on nexgen32e only needed for end of page gotcha
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* @note alignas(𝑘) is implied if compiler knows type
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* @note needed to defeat store tearing optimizations
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* @see Intel Six-Thousand Page Manual Manual V.3A §8.2.3.1
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* @see atomic_load()
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*/
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#define atomic_store(MEM, VAL) \
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({ \
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autotype(VAL) Val = (VAL); \
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typeof(&Val) Mem = (MEM); \
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asm("mov%z1\t%1,%0" : "=m"(*Mem) : "r"(Val)); \
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Val; \
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})
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#define bts(MEM, BIT) __BitOp("bts", BIT, MEM) /** bit test and set */
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#define btr(MEM, BIT) __BitOp("btr", BIT, MEM) /** bit test and reset */
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#define btc(MEM, BIT) __BitOp("btc", BIT, MEM) /** bit test and complement */
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#define lockbts(MEM, BIT) __BitOp("lock bts", BIT, MEM)
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#define lockbtr(MEM, BIT) __BitOp("lock btr", BIT, MEM)
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#define lockbtc(MEM, BIT) __BitOp("lock btc", BIT, MEM)
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#define lockinc(MEM) __ArithmeticOp1("lock inc", MEM)
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#define lockdec(MEM) __ArithmeticOp1("lock dec", MEM)
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#define locknot(MEM) __ArithmeticOp1("lock not", MEM)
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@ -225,66 +142,6 @@ unsigned bextra(const unsigned *, size_t, char);
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#define lockandeq(MEM, VAL) __ArithmeticOp2("lock and", VAL, MEM)
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#define lockoreq(MEM, VAL) __ArithmeticOp2("lock or", VAL, MEM)
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/**
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* Exchanges *MEMORY into *LOCALVAR w/ one operation.
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*
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* @param MEMORY is uint𝑘_t[hasatleast 1] where 𝑘 ∈ {8,16,32,64}
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* @param LOCALVAR is uint𝑘_t[hasatleast 1]
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* @return LOCALVAR[0]
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* @see xchg()
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*/
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#define lockxchg(MEMORY, LOCALVAR) \
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({ \
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asm("xchg\t%0,%1" : "+%m"(*(MEMORY)), "+r"(*(LOCALVAR))); \
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*(LOCALVAR); \
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})
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/**
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* Compares and exchanges.
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*
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* @param IFTHING is uint𝑘_t[hasatleast 1] where 𝑘 ∈ {8,16,32,64}
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* @return true if value was exchanged, otherwise false
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* @see lockcmpxchg()
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*/
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#define cmpxchg(IFTHING, ISEQUALTOME, REPLACEITWITHME) \
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({ \
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bool DidIt; \
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autotype(IFTHING) IfThing = (IFTHING); \
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typeof(*IfThing) IsEqualToMe = (ISEQUALTOME); \
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typeof(*IfThing) ReplaceItWithMe = (REPLACEITWITHME); \
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asm volatile(ZFLAG_ASM("cmpxchg\t%3,%1") \
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: ZFLAG_CONSTRAINT(DidIt), "+m"(*IfThing), "+a"(IsEqualToMe) \
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: "r"(ReplaceItWithMe) \
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: "cc"); \
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DidIt; \
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})
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/**
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* Compares and exchanges w/ one operation.
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*
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* @param IFTHING is uint𝑘_t[hasatleast 1] where 𝑘 ∈ {8,16,32,64}
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* @return true if value was exchanged, otherwise false
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* @see lockcmpxchg()
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*/
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#define lockcmpxchg(IFTHING, ISEQUALTOME, REPLACEITWITHME) \
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({ \
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bool DidIt; \
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autotype(IFTHING) IfThing = (IFTHING); \
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typeof(*IfThing) IsEqualToMe = (ISEQUALTOME); \
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typeof(*IfThing) ReplaceItWithMe = (REPLACEITWITHME); \
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asm volatile(ZFLAG_ASM("lock cmpxchg\t%3,%1") \
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: ZFLAG_CONSTRAINT(DidIt), "+m"(*IfThing), "+a"(IsEqualToMe) \
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: "r"(ReplaceItWithMe) \
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: "cc"); \
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DidIt; \
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})
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#define IsAddressCanonicalForm(P) \
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({ \
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intptr_t p2 = (intptr_t)(P); \
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(0xffff800000000000l <= p2 && p2 <= 0x00007fffffffffffl); \
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})
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/*───────────────────────────────────────────────────────────────────────────│─╗
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│ cosmopolitan § bits » implementation details ─╬─│┼
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╚────────────────────────────────────────────────────────────────────────────│*/
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@ -301,44 +158,6 @@ unsigned bextra(const unsigned *, size_t, char);
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MEM; \
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})
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#define __BitOp(OP, BIT, MEM) \
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({ \
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bool OldBit; \
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if (__builtin_constant_p(BIT)) { \
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asm(CFLAG_ASM(OP "%z1\t%2,%1") \
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: CFLAG_CONSTRAINT(OldBit), \
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"+m"((MEM)[(BIT) / (sizeof((MEM)[0]) * CHAR_BIT)]) \
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: "J"((BIT) % (sizeof((MEM)[0]) * CHAR_BIT)) \
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: "cc"); \
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} else if (sizeof((MEM)[0]) == 2) { \
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asm(CFLAG_ASM(OP "\t%w2,%1") \
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: CFLAG_CONSTRAINT(OldBit), "+m"((MEM)[0]) \
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: "r"(BIT) \
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: "cc"); \
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} else if (sizeof((MEM)[0]) == 4) { \
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asm(CFLAG_ASM(OP "\t%k2,%1") \
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: CFLAG_CONSTRAINT(OldBit), "+m"((MEM)[0]) \
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: "r"(BIT) \
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: "cc"); \
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} else if (sizeof((MEM)[0]) == 8) { \
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asm(CFLAG_ASM(OP "\t%q2,%1") \
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: CFLAG_CONSTRAINT(OldBit), "+m"((MEM)[0]) \
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: "r"(BIT) \
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: "cc"); \
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} \
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OldBit; \
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})
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#else
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#define cmpxchg(MEM, CMP, VAL) \
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cmpxchg(MEM, (intptr_t)(CMP), (intptr_t)(VAL), sizeof(*(MEM)))
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#define lockcmpxchg(MEM, CMP, VAL) \
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lockcmpxchg(MEM, (intptr_t)(CMP), (intptr_t)(VAL), sizeof(*(MEM)))
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#define lockxchg(MEM, VAR) \
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lockxchg(MEM, VAR, sizeof(*(MEM)) / (sizeof(*(MEM)) == sizeof(*(VAR))))
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#define atomic_store(MEM, VAL) \
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atomic_store(MEM, VAL, sizeof(*(MEM)) / (sizeof(*(MEM)) == sizeof(*(VAL))))
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#define atomic_load(MEM) atomic_load(MEM, sizeof(*(MEM)))
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#endif /* __GNUC__ && !__STRICT_ANSI__ */
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COSMOPOLITAN_C_END_
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#endif /* !(__ASSEMBLER__ + __LINKER__ + 0) */
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