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Introduce native support for MacOS ARM64

Browse source 
There's a new program named ape/ape-m1.c which will be used to build an
embeddable binary that can load ape and elf executables. The support is
mostly working so far, but still chasing down ABI issues.
This commit is contained in:
Justine Tunney 2023-05-18 19:05:08 -07:00
parent b852650c08
commit 1422e96b4e
No known key found for this signature in database
GPG key ID: BE714B4575D6E328
757 changed files with 2988 additions and 1321 deletions
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2
libc/intrin/aarch64/memchr.S
View file

@ -29,7 +29,7 @@
#define __memchr_aarch64 memchr
.ident "\n\
.ident "\n\n\
Optimized Routines (MIT License)\n\
Copyright 2022 ARM Limited\n"
.include "libc/disclaimer.inc"

2
libc/intrin/aarch64/memcmp.S
View file

@ -29,7 +29,7 @@
#define __memcmp_aarch64 memcmp
.ident "\n\
.ident "\n\n\
Optimized Routines (MIT License)\n\
Copyright 2022 ARM Limited\n"
.include "libc/disclaimer.inc"

2
libc/intrin/aarch64/memcpy.S
View file

@ -30,7 +30,7 @@
#define __memcpy_aarch64_simd memcpy
#define __memmove_aarch64_simd memmove
.ident "\n\
.ident "\n\n\
Optimized Routines (MIT License)\n\
Copyright 2022 ARM Limited\n"
.include "libc/disclaimer.inc"

2
libc/intrin/aarch64/memrchr.S
View file

@ -29,7 +29,7 @@
#define __memrchr_aarch64 memrchr
.ident "\n\
.ident "\n\n\
Optimized Routines (MIT License)\n\
Copyright 2022 ARM Limited\n"
.include "libc/disclaimer.inc"

2
libc/intrin/aarch64/memset.S
View file

@ -29,7 +29,7 @@
#define __memset_aarch64 memset
.ident "\n\
.ident "\n\n\
Optimized Routines (MIT License)\n\
Copyright 2022 ARM Limited\n"
.include "libc/disclaimer.inc"

2
libc/intrin/aarch64/stpcpy.S
View file

@ -29,7 +29,7 @@
#define __stpcpy_aarch64 stpcpy
.ident "\n\
.ident "\n\n\
Optimized Routines (MIT License)\n\
Copyright 2022 ARM Limited\n"
.include "libc/disclaimer.inc"

2
libc/intrin/aarch64/strchr.S
View file

@ -29,7 +29,7 @@
#define __strchr_aarch64 strchr
.ident "\n\
.ident "\n\n\
Optimized Routines (MIT License)\n\
Copyright 2022 ARM Limited\n"
.include "libc/disclaimer.inc"

2
libc/intrin/aarch64/strchrnul.S
View file

@ -29,7 +29,7 @@
#define __strchrnul_aarch64 strchrnul
.ident "\n\
.ident "\n\n\
Optimized Routines (MIT License)\n\
Copyright 2022 ARM Limited\n"
.include "libc/disclaimer.inc"

2
libc/intrin/aarch64/strcmp.S
View file

@ -29,7 +29,7 @@
#define __strcmp_aarch64 strcmp
.ident "\n\
.ident "\n\n\
Optimized Routines (MIT License)\n\
Copyright 2022 ARM Limited\n"
.include "libc/disclaimer.inc"

2
libc/intrin/aarch64/strcpy.S
View file

@ -29,7 +29,7 @@
#define __strcpy_aarch64 strcpy
.ident "\n\
.ident "\n\n\
Optimized Routines (MIT License)\n\
Copyright 2022 ARM Limited\n"
.include "libc/disclaimer.inc"

2
libc/intrin/aarch64/strlen.S
View file

@ -29,7 +29,7 @@
#define __strlen_aarch64 strlen
.ident "\n\
.ident "\n\n\
Optimized Routines (MIT License)\n\
Copyright 2022 ARM Limited\n"
.include "libc/disclaimer.inc"

2
libc/intrin/aarch64/strncmp.S
View file

@ -29,7 +29,7 @@
#define __strncmp_aarch64 strncmp
.ident "\n\
.ident "\n\n\
Optimized Routines (MIT License)\n\
Copyright 2022 ARM Limited\n"
.include "libc/disclaimer.inc"

2
libc/intrin/aarch64/strnlen.S
View file

@ -29,7 +29,7 @@
#define __strnlen_aarch64 strnlen
.ident "\n\
.ident "\n\n\
Optimized Routines (MIT License)\n\
Copyright 2022 ARM Limited\n"
.include "libc/disclaimer.inc"

2
libc/intrin/aarch64/strrchr.S
View file

@ -29,7 +29,7 @@
#define __strrchr_aarch64 strrchr
.ident "\n\
.ident "\n\n\
Optimized Routines (MIT License)\n\
Copyright 2022 ARM Limited\n"
.include "libc/disclaimer.inc"

8
libc/intrin/asan.c
View file

@ -412,7 +412,7 @@ static bool __asan_is_mapped(int x) {
}
static bool __asan_is_image(const unsigned char *p) {
return _base <= p && p < _end;
return __executable_start <= p && p < _end;
}
static bool __asan_exists(const void *x) {
@ -823,7 +823,7 @@ static void __asan_report_memory_origin(const unsigned char *addr, int size,
default:
break;
}
if (_base <= addr && addr < _end) {
if (__executable_start <= addr && addr < _end) {
__asan_report_memory_origin_image((intptr_t)addr, size);
} else if (IsAutoFrame((intptr_t)addr >> 16)) {
__asan_report_memory_origin_heap(addr, size);
@ -898,7 +898,7 @@ dontdiscard static __asan_die_f *__asan_report(const void *addr, int size,
}
*p++ = '\n';
}
p = __asan_format_section(p, _base, _etext, ".text", addr);
p = __asan_format_section(p, __executable_start, _etext, ".text", addr);
p = __asan_format_section(p, _etext, _edata, ".data", addr);
p = __asan_format_section(p, _end, _edata, ".bss", addr);
__mmi_lock();
@ -1487,7 +1487,7 @@ void __asan_init(int argc, char **argv, char **envp, intptr_t *auxv) {
REQUIRE(dlmalloc_usable_size);
}
__asan_shadow_existing_mappings();
__asan_map_shadow((uintptr_t)_base, _end - _base);
__asan_map_shadow((uintptr_t)__executable_start, _end - __executable_start);
__asan_map_shadow(0, 4096);
__asan_poison(0, GUARDSIZE, kAsanNullPage);
if (!IsWindows()) {

3
libc/intrin/assertfail.greg.c
View file

@ -20,6 +20,7 @@
#include "libc/atomic.h"
#include "libc/calls/state.internal.h"
#include "libc/calls/syscall-sysv.internal.h"
#include "libc/errno.h"
#include "libc/intrin/atomic.h"
#include "libc/intrin/kprintf.h"
#include "libc/intrin/weaken.h"
@ -38,7 +39,7 @@ relegated void __assert_fail(const char *expr, const char *file, int line) {
owner = 0;
me = sys_gettid();
pthread_setcancelstate(PTHREAD_CANCEL_DISABLE, 0);
kprintf("%s:%d: assert(%s) failed (tid %d)\n", file, line, expr, me);
kprintf("%s:%d: assert(%s) failed (tid %d) %m\n", file, line, expr, me);
if (__vforked ||
atomic_compare_exchange_strong_explicit(
&once, &owner, me, memory_order_relaxed, memory_order_relaxed)) {

2
libc/intrin/describeframe.c
View file

@ -66,7 +66,7 @@ static const char *GetFrameName(int x) {
sizeof(struct WinArgs) - 1) >>
16))) {
return "winargs";
} else if ((int)((intptr_t)_base >> 16) <= x &&
} else if ((int)((intptr_t)__executable_start >> 16) <= x &&
x <= (int)(((intptr_t)_end - 1) >> 16)) {
return "image";
} else {

4
libc/intrin/directmap.c
View file

@ -62,9 +62,11 @@ struct DirectMap sys_mmap(void *addr, size_t size, int prot, int flags, int fd,
register long res_x0 asm("x0");
long res;
asm volatile("mov\tx8,%1\n\t"
"mov\tx16,%2\n\t"
"svc\t0"
: "=r"(res_x0)
: "i"(222), "r"(r0), "r"(r1), "r"(r2), "r"(r3), "r"(r4), "r"(r5)
: "i"(222), "i"(197), "r"(r0), "r"(r1), "r"(r2), "r"(r3),
"r"(r4), "r"(r5)
: "x8", "memory");
res = res_x0;
if ((unsigned long)res >= (unsigned long)-4095) {

5
libc/intrin/exit.c
View file

@ -68,10 +68,11 @@ wontreturn void _Exit(int exitcode) {
#elif defined(__aarch64__)
register long x0 asm("x0") = exitcode;
asm volatile("mov\tx8,%0\n\t"
"mov\tx16,%1\n\t"
"svc\t0"
: /* no outputs */
: "i"(94), "r"(x0)
: "x8", "memory");
: "i"(94), "i"(1), "r"(x0)
: "x8", "x16", "memory");
notpossible;
#else
#error "arch unsupported"

3
libc/intrin/exit1.greg.c
View file

@ -76,9 +76,10 @@ privileged wontreturn void _Exit1(int rc) {
#elif defined(__aarch64__)
register long r0 asm("x0") = rc;
asm volatile("mov\tx8,%0\n\t"
"mov\tx16,%1\n\t"
"svc\t0"
: /* no outputs */
: "i"(93), "r"(r0)
: "i"(93), "i"(0x169), "r"(r0)
: "x8", "memory");
notpossible;
#else

11
libc/intrin/kprintf.greg.c
View file

@ -130,11 +130,13 @@ privileged static inline bool kiskernelpointer(const void *p) {
}
privileged static inline bool kistextpointer(const void *p) {
return _base <= (const unsigned char *)p && (const unsigned char *)p < _etext;
return __executable_start <= (const unsigned char *)p &&
(const unsigned char *)p < _etext;
}
privileged static inline bool kisimagepointer(const void *p) {
return _base <= (const unsigned char *)p && (const unsigned char *)p < _end;
return __executable_start <= (const unsigned char *)p &&
(const unsigned char *)p < _end;
}
privileged static inline bool kischarmisaligned(const char *p, signed char t) {
@ -224,11 +226,12 @@ privileged static void klog(const char *b, size_t n) {
register long r0 asm("x0") = (long)2;
register long r1 asm("x1") = (long)b;
register long r2 asm("x2") = (long)n;
register long r8 asm("x8") = (long)__NR_write;
register long r8 asm("x8") = (long)__NR_write & 0x7ff;
register long r16 asm("x16") = (long)__NR_write & 0x7ff;
register long res_x0 asm("x0");
asm volatile("svc\t0"
: "=r"(res_x0)
: "r"(r0), "r"(r1), "r"(r2), "r"(r8)
: "r"(r0), "r"(r1), "r"(r2), "r"(r8), "r"(r16)
: "memory");
#else
#error "unsupported architecture"

8
libc/intrin/nopl.internal.h
View file

@ -20,7 +20,7 @@
#define _NOPL_PROLOGUE(SECTION) \
".section \".sort.rodata." SECTION ".1" \
"\",\"aG\",@progbits,\"" SECTION "\",comdat\n\t" \
".align\t4\n\t" \
".balign\t4\n\t" \
".type\t\"" SECTION "_start\",@object\n\t" \
".globl\t\"" SECTION "_start\"\n\t" \
".equ\t\"" SECTION "_start\",.\n\t" \
@ -29,7 +29,7 @@
#define _NOPL_EPILOGUE(SECTION) \
".section \".sort.rodata." SECTION ".3" \
"\",\"aG\",@progbits,\"" SECTION "\",comdat\n\t" \
".align\t4\n\t" \
".balign\t4\n\t" \
".type\"" SECTION "_end\",@object\n\t" \
".globl\t\"" SECTION "_end\"\n\t" \
".equ\t\"" SECTION "_end\",.\n\t" \
@ -40,7 +40,7 @@
asm volatile(_NOPL_PROLOGUE(SECTION) /* */ \
_NOPL_EPILOGUE(SECTION) /* */ \
".section \".sort.rodata." SECTION ".2\",\"a\",@progbits\n\t" \
".align\t4\n\t" \
".balign\t4\n\t" \
".long\t353f-%a1\n\t" \
".previous\n353:\t" \
"nopl\t%a0" \
@ -57,7 +57,7 @@
asm volatile(_NOPL_PROLOGUE(SECTION) /* */ \
_NOPL_EPILOGUE(SECTION) /* */ \
".section \".sort.rodata." SECTION ".2\",\"a\",@progbits\n\t" \
".align\t4\n\t" \
".balign\t4\n\t" \
".long\t353f-%a2\n\t" \
".previous\n353:\t" \
"nopl\t%a1" \

1
libc/intrin/stracef.greg.c
View file

@ -19,6 +19,7 @@
#include "libc/intrin/kprintf.h"
#include "libc/intrin/strace.internal.h"
#include "libc/runtime/runtime.h"
#include "libc/thread/tls.h"
#include "libc/thread/tls2.h"
privileged void __stracef(const char *fmt, ...) {

3
libc/intrin/sys_gettid.greg.c
View file

@ -65,9 +65,10 @@ privileged int sys_gettid(void) {
#elif defined(__aarch64__)
register long res_x0 asm("x0");
asm volatile("mov\tx8,%1\n\t"
"mov\tx16,%2\n\t"
"svc\t0"
: "=r"(res_x0)
: "i"(178)
: "i"(178), "i"(186)
: "x8", "memory");
return res_x0;
#else