mirror of
https://github.com/jart/cosmopolitan.git
synced 2025-06-27 23:08:31 +00:00
Make more improvements
This change includes many bug fixes, for the NT polyfills, strings, memory, boot, and math libraries which were discovered by adding more tools for recreational programming, such as PC emulation. Lemon has also been vendored because it works so well at parsing languages.
This commit is contained in:
Justine Tunney
parent
416fd86676
commit
23d333c090
201 changed files with 14558 additions and 3082 deletions
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@ -36,12 +36,6 @@ static const char kFpuName[][8][8] = {
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{"fneni", "fndisi", "fnclex", "fninit", "fnsetpm"},
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};
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char *DisOpFpu0(struct XedDecodedInst *x, int group) {
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const char *s;
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s = kFpuName[group][ModrmRm(x->op.rde)];
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return *s ? s : UNKNOWN;
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}
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char *DisOpFpu1(struct XedDecodedInst *x, char *p, const char *extra) {
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stpcpy(stpcpy(p, kFpuName[0][ModrmReg(x->op.rde)]), extra);
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return p;
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@ -88,68 +82,88 @@ char *DisOpVpsWpsVssWssVpdWpdVsdWsd(struct XedDecodedInst *x, char *p,
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return p;
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}
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const char *DisSpecFpu0(struct XedDecodedInst *x, int group) {
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const char *s;
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s = kFpuName[group][ModrmRm(x->op.rde)];
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return *s ? s : UNKNOWN;
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}
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const char *DisSpecRegMem(struct XedDecodedInst *x, const char *a,
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const char *b) {
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if (IsModrmRegister(x->op.rde)) {
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return a;
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} else {
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return b;
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}
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}
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const char *DisSpecRegMemFpu0(struct XedDecodedInst *x, int group,
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const char *b) {
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return DisSpecRegMem(x, DisSpecFpu0(x, group), b);
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}
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const char *DisSpecMap0(struct XedDecodedInst *x, char *p) {
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switch (x->op.opcode & 0xff) {
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RCASE(0x00, "add Eb %Gb");
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RCASE(0x01, "add Evqp %Gvqp");
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RCASE(0x02, "add %Gb Eb");
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RCASE(0x03, "add %Gvqp Evqp");
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RCASE(0x04, "add %al Ib");
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RCASE(0x05, "add %rAX Ivds");
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RCASE(0x00, "ALU Eb %Gb");
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RCASE(0x01, "ALU Evqp %Gvqp");
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RCASE(0x02, "ALU %Gb Eb");
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RCASE(0x03, "ALU %Gvqp Evqp");
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RCASE(0x04, "ALU %al Ib");
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RCASE(0x05, "ALU %rAX Ivds");
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RCASE(0x06, "push %es");
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RCASE(0x07, "pop %es");
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RCASE(0x08, "or Eb %Gb");
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RCASE(0x09, "or Evqp %Gvqp");
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RCASE(0x0a, "or %Gb Eb");
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RCASE(0x0b, "or %Gvqp Evqp");
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RCASE(0x0c, "or %al Ib");
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RCASE(0x0d, "or %rAX Ivds");
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RCASE(0x08, "ALU Eb %Gb");
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RCASE(0x09, "ALU Evqp %Gvqp");
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RCASE(0x0a, "ALU %Gb Eb");
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RCASE(0x0b, "ALU %Gvqp Evqp");
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RCASE(0x0c, "ALU %al Ib");
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RCASE(0x0d, "ALU %rAX Ivds");
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RCASE(0x0e, "push %cs");
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RCASE(0x0f, "pop %cs");
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RCASE(0x10, "adc Eb %Gb");
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RCASE(0x11, "adc Evqp %Gvqp");
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RCASE(0x12, "adc %Gb Eb");
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RCASE(0x13, "adc %Gvqp Evqp");
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RCASE(0x14, "adc %al Ib");
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RCASE(0x15, "adc %rAX Ivds");
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RCASE(0x10, "ALU Eb %Gb");
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RCASE(0x11, "ALU Evqp %Gvqp");
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RCASE(0x12, "ALU %Gb Eb");
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RCASE(0x13, "ALU %Gvqp Evqp");
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RCASE(0x14, "ALU %al Ib");
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RCASE(0x15, "ALU %rAX Ivds");
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RCASE(0x16, "push %ss");
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RCASE(0x17, "pop %ss");
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RCASE(0x18, "sbb Eb %Gb");
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RCASE(0x19, "sbb Evqp %Gvqp");
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RCASE(0x1a, "sbb %Gb Eb");
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RCASE(0x1b, "sbb %Gvqp Evqp");
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RCASE(0x1c, "sbb %al Ib");
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RCASE(0x1d, "sbb %rAX Ivds");
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RCASE(0x18, "ALU Eb %Gb");
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RCASE(0x19, "ALU Evqp %Gvqp");
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RCASE(0x1a, "ALU %Gb Eb");
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RCASE(0x1b, "ALU %Gvqp Evqp");
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RCASE(0x1c, "ALU %al Ib");
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RCASE(0x1d, "ALU %rAX Ivds");
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RCASE(0x1e, "push %ds");
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RCASE(0x1f, "pop %ds");
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RCASE(0x20, "and Eb %Gb");
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RCASE(0x21, "and Evqp %Gvqp");
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RCASE(0x22, "and %Gb Eb");
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RCASE(0x23, "and %Gvqp Evqp");
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RCASE(0x24, "and %al Ib");
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RCASE(0x25, "and %rAX Ivds");
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RCASE(0x20, "ALU Eb %Gb");
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RCASE(0x21, "ALU Evqp %Gvqp");
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RCASE(0x22, "ALU %Gb Eb");
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RCASE(0x23, "ALU %Gvqp Evqp");
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RCASE(0x24, "ALU %al Ib");
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RCASE(0x25, "ALU %rAX Ivds");
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RCASE(0x26, "push %es");
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RCASE(0x27, "pop %es");
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RCASE(0x28, "sub Eb %Gb");
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RCASE(0x29, "sub Evqp %Gvqp");
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RCASE(0x28, "ALU Eb %Gb");
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RCASE(0x29, "ALU Evqp %Gvqp");
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RCASE(0x2a, "ALU %Gb Eb");
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RCASE(0x2b, "ALU %Gvqp Evqp");
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RCASE(0x2c, "ALU %al Ib");
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RCASE(0x2d, "ALU %rAX Ivds");
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RCASE(0x2F, "das");
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RCASE(0x2a, "sub %Gb Eb");
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RCASE(0x2b, "sub %Gvqp Evqp");
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RCASE(0x2c, "sub %al Ib");
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RCASE(0x2d, "sub %rAX Ivds");
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RCASE(0x30, "xor Eb %Gb");
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RCASE(0x31, "xor Evqp %Gvqp");
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RCASE(0x32, "xor %Gb Eb");
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RCASE(0x33, "xor %Gvqp Evqp");
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RCASE(0x34, "xor %al Ib");
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RCASE(0x35, "xor %rAX Ivds");
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RCASE(0x30, "ALU Eb %Gb");
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RCASE(0x31, "ALU Evqp %Gvqp");
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RCASE(0x32, "ALU %Gb Eb");
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RCASE(0x33, "ALU %Gvqp Evqp");
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RCASE(0x34, "ALU %al Ib");
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RCASE(0x35, "ALU %rAX Ivds");
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RCASE(0x37, "aaa");
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RCASE(0x38, "cmp Eb %Gb");
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RCASE(0x39, "cmp Evqp %Gvqp");
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RCASE(0x3A, "cmp %Gb Eb");
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RCASE(0x3B, "cmp %Gvqp Evqp");
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RCASE(0x3C, "cmp %al Ib");
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RCASE(0x3D, "cmp %rAX Ivds");
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RCASE(0x38, "ALU Eb %Gb");
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RCASE(0x39, "ALU Evqp %Gvqp");
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RCASE(0x3A, "ALU %Gb Eb");
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RCASE(0x3B, "ALU %Gvqp Evqp");
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RCASE(0x3C, "ALU %al Ib");
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RCASE(0x3D, "ALU %rAX Ivds");
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RCASE(0x3F, "aas");
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RCASE(0x40 ... 0x47, "inc %Zv");
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RCASE(0x48 ... 0x4f, "dec %Zv");
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@ -167,26 +181,11 @@ const char *DisSpecMap0(struct XedDecodedInst *x, char *p) {
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RCASE(0x6D, "insWL Yv %dx");
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RCASE(0x6E, "outsb %dx Xb");
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RCASE(0x6F, "outsWL %dx Xv");
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RCASE(0x70, "joBT Jbs");
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RCASE(0x71, "jnoBT Jbs");
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RCASE(0x72, "jbBT Jbs");
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RCASE(0x73, "jaeBT Jbs");
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RCASE(0x74, "jeBT Jbs");
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RCASE(0x75, "jneBT Jbs");
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RCASE(0x76, "jbeBT Jbs");
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RCASE(0x77, "jaBT Jbs");
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RCASE(0x78, "jsBT Jbs");
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RCASE(0x79, "jnsBT Jbs");
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RCASE(0x7a, "jpBT Jbs");
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RCASE(0x7b, "jnpBT Jbs");
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RCASE(0x7c, "jlBT Jbs");
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RCASE(0x7d, "jgeBT Jbs");
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RCASE(0x7e, "jleBT Jbs");
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RCASE(0x7f, "jgBT Jbs");
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RCASE(0x80, "ALU Eb Ib");
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RCASE(0x81, "ALU Evqp Ivds");
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RCASE(0x82, "ALU Eb Ib");
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RCASE(0x83, "ALU Evqp Ibs");
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RCASE(0x70 ... 0x7f, "jCC Jbs");
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RCASE(0x80, "ALU2 Eb Ib");
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RCASE(0x81, "ALU2 Evqp Ivds");
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RCASE(0x82, "ALU2 Eb Ib");
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RCASE(0x83, "ALU2 Evqp Ibs");
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RCASE(0x84, "test Eb %Gb");
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RCASE(0x85, "test %Gvqp Evqp");
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RCASE(0x86, "xchg %Gb Eb");
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@ -202,6 +201,7 @@ const char *DisSpecMap0(struct XedDecodedInst *x, char *p) {
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RCASE(0x91 ... 0x97, "xchg %Zvqp %rAX");
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RCASE(0x98, "cwtl");
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RCASE(0x99, "cltd");
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RCASE(0x9A, "lcall Pvds Kvds");
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RCASE(0x9B, "fwait");
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RCASE(0x9C, "pushfWQ");
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RCASE(0x9D, "popfWQ");
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@ -234,6 +234,8 @@ const char *DisSpecMap0(struct XedDecodedInst *x, char *p) {
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RCASE(0xC6, "mov Eb Ib");
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RCASE(0xC7, "mov Evqp Ivds");
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RCASE(0xC9, "leave");
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RCASE(0xCA, "lret Iw");
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RCASE(0xCB, "lret");
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RCASE(0xCC, "int3");
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RCASE(0xCD, "int Ib");
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RCASE(0xD0, "BIT Eb $1");
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@ -280,163 +282,36 @@ const char *DisSpecMap0(struct XedDecodedInst *x, char *p) {
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switch (ModrmReg(x->op.rde)) {
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RCASE(1, "fxch EST1");
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RCASE(3, "fstps Msr %st");
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case 0:
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if (IsModrmRegister(x->op.rde)) {
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return "fld EST";
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} else {
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return "flds Msr";
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}
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break;
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case 2:
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if (IsModrmRegister(x->op.rde)) {
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return "fnop";
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} else {
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return "fsts Msr %st";
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}
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break;
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case 4:
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if (IsModrmRegister(x->op.rde)) {
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return DisOpFpu0(x, 1);
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} else {
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return "fldenv Me";
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}
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break;
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case 5:
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if (IsModrmRegister(x->op.rde)) {
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return DisOpFpu0(x, 2);
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} else {
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return "fldcw Mw";
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}
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break;
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case 6:
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if (IsModrmRegister(x->op.rde)) {
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return DisOpFpu0(x, 3);
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} else {
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return "fnstenv M";
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}
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break;
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case 7:
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if (IsModrmRegister(x->op.rde)) {
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return DisOpFpu0(x, 4);
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} else {
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return "fnstcw Mw";
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}
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break;
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RCASE(0, DisSpecRegMem(x, "fld EST", "flds Msr"));
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RCASE(2, DisSpecRegMem(x, "fnop", "fsts Msr %st"));
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RCASE(4, DisSpecRegMemFpu0(x, 1, "fldenv Me"));
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RCASE(5, DisSpecRegMemFpu0(x, 2, "fldcw Mw"));
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RCASE(6, DisSpecRegMemFpu0(x, 3, "fnstenv M"));
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RCASE(7, DisSpecRegMemFpu0(x, 4, "fnstcw Mw"));
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}
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break;
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case 0xDA:
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switch (ModrmReg(x->op.rde)) {
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case 0:
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if (!IsModrmRegister(x->op.rde)) {
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return "fiaddl Mdi";
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} else {
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return "fcmovb %st EST";
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}
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break;
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case 1:
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if (!IsModrmRegister(x->op.rde)) {
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return "fimull Mdi";
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} else {
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return "fcmove %st EST";
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}
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break;
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case 2:
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if (!IsModrmRegister(x->op.rde)) {
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return "ficoml Mdi";
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} else {
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return "fcmovbe %st EST";
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}
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break;
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case 3:
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if (!IsModrmRegister(x->op.rde)) {
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return "ficompl Mdi";
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} else {
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return "fcmovu %st EST";
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}
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break;
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case 4:
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if (!IsModrmRegister(x->op.rde)) {
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return "fisubl Mdi";
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} else {
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return "fisubr Mdi";
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}
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break;
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case 5:
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if (!IsModrmRegister(x->op.rde)) {
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return "fisubrl Mdi";
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} else {
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return "fucompp";
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}
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break;
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case 6:
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if (!IsModrmRegister(x->op.rde)) {
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return "fidivl Mdi";
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} else {
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return UNKNOWN;
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}
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break;
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case 7:
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if (!IsModrmRegister(x->op.rde)) {
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return "fidivrl Mdi";
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} else {
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return UNKNOWN;
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}
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break;
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RCASE(0, DisSpecRegMem(x, "fcmovb %st EST", "fiaddl Mdi"));
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RCASE(1, DisSpecRegMem(x, "fcmove %st EST", "fimull Mdi"));
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RCASE(2, DisSpecRegMem(x, "fcmovbe %st EST", "ficoml Mdi"));
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RCASE(3, DisSpecRegMem(x, "fcmovu %st EST", "ficompl Mdi"));
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RCASE(4, DisSpecRegMem(x, "fisubr Mdi", "fisubl Mdi"));
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RCASE(5, DisSpecRegMem(x, "fucompp", "fisubrl Mdi"));
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RCASE(6, DisSpecRegMem(x, "fidivl Mdi", "UNKNOWN"));
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RCASE(7, DisSpecRegMem(x, "fidivrl Mdi", "UNKNOWN"));
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}
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break;
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case 0xDB:
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switch (ModrmReg(x->op.rde)) {
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case 0:
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if (!IsModrmRegister(x->op.rde)) {
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return "fildl Mdi";
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} else {
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return "fcmovnb %st EST";
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}
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break;
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case 1:
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if (!IsModrmRegister(x->op.rde)) {
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return "fisttpl Mdi";
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} else {
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return "fcmovne %st EST";
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}
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break;
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case 2:
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if (!IsModrmRegister(x->op.rde)) {
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return "fistl Mdi";
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} else {
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return "fcmovnbe %st EST";
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}
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break;
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case 3:
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if (!IsModrmRegister(x->op.rde)) {
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return "fistpl Mdi";
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} else {
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return "fcmovnu %st EST";
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}
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break;
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case 4:
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return DisOpFpu0(x, 5);
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case 5:
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if (!IsModrmRegister(x->op.rde)) {
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return "fldt Mer";
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} else {
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return "fucomi %st EST";
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}
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break;
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case 6:
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if (IsModrmRegister(x->op.rde)) {
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return "fcomi %st EST";
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} else {
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return UNKNOWN;
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}
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break;
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case 7:
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if (!IsModrmRegister(x->op.rde)) {
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return "fstpt Mer";
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} else {
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return UNKNOWN;
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}
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break;
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RCASE(0, DisSpecRegMem(x, "fcmovnb %st EST", "fildl Mdi"));
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RCASE(1, DisSpecRegMem(x, "fcmovne %st EST", "fisttpl Mdi"));
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RCASE(2, DisSpecRegMem(x, "fcmovnbe %st EST", "fistl Mdi"));
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RCASE(3, DisSpecRegMem(x, "fcmovnu %st EST", "fistpl Mdi"));
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RCASE(4, DisSpecFpu0(x, 5));
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RCASE(5, DisSpecRegMem(x, "fucomi %st EST", "fldt Mer"));
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RCASE(6, DisSpecRegMem(x, "fcomi %st EST", UNKNOWN));
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RCASE(7, DisSpecRegMem(x, UNKNOWN, "fstpt Mer"));
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}
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break;
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case 0xD8:
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@ -590,22 +465,7 @@ const char *DisSpecMap1(struct XedDecodedInst *x, char *p) {
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RCASE(0x2E, Osz(x->op.rde) ? "ucomisd %Vsd Wsd" : "ucomiss %Vss Wss");
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RCASE(0x2F, Osz(x->op.rde) ? "comisd %Vsd Wsd" : "comiss %Vss Wss");
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||||
RCASE(0x31, "rdtsc");
|
||||
RCASE(0x40, "cmovo %Gvqp Evqp");
|
||||
RCASE(0x41, "cmovno %Gvqp Evqp");
|
||||
RCASE(0x42, "cmovb %Gvqp Evqp");
|
||||
RCASE(0x43, "cmovae %Gvqp Evqp");
|
||||
RCASE(0x44, "cmove %Gvqp Evqp");
|
||||
RCASE(0x45, "cmovne %Gvqp Evqp");
|
||||
RCASE(0x46, "cmovbe %Gvqp Evqp");
|
||||
RCASE(0x47, "cmova %Gvqp Evqp");
|
||||
RCASE(0x48, "cmovs %Gvqp Evqp");
|
||||
RCASE(0x49, "cmovns %Gvqp Evqp");
|
||||
RCASE(0x4a, "cmovp %Gvqp Evqp");
|
||||
RCASE(0x4b, "cmovnp %Gvqp Evqp");
|
||||
RCASE(0x4c, "cmovl %Gvqp Evqp");
|
||||
RCASE(0x4d, "cmovge %Gvqp Evqp");
|
||||
RCASE(0x4e, "cmovle %Gvqp Evqp");
|
||||
RCASE(0x4f, "cmovg %Gvqp Evqp");
|
||||
RCASE(0x40 ... 0x4f, "cmovCC %Gvqp Evqp");
|
||||
RCASE(0x52, DisOpVpsWpsVssWss(x, p, "rsqrt"));
|
||||
RCASE(0x53, DisOpVpsWpsVssWss(x, p, "rcp"));
|
||||
RCASE(0x54, DisOpVpdWpdVpsWps(x, p, "and"));
|
||||
|
|
@ -635,38 +495,8 @@ const char *DisSpecMap1(struct XedDecodedInst *x, char *p) {
|
|||
RCASE(0x74, DisOpPqQqVdqWdq(x, p, "pcmpeqb"));
|
||||
RCASE(0x75, DisOpPqQqVdqWdq(x, p, "pcmpeqw"));
|
||||
RCASE(0x76, DisOpPqQqVdqWdq(x, p, "pcmpeqd"));
|
||||
RCASE(0x80, "jo Jvds");
|
||||
RCASE(0x81, "jno Jvds");
|
||||
RCASE(0x82, "jb Jvds");
|
||||
RCASE(0x83, "jae Jvds");
|
||||
RCASE(0x84, "je Jvds");
|
||||
RCASE(0x85, "jne Jvds");
|
||||
RCASE(0x86, "jbe Jvds");
|
||||
RCASE(0x87, "ja Jvds");
|
||||
RCASE(0x88, "js Jvds");
|
||||
RCASE(0x89, "jns Jvds");
|
||||
RCASE(0x8a, "jp Jvds");
|
||||
RCASE(0x8b, "jnp Jvds");
|
||||
RCASE(0x8c, "jl Jvds");
|
||||
RCASE(0x8d, "jge Jvds");
|
||||
RCASE(0x8e, "jle Jvds");
|
||||
RCASE(0x8f, "jg Jvds");
|
||||
RCASE(0x90, "seto Eb");
|
||||
RCASE(0x91, "setno Eb");
|
||||
RCASE(0x92, "setb Eb");
|
||||
RCASE(0x93, "setnb Eb");
|
||||
RCASE(0x94, "sete Eb");
|
||||
RCASE(0x95, "setne Eb");
|
||||
RCASE(0x96, "setbe Eb");
|
||||
RCASE(0x97, "seta Eb");
|
||||
RCASE(0x98, "sets Eb");
|
||||
RCASE(0x99, "setns Eb");
|
||||
RCASE(0x9A, "setp Eb");
|
||||
RCASE(0x9B, "setnp Eb");
|
||||
RCASE(0x9C, "setl Eb");
|
||||
RCASE(0x9D, "setge Eb");
|
||||
RCASE(0x9E, "setle Eb");
|
||||
RCASE(0x9F, "setg Eb");
|
||||
RCASE(0x80 ... 0x8f, "jCC Jvds");
|
||||
RCASE(0x90 ... 0x9f, "setCC Jvds");
|
||||
RCASE(0xA0, "push %fs");
|
||||
RCASE(0xA1, "pop %fs");
|
||||
RCASE(0xA2, "cpuid");
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue