mirror of
https://github.com/jart/cosmopolitan.git
synced 2025-07-28 13:30:29 +00:00
Get binaries closer to running without an o/s
blinkenlights now does a pretty good job emulating what happens when binaries boot from BIOS into long mode. So it's been much easier to debug the bare metal process and wrinkle out many issues.
This commit is contained in:
Justine Tunney
parent
feed0d2b0e
commit
2d80bbc802
50 changed files with 974 additions and 1062 deletions
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@ -17,7 +17,9 @@
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│ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA │
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│ 02110-1301 USA │
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╚─────────────────────────────────────────────────────────────────────────────*/
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#include "libc/log/check.h"
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#include "libc/macros.h"
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#include "libc/rand/rand.h"
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#include "libc/runtime/runtime.h"
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#include "tool/build/lib/abp.h"
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#include "tool/build/lib/address.h"
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@ -202,14 +204,87 @@ static relegated void OpMovEvqpSw(struct Machine *m, uint32_t rde) {
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Read64(GetSegment(m, rde, ModrmReg(rde))) >> 4);
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}
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static relegated void OpMovSwEvqp(struct Machine *m, uint32_t rde) {
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Write64(GetSegment(m, rde, ModrmReg(rde)),
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ReadMemory(rde, GetModrmRegisterWordPointerReadOszRexw(m, rde)) << 4);
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static relegated int GetDescriptor(struct Machine *m, int selector,
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uint64_t *out_descriptor) {
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uint8_t buf[8];
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DCHECK(m->gdt_base + m->gdt_limit <= m->real.n);
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selector &= -8;
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if (8 <= selector && selector + 8 <= m->gdt_limit) {
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SetReadAddr(m, m->gdt_base + selector, 8);
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*out_descriptor = Read64(m->real.p + m->gdt_base + selector);
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return 0;
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} else {
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return -1;
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}
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}
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static relegated void OpJmpf(struct Machine *m, uint32_t rde) {
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Write64(m->cs, m->xedd->op.uimm0 << 4);
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m->ip = m->xedd->op.disp;
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static uint64_t GetDescriptorBase(uint64_t d) {
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return (d & 0xff00000000000000) >> 32 | (d & 0x000000ffffff0000) >> 16;
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}
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static uint64_t GetDescriptorLimit(uint64_t d) {
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return (d & 0x000f000000000000) >> 32 | d & 0xffff;
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}
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static int GetDescriptorMode(uint64_t d) {
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uint8_t kMode[] = {
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XED_MACHINE_MODE_REAL,
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XED_MACHINE_MODE_LONG_64,
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XED_MACHINE_MODE_LEGACY_32,
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XED_MACHINE_MODE_LONG_64,
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};
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return kMode[(d & 0x0060000000000000) >> 53];
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}
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static bool IsProtectedMode(struct Machine *m) {
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return m->cr0 & 1;
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}
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static relegated void OpMovSwEvqp(struct Machine *m, uint32_t rde) {
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uint64_t x, d;
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x = ReadMemory(rde, GetModrmRegisterWordPointerReadOszRexw(m, rde));
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if (!IsProtectedMode(m)) {
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x <<= 4;
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} else if (GetDescriptor(m, x, &d) != -1) {
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x = GetDescriptorBase(d);
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} else {
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ThrowProtectionFault(m);
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}
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Write64(GetSegment(m, rde, ModrmReg(rde)), x);
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}
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static void OpLsl(struct Machine *m, uint32_t rde) {
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uint64_t descriptor;
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if (GetDescriptor(m, Read16(GetModrmRegisterWordPointerRead2(m, rde)),
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&descriptor) != -1) {
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WriteRegister(rde, RegRexrReg(m, rde), GetDescriptorLimit(descriptor));
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SetFlag(m->flags, FLAGS_ZF, true);
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} else {
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SetFlag(m->flags, FLAGS_ZF, false);
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}
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}
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static void ChangeMachineMode(struct Machine *m, int mode) {
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if (mode == m->mode) return;
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ResetInstructionCache(m);
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m->mode = mode;
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}
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static void OpJmpf(struct Machine *m, uint32_t rde) {
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uint64_t descriptor;
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if (!IsProtectedMode(m)) {
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Write64(m->cs, m->xedd->op.uimm0 << 4);
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m->ip = m->xedd->op.disp;
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} else if (GetDescriptor(m, m->xedd->op.uimm0, &descriptor) != -1) {
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Write64(m->cs, GetDescriptorBase(descriptor));
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m->ip = m->xedd->op.disp;
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ChangeMachineMode(m, GetDescriptorMode(descriptor));
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} else {
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ThrowProtectionFault(m);
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}
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if (m->onlongbranch) {
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m->onlongbranch(m);
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}
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}
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static relegated void OpXlatAlBbb(struct Machine *m, uint32_t rde) {
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@ -373,11 +448,49 @@ static void OpCmpxchg16b(struct Machine *m, uint32_t rde) {
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}
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}
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static void OpCmpxchgDxAx(struct Machine *m, uint32_t rde) {
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if (Rexw(rde)) {
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OpCmpxchg16b(m, rde);
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} else {
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OpCmpxchg8b(m, rde);
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static void OpRdrand(struct Machine *m, uint32_t rde) {
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WriteRegister(rde, RegRexbRm(m, rde), rand64());
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}
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static void OpRdseed(struct Machine *m, uint32_t rde) {
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OpRdrand(m, rde);
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}
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static void Op1c7(struct Machine *m, uint32_t rde) {
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bool ismem;
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ismem = !IsModrmRegister(rde);
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switch (ModrmReg(rde)) {
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case 1:
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if (ismem) {
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if (Rexw(rde)) {
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OpCmpxchg16b(m, rde);
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} else {
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OpCmpxchg8b(m, rde);
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}
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} else {
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OpUd(m, rde);
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}
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break;
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case 6:
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if (!ismem) {
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OpRdrand(m, rde);
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} else {
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OpUd(m, rde);
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}
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break;
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case 7:
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if (!ismem) {
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if (Rep(rde) == 3) {
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OpRdpid(m, rde);
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} else {
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OpRdseed(m, rde);
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}
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} else {
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OpUd(m, rde);
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}
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break;
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default:
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OpUd(m, rde);
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}
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}
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@ -699,8 +812,7 @@ static void OpAlubFlipTest(struct Machine *m, uint32_t rde) {
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}
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static void Alubi(struct Machine *m, uint32_t rde, aluop_f op) {
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uint8_t *a, x;
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a = GetModrmRegisterBytePointerWrite(m, rde);
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uint8_t *a = GetModrmRegisterBytePointerWrite(m, rde);
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Write8(a, op(Read8(a), m->xedd->op.uimm0, &m->flags));
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}
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@ -770,7 +882,6 @@ static void OpAluwFlipTest(struct Machine *m, uint32_t rde) {
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static void Aluwi(struct Machine *m, uint32_t rde, aluop_f ops[4]) {
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uint8_t *a;
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uint64_t x;
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a = GetModrmRegisterWordPointerWriteOszRexw(m, rde);
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WriteRegisterOrMemory(
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rde, a,
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@ -1339,8 +1450,105 @@ static void OpDoubleShift(struct Machine *m, uint32_t rde) {
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m->xedd->op.opcode & 8, &m->flags));
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}
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static void OpFxsave(struct Machine *m, uint32_t rde) {
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int64_t v;
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uint8_t buf[32];
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memset(buf, 0, 32);
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Write16(buf + 0, m->fpu.cw);
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Write16(buf + 2, m->fpu.sw);
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Write8(buf + 4, m->fpu.tw);
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Write16(buf + 6, m->fpu.op);
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Write32(buf + 8, m->fpu.ip);
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Write32(buf + 24, m->sse.mxcsr);
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v = ComputeAddress(m, rde);
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VirtualRecv(m, v + 0, buf, 32);
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VirtualRecv(m, v + 32, m->fpu.st, 128);
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VirtualRecv(m, v + 160, m->xmm, 256);
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SetWriteAddr(m, v, 416);
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}
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static void OpFxrstor(struct Machine *m, uint32_t rde) {
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int64_t v;
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uint8_t buf[32];
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v = ComputeAddress(m, rde);
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SetReadAddr(m, v, 416);
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VirtualSend(m, buf, v + 0, 32);
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VirtualSend(m, m->fpu.st, v + 32, 128);
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VirtualSend(m, m->xmm, v + 160, 256);
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m->fpu.cw = Read16(buf + 0);
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m->fpu.sw = Read16(buf + 2);
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m->fpu.tw = Read8(buf + 4);
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m->fpu.op = Read16(buf + 6);
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m->fpu.ip = Read32(buf + 8);
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m->sse.mxcsr = Read32(buf + 24);
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}
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static void OpXsave(struct Machine *m, uint32_t rde) {
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}
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static void OpLdmxcsr(struct Machine *m, uint32_t rde) {
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m->sse.mxcsr = Read32(ComputeReserveAddressRead4(m, rde));
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}
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static void OpStmxcsr(struct Machine *m, uint32_t rde) {
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Write32(ComputeReserveAddressWrite4(m, rde), m->sse.mxcsr);
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}
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static void OpRdfsbase(struct Machine *m, uint32_t rde) {
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WriteRegister(rde, RegRexbRm(m, rde), Read64(m->fs));
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}
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static void OpRdgsbase(struct Machine *m, uint32_t rde) {
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WriteRegister(rde, RegRexbRm(m, rde), Read64(m->gs));
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}
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static void OpWrfsbase(struct Machine *m, uint32_t rde) {
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Write64(m->fs, ReadMemory(rde, RegRexbRm(m, rde)));
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}
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static void OpWrgsbase(struct Machine *m, uint32_t rde) {
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Write64(m->gs, ReadMemory(rde, RegRexbRm(m, rde)));
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}
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static void Op1ae(struct Machine *m, uint32_t rde) {
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bool ismem;
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ismem = !IsModrmRegister(rde);
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switch (ModrmReg(rde)) {
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case 0:
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if (ismem) {
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OpFxsave(m, rde);
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} else {
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OpRdfsbase(m, rde);
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}
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break;
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case 1:
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if (ismem) {
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OpFxrstor(m, rde);
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} else {
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OpRdgsbase(m, rde);
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}
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break;
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case 2:
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if (ismem) {
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OpLdmxcsr(m, rde);
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} else {
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OpWrfsbase(m, rde);
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}
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break;
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case 3:
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if (ismem) {
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OpStmxcsr(m, rde);
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} else {
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OpWrgsbase(m, rde);
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}
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break;
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case 4:
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if (ismem) {
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OpXsave(m, rde);
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} else {
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OpUd(m, rde);
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}
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break;
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case 5:
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OpLfence(m, rde);
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break;
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@ -1348,10 +1556,10 @@ static void Op1ae(struct Machine *m, uint32_t rde) {
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OpMfence(m, rde);
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break;
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case 7:
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if (ModrmMod(rde) == 0b11 && ModrmReg(rde) == 0b111) {
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OpSfence(m, rde);
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} else {
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if (ismem) {
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OpClflush(m, rde);
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} else {
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OpSfence(m, rde);
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}
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break;
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default:
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@ -1363,11 +1571,32 @@ static void OpSalc(struct Machine *m, uint32_t rde) {
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Write8(m->ax, GetFlag(m->flags, FLAGS_CF));
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}
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static void OpBofram(struct Machine *m, uint32_t rde) {
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if (m->xedd->op.disp) {
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m->bofram[0] = m->ip;
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m->bofram[1] = m->ip + (m->xedd->op.disp & 0xff);
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} else {
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m->bofram[0] = 0;
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m->bofram[1] = 0;
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}
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}
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static void OpBinbase(struct Machine *m, uint32_t rde) {
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if (m->onbinbase) {
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m->onbinbase(m);
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}
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}
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static void OpNopEv(struct Machine *m, uint32_t rde) {
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switch (ModrmMod(rde) << 6 | ModrmReg(rde) << 3 | ModrmRm(rde)) {
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case 0x45:
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case 0105:
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OpBofram(m, rde);
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break;
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case 0007:
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case 0107:
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case 0207:
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OpBinbase(m, rde);
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break;
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default:
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OpNoop(m, rde);
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}
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@ -1421,6 +1650,14 @@ static void OpMovCqRq(struct Machine *m, uint32_t rde) {
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}
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}
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static void OpWrmsr(struct Machine *m, uint32_t rde) {
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}
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static void OpRdmsr(struct Machine *m, uint32_t rde) {
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Write32(m->dx, 0);
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Write32(m->ax, 0);
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}
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static const nexgen32e_f kNexgen32e[] = {
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[0x000] = OpAlubAdd,
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[0x001] = OpAluw,
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@ -1681,7 +1918,7 @@ static const nexgen32e_f kNexgen32e[] = {
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[0x100] = OpUd,
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[0x101] = Op101,
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[0x102] = OpUd,
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[0x103] = OpUd,
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[0x103] = OpLsl,
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[0x104] = OpUd,
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[0x105] = OpSyscall,
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[0x106] = OpUd,
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@ -1708,7 +1945,7 @@ static const nexgen32e_f kNexgen32e[] = {
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[0x11B] = OpHintNopEv,
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[0x11C] = OpHintNopEv,
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[0x11D] = OpHintNopEv,
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[0x11E] = OpUd,
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[0x11E] = OpHintNopEv,
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[0x11F] = OpNopEv,
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[0x120] = OpMovRqCq,
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[0x121] = OpUd,
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@ -1726,9 +1963,9 @@ static const nexgen32e_f kNexgen32e[] = {
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[0x12D] = OpCvt0f2d,
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[0x12E] = OpComissVsWs,
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[0x12F] = OpComissVsWs,
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[0x130] = OpUd,
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[0x130] = OpWrmsr,
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[0x131] = OpRdtsc,
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[0x132] = OpUd,
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[0x132] = OpRdmsr,
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[0x133] = OpUd,
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[0x134] = OpUd,
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[0x135] = OpUd,
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@ -1877,7 +2114,7 @@ static const nexgen32e_f kNexgen32e[] = {
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[0x1C4] = OpPinsrwVdqEwIb,
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[0x1C5] = OpPextrwGdqpUdqIb,
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[0x1C6] = OpShufpsd,
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[0x1C7] = OpCmpxchgDxAx,
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[0x1C7] = Op1c7,
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[0x1C8] = OpBswapZvqp,
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[0x1C9] = OpBswapZvqp,
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[0x1CA] = OpBswapZvqp,
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