mirror of
https://github.com/jart/cosmopolitan.git
synced 2025-02-07 06:53:33 +00:00
Apply touchups to last PR
Compilers like GCC require comments on lines like `#endif rdmsr`. Since the rdmsr macro was only being used in arch_prctl(), I've localized the macro, and I'm considering deleting arch_prctl() too, since there isn't any way to have mem segments unfortunately across operating systems ;_; The remaining changed lines are due to clang-format which runs on auto.
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888cfa74d7
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6 changed files with 159 additions and 135 deletions
21
.vscode/vscode.h
vendored
21
.vscode/vscode.h
vendored
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@ -11,11 +11,11 @@
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#define __INT_MAX__ 0x7FFFFFFF
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#define __LONG_MAX__ 0x7FFFFFFFFFFFFFFF
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#define __LONG_LONG_MAX__ __LONG_MAX__
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#define __CHAR_MIN__ -((__CHAR_MAX__)+1)
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#define __SHRT_MIN__ -((__SHRT_MAX__)+1)
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#define __INT_MIN__ -((__INT_MAX__)+1)
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#define __LONG_MIN__ -((__LONG_MAX__)+1)
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#define __LONG_LONG_MIN__ -((__LONG_LONG_MAX__)+1)
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#define __CHAR_MIN__ -((__CHAR_MAX__) + 1)
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#define __SHRT_MIN__ -((__SHRT_MAX__) + 1)
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#define __INT_MIN__ -((__INT_MAX__) + 1)
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#define __LONG_MIN__ -((__LONG_MAX__) + 1)
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#define __LONG_LONG_MIN__ -((__LONG_LONG_MAX__) + 1)
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#define __UCHAR_MAX__ 0xFF
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#define __USHRT_MAX__ 0xFFFF
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#define __UINT_MAX__ 0xFFFFFFFF
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@ -123,7 +123,7 @@ typedef struct { int ax, dx; } axdx_t;
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/* duplicate and replace xmmintrin.internal.h to fix it for IntelliSense
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* SEE: <> */
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#define _Vector_size(x) __attribute__(( vector_size( x ) ))
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#define _Vector_size(x) __attribute__((__vector_size__(x)))
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#define IMAGE_BASE_VIRTUAL 0x400000
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#define __SIGACTION(...) (0)
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@ -136,9 +136,7 @@ typedef struct { int ax, dx; } axdx_t;
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#define CONCAT(a, b, c, d, e) 0
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#define shuffle(...) 0
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#define reverse(x, y) 0
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#define atomic_load(...) 0
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#define atomic_store(...) 0
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#define autotype(x) int
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#define autotype(x) intptr_t
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#define _Generic_(...) (void*)(0)
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#define _Generic(...) _Generic_
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@ -146,11 +144,6 @@ typedef struct { int ax, dx; } axdx_t;
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#define _Section(...)
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#define offsetof(x, y) 0
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#define cmpxchg(...) 0
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#define lockxchg(...) 0
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#define lockcmpxchg(...) 0
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#define xgetbv(...) 0
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#define rdmsr(...) 0
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#define INITIALIZER(...) struct _dummy
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#define __far
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#define tinystrstr(...) 0
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@ -17,11 +17,10 @@
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│ PERFORMANCE OF THIS SOFTWARE. │
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╚─────────────────────────────────────────────────────────────────────────────*/
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#include "ape/lib/pc.h"
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#include "libc/bits/bits.h"
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textreal void pageunmap(int64_t vaddr) {
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uint64_t *entry;
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entry = __getpagetableentry(vaddr, 3, &g_pml4t, &g_ptsp_xlm);
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*entry &= ~PAGE_V;
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invlpg(vaddr);
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asm volatile("invlpg\t(%0)" : /* no outputs */ : "r"(vaddr) : "memory");
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}
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34
libc/bits/atomic_load.c
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34
libc/bits/atomic_load.c
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@ -0,0 +1,34 @@
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/*-*- mode:c;indent-tabs-mode:nil;c-basic-offset:2;tab-width:8;coding:utf-8 -*-│
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│vi: set net ft=c ts=2 sts=2 sw=2 fenc=utf-8 :vi│
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╞══════════════════════════════════════════════════════════════════════════════╡
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│ Copyright 2021 Justine Alexandra Roberts Tunney │
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│ │
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│ Permission to use, copy, modify, and/or distribute this software for │
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│ any purpose with or without fee is hereby granted, provided that the │
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│ above copyright notice and this permission notice appear in all copies. │
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│ │
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│ THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL │
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│ WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED │
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│ WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE │
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│ AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL │
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│ DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR │
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│ PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER │
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│ TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR │
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│ PERFORMANCE OF THIS SOFTWARE. │
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╚─────────────────────────────────────────────────────────────────────────────*/
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#include "libc/bits/bits.h"
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#include "libc/macros.h"
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#include "libc/str/str.h"
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/**
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* Atomically loads value.
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*
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* This macro is intended to prevent things like compiler load tearing
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* optimizations.
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*/
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intptr_t(atomic_load)(void *p, size_t n) {
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intptr_t x;
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x = 0;
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memcpy(&x, p, MAX(n, sizeof(x)));
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return x;
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}
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32
libc/bits/atomic_store.c
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32
libc/bits/atomic_store.c
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@ -0,0 +1,32 @@
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/*-*- mode:c;indent-tabs-mode:nil;c-basic-offset:2;tab-width:8;coding:utf-8 -*-│
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│vi: set net ft=c ts=2 sts=2 sw=2 fenc=utf-8 :vi│
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╞══════════════════════════════════════════════════════════════════════════════╡
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│ Copyright 2021 Justine Alexandra Roberts Tunney │
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│ │
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│ Permission to use, copy, modify, and/or distribute this software for │
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│ any purpose with or without fee is hereby granted, provided that the │
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│ above copyright notice and this permission notice appear in all copies. │
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│ │
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│ THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL │
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│ WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED │
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│ WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE │
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│ AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL │
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│ DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR │
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│ PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER │
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│ TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR │
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│ PERFORMANCE OF THIS SOFTWARE. │
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╚─────────────────────────────────────────────────────────────────────────────*/
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#include "libc/bits/bits.h"
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#include "libc/macros.h"
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#include "libc/str/str.h"
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/**
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* Atomically stores value.
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*
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* This macro is intended to prevent things like compiler store tearing
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* optimizations.
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*/
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intptr_t(atomic_store)(void *p, intptr_t x, size_t n) {
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memcpy(p, &x, MAX(n, sizeof(x)));
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return x;
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}
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@ -24,6 +24,8 @@ unsigned long hamming(unsigned long, unsigned long) pureconst;
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intptr_t lockxchg(void *, void *, size_t);
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bool cmpxchg(void *, intptr_t, intptr_t, size_t);
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bool lockcmpxchg(void *, intptr_t, intptr_t, size_t);
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intptr_t atomic_load(void *, size_t);
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intptr_t atomic_store(void *, intptr_t, size_t);
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/*───────────────────────────────────────────────────────────────────────────│─╗
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│ cosmopolitan § bits » no assembly required ─╬─│┼
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* @see Intel's Six-Thousand Page Manual V.3A §8.2.3.1
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* @see atomic_store()
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*/
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#ifndef atomic_load
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#define atomic_load(MEM) \
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({ \
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autotype(MEM) Mem = (MEM); \
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asm("mov\t%1,%0" : "=r"(Reg) : "m"(*Mem)); \
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Reg; \
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})
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#endif /* atomic_load */
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/**
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* Saves scalar to memory w/ one operation.
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* @see Intel Six-Thousand Page Manual Manual V.3A §8.2.3.1
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* @see atomic_load()
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*/
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#ifndef atomic_store
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#define atomic_store(MEM, VAL) \
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({ \
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autotype(VAL) Val = (VAL); \
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asm("mov%z1\t%1,%0" : "=m"(*Mem) : "r"(Val)); \
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Val; \
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})
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#endif /* atomic_store */
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#define bts(MEM, BIT) __BitOp("bts", BIT, MEM) /** bit test and set */
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#define btr(MEM, BIT) __BitOp("btr", BIT, MEM) /** bit test and reset */
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* @return LOCALVAR[0]
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* @see xchg()
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*/
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#ifndef lockxchg
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#define lockxchg(MEMORY, LOCALVAR) \
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({ \
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_Static_assert( \
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asm("xchg\t%0,%1" : "+%m"(*(MEMORY)), "+r"(*(LOCALVAR))); \
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*(LOCALVAR); \
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})
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#endif /* lockxchg */
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/**
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* Compares and exchanges.
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* @return true if value was exchanged, otherwise false
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* @see lockcmpxchg()
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*/
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#ifndef cmpxchg
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#define cmpxchg(IFTHING, ISEQUALTOME, REPLACEITWITHME) \
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({ \
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bool DidIt; \
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: "cc"); \
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DidIt; \
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})
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#endif /* cmpxchg */
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/**
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* Compares and exchanges w/ one operation.
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* @return true if value was exchanged, otherwise false
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* @see lockcmpxchg()
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*/
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#ifndef lockcmpxchg
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#define lockcmpxchg(IFTHING, ISEQUALTOME, REPLACEITWITHME) \
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({ \
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bool DidIt; \
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: "cc"); \
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DidIt; \
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})
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#endif /* lockcmpxchg */
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/**
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* Gets value of extended control register.
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*/
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#ifndef xgetbv
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#define xgetbv(xcr_register_num) \
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({ \
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unsigned hi, lo; \
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asm("xgetbv" : "=d"(hi), "=a"(lo) : "c"(cr_register_num)); \
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(uint64_t) hi << 32 | lo; \
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})
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#endif /* xgetbv */
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/**
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* Reads model-specific register.
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* @note programs running as guests won't have authorization
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*/
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#ifndef rdmsr
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#define rdmsr(msr) \
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({ \
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uint32_t lo, hi; \
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asm volatile("rdmsr" : "=a"(lo), "=d"(hi) : "c"(msr)); \
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(uint64_t) hi << 32 | lo; \
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})
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#endif rdmsr
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/**
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* Writes model-specific register.
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* @note programs running as guests won't have authorization
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*/
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#define wrmsr(msr, val) \
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do { \
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uint64_t val_ = (val); \
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asm volatile("wrmsr" \
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: /* no outputs */ \
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: "c"(msr), "a"((uint32_t)val_), \
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"d"((uint32_t)(val_ >> 32))); \
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} while (0)
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/**
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* Tells CPU page tables changed for virtual address.
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* @note programs running as guests won't have authorization
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*/
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#define invlpg(MEM) \
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asm volatile("invlpg\t(%0)" : /* no outputs */ : "r"(MEM) : "memory")
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#define IsAddressCanonicalForm(P) \
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({ \
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lockcmpxchg(MEM, (intptr_t)(CMP), (intptr_t)(VAL), sizeof(*(MEM)))
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#define lockxchg(MEM, VAR) \
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lockxchg(MEM, VAR, sizeof(*(MEM)) / (sizeof(*(MEM)) == sizeof(*(VAR))))
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#define atomic_store(MEM, VAL) \
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atomic_store(MEM, VAL, sizeof(*(MEM)) / (sizeof(*(MEM)) == sizeof(*(VAL))))
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#define atomic_load(MEM) atomic_load(MEM, sizeof(*(MEM)))
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#endif /* __GNUC__ && !__STRICT_ANSI__ */
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COSMOPOLITAN_C_END_
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#endif /* !(__ASSEMBLER__ + __LINKER__ + 0) */
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* operating systems.
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*/
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#define rdmsr(msr) \
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({ \
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uint32_t lo, hi; \
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asm volatile("rdmsr" : "=a"(lo), "=d"(hi) : "c"(msr)); \
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(uint64_t) hi << 32 | lo; \
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})
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#define wrmsr(msr, val) \
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do { \
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uint64_t val_ = (val); \
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asm volatile("wrmsr" \
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: /* no outputs */ \
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: "c"(msr), "a"((uint32_t)val_), \
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"d"((uint32_t)(val_ >> 32))); \
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} while (0)
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int sys_arch_prctl(int, int64_t) hidden;
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static inline int arch_prctl_fsgsbase(int code, int64_t addr) {
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