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Add Intel intrinsics headers
This commit is contained in:
Justine Tunney
parent
369f9740de
commit
b7bf052a4b
121 changed files with 47114 additions and 849 deletions
213
third_party/intel/avx512bitalgintrin.internal.h
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213
third_party/intel/avx512bitalgintrin.internal.h
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#if !defined _IMMINTRIN_H_INCLUDED
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#error \
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"Never use <avx512bitalgintrin.h> directly; include <x86intrin.h> instead."
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#endif
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#ifndef _AVX512BITALGINTRIN_H_INCLUDED
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#define _AVX512BITALGINTRIN_H_INCLUDED
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#ifndef __AVX512BITALG__
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#pragma GCC push_options
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#pragma GCC target("avx512bitalg")
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#define __DISABLE_AVX512BITALG__
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#endif /* __AVX512BITALG__ */
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extern __inline __m512i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_popcnt_epi8(__m512i __A) {
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return (__m512i)__builtin_ia32_vpopcountb_v64qi((__v64qi)__A);
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}
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extern __inline __m512i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_popcnt_epi16(__m512i __A) {
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return (__m512i)__builtin_ia32_vpopcountw_v32hi((__v32hi)__A);
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}
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#ifdef __DISABLE_AVX512BITALG__
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#undef __DISABLE_AVX512BITALG__
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#pragma GCC pop_options
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#endif /* __DISABLE_AVX512BITALG__ */
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#if !defined(__AVX512BITALG__) || !defined(__AVX512BW__)
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#pragma GCC push_options
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#pragma GCC target("avx512bitalg,avx512bw")
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#define __DISABLE_AVX512BITALGBW__
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#endif /* __AVX512VLBW__ */
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extern __inline __m512i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_mask_popcnt_epi8(__m512i __A, __mmask64 __U, __m512i __B) {
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return (__m512i)__builtin_ia32_vpopcountb_v64qi_mask(
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(__v64qi)__A, (__v64qi)__B, (__mmask64)__U);
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}
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extern __inline __m512i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_maskz_popcnt_epi8(__mmask64 __U, __m512i __A) {
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return (__m512i)__builtin_ia32_vpopcountb_v64qi_mask(
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(__v64qi)__A, (__v64qi)_mm512_setzero_si512(), (__mmask64)__U);
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}
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extern __inline __m512i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_mask_popcnt_epi16(__m512i __A, __mmask32 __U, __m512i __B) {
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return (__m512i)__builtin_ia32_vpopcountw_v32hi_mask(
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(__v32hi)__A, (__v32hi)__B, (__mmask32)__U);
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}
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extern __inline __m512i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_maskz_popcnt_epi16(__mmask32 __U, __m512i __A) {
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return (__m512i)__builtin_ia32_vpopcountw_v32hi_mask(
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(__v32hi)__A, (__v32hi)_mm512_setzero_si512(), (__mmask32)__U);
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}
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extern __inline __mmask64
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_bitshuffle_epi64_mask(__m512i __A, __m512i __B) {
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return (__mmask64)__builtin_ia32_vpshufbitqmb512_mask(
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(__v64qi)__A, (__v64qi)__B, (__mmask64)-1);
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}
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extern __inline __mmask64
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_mask_bitshuffle_epi64_mask(__mmask64 __M, __m512i __A, __m512i __B) {
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return (__mmask64)__builtin_ia32_vpshufbitqmb512_mask(
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(__v64qi)__A, (__v64qi)__B, (__mmask64)__M);
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}
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#ifdef __DISABLE_AVX512BITALGBW__
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#undef __DISABLE_AVX512BITALGBW__
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#pragma GCC pop_options
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#endif /* __DISABLE_AVX512BITALGBW__ */
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#if !defined(__AVX512BITALG__) || !defined(__AVX512VL__) || \
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!defined(__AVX512BW__)
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#pragma GCC push_options
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#pragma GCC target("avx512bitalg,avx512vl,avx512bw")
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#define __DISABLE_AVX512BITALGVLBW__
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#endif /* __AVX512VLBW__ */
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extern __inline __m256i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_mask_popcnt_epi8(__m256i __A, __mmask32 __U, __m256i __B) {
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return (__m256i)__builtin_ia32_vpopcountb_v32qi_mask(
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(__v32qi)__A, (__v32qi)__B, (__mmask32)__U);
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}
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extern __inline __m256i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_maskz_popcnt_epi8(__mmask32 __U, __m256i __A) {
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return (__m256i)__builtin_ia32_vpopcountb_v32qi_mask(
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(__v32qi)__A, (__v32qi)_mm256_setzero_si256(), (__mmask32)__U);
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}
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extern __inline __mmask32
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_bitshuffle_epi64_mask(__m256i __A, __m256i __B) {
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return (__mmask32)__builtin_ia32_vpshufbitqmb256_mask(
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(__v32qi)__A, (__v32qi)__B, (__mmask32)-1);
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}
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extern __inline __mmask32
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_mask_bitshuffle_epi64_mask(__mmask32 __M, __m256i __A, __m256i __B) {
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return (__mmask32)__builtin_ia32_vpshufbitqmb256_mask(
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(__v32qi)__A, (__v32qi)__B, (__mmask32)__M);
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}
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#ifdef __DISABLE_AVX512BITALGVLBW__
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#undef __DISABLE_AVX512BITALGVLBW__
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#pragma GCC pop_options
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#endif /* __DISABLE_AVX512BITALGVLBW__ */
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#if !defined(__AVX512BITALG__) || !defined(__AVX512VL__)
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#pragma GCC push_options
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#pragma GCC target("avx512bitalg,avx512vl")
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#define __DISABLE_AVX512BITALGVL__
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#endif /* __AVX512VLBW__ */
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extern __inline __mmask16
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_bitshuffle_epi64_mask(__m128i __A, __m128i __B) {
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return (__mmask16)__builtin_ia32_vpshufbitqmb128_mask(
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(__v16qi)__A, (__v16qi)__B, (__mmask16)-1);
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}
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extern __inline __mmask16
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_mask_bitshuffle_epi64_mask(__mmask16 __M, __m128i __A, __m128i __B) {
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return (__mmask16)__builtin_ia32_vpshufbitqmb128_mask(
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(__v16qi)__A, (__v16qi)__B, (__mmask16)__M);
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}
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extern __inline __m256i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_popcnt_epi8(__m256i __A) {
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return (__m256i)__builtin_ia32_vpopcountb_v32qi((__v32qi)__A);
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}
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extern __inline __m256i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_popcnt_epi16(__m256i __A) {
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return (__m256i)__builtin_ia32_vpopcountw_v16hi((__v16hi)__A);
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}
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extern __inline __m128i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_popcnt_epi8(__m128i __A) {
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return (__m128i)__builtin_ia32_vpopcountb_v16qi((__v16qi)__A);
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}
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extern __inline __m128i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_popcnt_epi16(__m128i __A) {
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return (__m128i)__builtin_ia32_vpopcountw_v8hi((__v8hi)__A);
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}
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extern __inline __m256i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_mask_popcnt_epi16(__m256i __A, __mmask16 __U, __m256i __B) {
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return (__m256i)__builtin_ia32_vpopcountw_v16hi_mask(
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(__v16hi)__A, (__v16hi)__B, (__mmask16)__U);
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}
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extern __inline __m256i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_maskz_popcnt_epi16(__mmask16 __U, __m256i __A) {
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return (__m256i)__builtin_ia32_vpopcountw_v16hi_mask(
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(__v16hi)__A, (__v16hi)_mm256_setzero_si256(), (__mmask16)__U);
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}
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extern __inline __m128i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_mask_popcnt_epi8(__m128i __A, __mmask16 __U, __m128i __B) {
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return (__m128i)__builtin_ia32_vpopcountb_v16qi_mask(
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(__v16qi)__A, (__v16qi)__B, (__mmask16)__U);
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}
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extern __inline __m128i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_maskz_popcnt_epi8(__mmask16 __U, __m128i __A) {
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return (__m128i)__builtin_ia32_vpopcountb_v16qi_mask(
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(__v16qi)__A, (__v16qi)_mm_setzero_si128(), (__mmask16)__U);
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}
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extern __inline __m128i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_mask_popcnt_epi16(__m128i __A, __mmask8 __U, __m128i __B) {
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return (__m128i)__builtin_ia32_vpopcountw_v8hi_mask((__v8hi)__A, (__v8hi)__B,
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(__mmask8)__U);
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}
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extern __inline __m128i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_maskz_popcnt_epi16(__mmask8 __U, __m128i __A) {
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return (__m128i)__builtin_ia32_vpopcountw_v8hi_mask(
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(__v8hi)__A, (__v8hi)_mm_setzero_si128(), (__mmask8)__U);
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}
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#ifdef __DISABLE_AVX512BITALGVL__
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#undef __DISABLE_AVX512BITALGVL__
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#pragma GCC pop_options
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#endif /* __DISABLE_AVX512BITALGBW__ */
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#endif /* _AVX512BITALGINTRIN_H_INCLUDED */
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