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Add Intel intrinsics headers
This commit is contained in:
Justine Tunney
parent
369f9740de
commit
b7bf052a4b
121 changed files with 47114 additions and 849 deletions
344
third_party/intel/gfniintrin.internal.h
vendored
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344
third_party/intel/gfniintrin.internal.h
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#ifndef _IMMINTRIN_H_INCLUDED
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#error "Never use <gfniintrin.h> directly; include <immintrin.h> instead."
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#endif
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#ifndef _GFNIINTRIN_H_INCLUDED
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#define _GFNIINTRIN_H_INCLUDED
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#if !defined(__GFNI__) || !defined(__SSE2__)
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#pragma GCC push_options
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#pragma GCC target("gfni,sse2")
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#define __DISABLE_GFNI__
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#endif /* __GFNI__ */
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extern __inline __m128i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_gf2p8mul_epi8(__m128i __A, __m128i __B) {
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return (__m128i)__builtin_ia32_vgf2p8mulb_v16qi((__v16qi)__A, (__v16qi)__B);
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}
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#ifdef __OPTIMIZE__
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extern __inline __m128i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_gf2p8affineinv_epi64_epi8(__m128i __A, __m128i __B, const int __C) {
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return (__m128i)__builtin_ia32_vgf2p8affineinvqb_v16qi((__v16qi)__A,
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(__v16qi)__B, __C);
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}
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extern __inline __m128i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_gf2p8affine_epi64_epi8(__m128i __A, __m128i __B, const int __C) {
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return (__m128i)__builtin_ia32_vgf2p8affineqb_v16qi((__v16qi)__A,
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(__v16qi)__B, __C);
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}
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#else
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#define _mm_gf2p8affineinv_epi64_epi8(A, B, C) \
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((__m128i)__builtin_ia32_vgf2p8affineinvqb_v16qi( \
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(__v16qi)(__m128i)(A), (__v16qi)(__m128i)(B), (int)(C)))
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#define _mm_gf2p8affine_epi64_epi8(A, B, C) \
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((__m128i)__builtin_ia32_vgf2p8affineqb_v16qi( \
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(__v16qi)(__m128i)(A), (__v16qi)(__m128i)(B), (int)(C)))
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#endif
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#ifdef __DISABLE_GFNI__
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#undef __DISABLE_GFNI__
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#pragma GCC pop_options
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#endif /* __DISABLE_GFNI__ */
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#if !defined(__GFNI__) || !defined(__AVX__)
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#pragma GCC push_options
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#pragma GCC target("gfni,avx")
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#define __DISABLE_GFNIAVX__
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#endif /* __GFNIAVX__ */
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extern __inline __m256i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_gf2p8mul_epi8(__m256i __A, __m256i __B) {
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return (__m256i)__builtin_ia32_vgf2p8mulb_v32qi((__v32qi)__A, (__v32qi)__B);
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}
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#ifdef __OPTIMIZE__
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extern __inline __m256i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_gf2p8affineinv_epi64_epi8(__m256i __A, __m256i __B, const int __C) {
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return (__m256i)__builtin_ia32_vgf2p8affineinvqb_v32qi((__v32qi)__A,
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(__v32qi)__B, __C);
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}
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extern __inline __m256i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_gf2p8affine_epi64_epi8(__m256i __A, __m256i __B, const int __C) {
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return (__m256i)__builtin_ia32_vgf2p8affineqb_v32qi((__v32qi)__A,
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(__v32qi)__B, __C);
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}
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#else
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#define _mm256_gf2p8affineinv_epi64_epi8(A, B, C) \
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((__m256i)__builtin_ia32_vgf2p8affineinvqb_v32qi( \
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(__v32qi)(__m256i)(A), (__v32qi)(__m256i)(B), (int)(C)))
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#define _mm256_gf2p8affine_epi64_epi8(A, B, C) \
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((__m256i)__builtin_ia32_vgf2p8affineqb_v32qi( \
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(__v32qi)(__m256i)(A), (__v32qi)(__m256i)(B), (int)(C)))
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#endif
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#ifdef __DISABLE_GFNIAVX__
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#undef __DISABLE_GFNIAVX__
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#pragma GCC pop_options
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#endif /* __GFNIAVX__ */
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#if !defined(__GFNI__) || !defined(__AVX512VL__)
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#pragma GCC push_options
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#pragma GCC target("gfni,avx512vl")
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#define __DISABLE_GFNIAVX512VL__
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#endif /* __GFNIAVX512VL__ */
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extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__,
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__artificial__))
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_mm_mask_gf2p8mul_epi8(__m128i __A, __mmask16 __B, __m128i __C, __m128i __D) {
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return (__m128i)__builtin_ia32_vgf2p8mulb_v16qi_mask(
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(__v16qi)__C, (__v16qi)__D, (__v16qi)__A, __B);
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}
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extern __inline __m128i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_maskz_gf2p8mul_epi8(__mmask16 __A, __m128i __B, __m128i __C) {
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return (__m128i)__builtin_ia32_vgf2p8mulb_v16qi_mask(
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(__v16qi)__B, (__v16qi)__C, (__v16qi)_mm_setzero_si128(), __A);
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}
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#ifdef __OPTIMIZE__
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extern __inline __m128i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_mask_gf2p8affineinv_epi64_epi8(__m128i __A, __mmask16 __B, __m128i __C,
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__m128i __D, const int __E) {
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return (__m128i)__builtin_ia32_vgf2p8affineinvqb_v16qi_mask(
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(__v16qi)__C, (__v16qi)__D, __E, (__v16qi)__A, __B);
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}
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extern __inline __m128i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_maskz_gf2p8affineinv_epi64_epi8(__mmask16 __A, __m128i __B, __m128i __C,
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const int __D) {
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return (__m128i)__builtin_ia32_vgf2p8affineinvqb_v16qi_mask(
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(__v16qi)__B, (__v16qi)__C, __D, (__v16qi)_mm_setzero_si128(), __A);
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}
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extern __inline __m128i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_mask_gf2p8affine_epi64_epi8(__m128i __A, __mmask16 __B, __m128i __C,
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__m128i __D, const int __E) {
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return (__m128i)__builtin_ia32_vgf2p8affineqb_v16qi_mask(
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(__v16qi)__C, (__v16qi)__D, __E, (__v16qi)__A, __B);
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}
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extern __inline __m128i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_maskz_gf2p8affine_epi64_epi8(__mmask16 __A, __m128i __B, __m128i __C,
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const int __D) {
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return (__m128i)__builtin_ia32_vgf2p8affineqb_v16qi_mask(
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(__v16qi)__B, (__v16qi)__C, __D, (__v16qi)_mm_setzero_si128(), __A);
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}
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#else
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#define _mm_mask_gf2p8affineinv_epi64_epi8(A, B, C, D, E) \
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((__m128i)__builtin_ia32_vgf2p8affineinvqb_v16qi_mask( \
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(__v16qi)(__m128i)(C), (__v16qi)(__m128i)(D), (int)(E), \
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(__v16qi)(__m128i)(A), (__mmask16)(B)))
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#define _mm_maskz_gf2p8affineinv_epi64_epi8(A, B, C, D) \
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((__m128i)__builtin_ia32_vgf2p8affineinvqb_v16qi_mask( \
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(__v16qi)(__m128i)(B), (__v16qi)(__m128i)(C), (int)(D), \
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(__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)(A)))
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#define _mm_mask_gf2p8affine_epi64_epi8(A, B, C, D, E) \
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((__m128i)__builtin_ia32_vgf2p8affineqb_v16qi_mask( \
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(__v16qi)(__m128i)(C), (__v16qi)(__m128i)(D), (int)(E), \
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(__v16qi)(__m128i)(A), (__mmask16)(B)))
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#define _mm_maskz_gf2p8affine_epi64_epi8(A, B, C, D) \
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((__m128i)__builtin_ia32_vgf2p8affineqb_v16qi_mask( \
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(__v16qi)(__m128i)(B), (__v16qi)(__m128i)(C), (int)(D), \
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(__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)(A)))
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#endif
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#ifdef __DISABLE_GFNIAVX512VL__
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#undef __DISABLE_GFNIAVX512VL__
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#pragma GCC pop_options
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#endif /* __GFNIAVX512VL__ */
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#if !defined(__GFNI__) || !defined(__AVX512VL__) || !defined(__AVX512BW__)
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#pragma GCC push_options
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#pragma GCC target("gfni,avx512vl,avx512bw")
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#define __DISABLE_GFNIAVX512VLBW__
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#endif /* __GFNIAVX512VLBW__ */
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extern __inline __m256i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_mask_gf2p8mul_epi8(__m256i __A, __mmask32 __B, __m256i __C,
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__m256i __D) {
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return (__m256i)__builtin_ia32_vgf2p8mulb_v32qi_mask(
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(__v32qi)__C, (__v32qi)__D, (__v32qi)__A, __B);
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}
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extern __inline __m256i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_maskz_gf2p8mul_epi8(__mmask32 __A, __m256i __B, __m256i __C) {
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return (__m256i)__builtin_ia32_vgf2p8mulb_v32qi_mask(
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(__v32qi)__B, (__v32qi)__C, (__v32qi)_mm256_setzero_si256(), __A);
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}
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#ifdef __OPTIMIZE__
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extern __inline __m256i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_mask_gf2p8affineinv_epi64_epi8(__m256i __A, __mmask32 __B,
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__m256i __C, __m256i __D,
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const int __E) {
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return (__m256i)__builtin_ia32_vgf2p8affineinvqb_v32qi_mask(
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(__v32qi)__C, (__v32qi)__D, __E, (__v32qi)__A, __B);
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}
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extern __inline __m256i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_maskz_gf2p8affineinv_epi64_epi8(__mmask32 __A, __m256i __B,
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__m256i __C, const int __D) {
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return (__m256i)__builtin_ia32_vgf2p8affineinvqb_v32qi_mask(
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(__v32qi)__B, (__v32qi)__C, __D, (__v32qi)_mm256_setzero_si256(), __A);
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}
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extern __inline __m256i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_mask_gf2p8affine_epi64_epi8(__m256i __A, __mmask32 __B, __m256i __C,
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__m256i __D, const int __E) {
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return (__m256i)__builtin_ia32_vgf2p8affineqb_v32qi_mask(
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(__v32qi)__C, (__v32qi)__D, __E, (__v32qi)__A, __B);
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}
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extern __inline __m256i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_maskz_gf2p8affine_epi64_epi8(__mmask32 __A, __m256i __B, __m256i __C,
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const int __D) {
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return (__m256i)__builtin_ia32_vgf2p8affineqb_v32qi_mask(
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(__v32qi)__B, (__v32qi)__C, __D, (__v32qi)_mm256_setzero_si256(), __A);
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}
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#else
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#define _mm256_mask_gf2p8affineinv_epi64_epi8(A, B, C, D, E) \
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((__m256i)__builtin_ia32_vgf2p8affineinvqb_v32qi_mask( \
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(__v32qi)(__m256i)(C), (__v32qi)(__m256i)(D), (int)(E), \
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(__v32qi)(__m256i)(A), (__mmask32)(B)))
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#define _mm256_maskz_gf2p8affineinv_epi64_epi8(A, B, C, D) \
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((__m256i)__builtin_ia32_vgf2p8affineinvqb_v32qi_mask( \
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(__v32qi)(__m256i)(B), (__v32qi)(__m256i)(C), (int)(D), \
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(__v32qi)(__m256i)_mm256_setzero_si256(), (__mmask32)(A)))
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#define _mm256_mask_gf2p8affine_epi64_epi8(A, B, C, D, E) \
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((__m256i)__builtin_ia32_vgf2p8affineqb_v32qi_mask( \
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(__v32qi)(__m256i)(C), (__v32qi)(__m256i)(D), (int)(E), \
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(__v32qi)(__m256i)(A), (__mmask32)(B)))
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#define _mm256_maskz_gf2p8affine_epi64_epi8(A, B, C, D) \
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((__m256i)__builtin_ia32_vgf2p8affineqb_v32qi_mask( \
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(__v32qi)(__m256i)(B), (__v32qi)(__m256i)(C), (int)(D), \
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(__v32qi)(__m256i)_mm256_setzero_si256(), (__mmask32)(A)))
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#endif
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#ifdef __DISABLE_GFNIAVX512VLBW__
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#undef __DISABLE_GFNIAVX512VLBW__
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#pragma GCC pop_options
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#endif /* __GFNIAVX512VLBW__ */
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#if !defined(__GFNI__) || !defined(__AVX512F__) || !defined(__AVX512BW__)
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#pragma GCC push_options
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#pragma GCC target("gfni,avx512f,avx512bw")
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#define __DISABLE_GFNIAVX512FBW__
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#endif /* __GFNIAVX512FBW__ */
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extern __inline __m512i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_mask_gf2p8mul_epi8(__m512i __A, __mmask64 __B, __m512i __C,
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__m512i __D) {
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return (__m512i)__builtin_ia32_vgf2p8mulb_v64qi_mask(
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(__v64qi)__C, (__v64qi)__D, (__v64qi)__A, __B);
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}
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extern __inline __m512i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_maskz_gf2p8mul_epi8(__mmask64 __A, __m512i __B, __m512i __C) {
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return (__m512i)__builtin_ia32_vgf2p8mulb_v64qi_mask(
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(__v64qi)__B, (__v64qi)__C, (__v64qi)_mm512_setzero_si512(), __A);
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}
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extern __inline __m512i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_gf2p8mul_epi8(__m512i __A, __m512i __B) {
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return (__m512i)__builtin_ia32_vgf2p8mulb_v64qi((__v64qi)__A, (__v64qi)__B);
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}
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#ifdef __OPTIMIZE__
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extern __inline __m512i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_mask_gf2p8affineinv_epi64_epi8(__m512i __A, __mmask64 __B,
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__m512i __C, __m512i __D,
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const int __E) {
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return (__m512i)__builtin_ia32_vgf2p8affineinvqb_v64qi_mask(
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(__v64qi)__C, (__v64qi)__D, __E, (__v64qi)__A, __B);
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}
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extern __inline __m512i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_maskz_gf2p8affineinv_epi64_epi8(__mmask64 __A, __m512i __B,
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__m512i __C, const int __D) {
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return (__m512i)__builtin_ia32_vgf2p8affineinvqb_v64qi_mask(
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(__v64qi)__B, (__v64qi)__C, __D, (__v64qi)_mm512_setzero_si512(), __A);
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}
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extern __inline __m512i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_gf2p8affineinv_epi64_epi8(__m512i __A, __m512i __B, const int __C) {
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return (__m512i)__builtin_ia32_vgf2p8affineinvqb_v64qi((__v64qi)__A,
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(__v64qi)__B, __C);
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}
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extern __inline __m512i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_mask_gf2p8affine_epi64_epi8(__m512i __A, __mmask64 __B, __m512i __C,
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__m512i __D, const int __E) {
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return (__m512i)__builtin_ia32_vgf2p8affineqb_v64qi_mask(
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(__v64qi)__C, (__v64qi)__D, __E, (__v64qi)__A, __B);
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}
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extern __inline __m512i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_maskz_gf2p8affine_epi64_epi8(__mmask64 __A, __m512i __B, __m512i __C,
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const int __D) {
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return (__m512i)__builtin_ia32_vgf2p8affineqb_v64qi_mask(
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(__v64qi)__B, (__v64qi)__C, __D, (__v64qi)_mm512_setzero_si512(), __A);
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}
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extern __inline __m512i
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__attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm512_gf2p8affine_epi64_epi8(__m512i __A, __m512i __B, const int __C) {
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return (__m512i)__builtin_ia32_vgf2p8affineqb_v64qi((__v64qi)__A,
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(__v64qi)__B, __C);
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}
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#else
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#define _mm512_mask_gf2p8affineinv_epi64_epi8(A, B, C, D, E) \
|
||||
((__m512i)__builtin_ia32_vgf2p8affineinvqb_v64qi_mask( \
|
||||
(__v64qi)(__m512i)(C), (__v64qi)(__m512i)(D), (int)(E), \
|
||||
(__v64qi)(__m512i)(A), (__mmask64)(B)))
|
||||
#define _mm512_maskz_gf2p8affineinv_epi64_epi8(A, B, C, D) \
|
||||
((__m512i)__builtin_ia32_vgf2p8affineinvqb_v64qi_mask( \
|
||||
(__v64qi)(__m512i)(B), (__v64qi)(__m512i)(C), (int)(D), \
|
||||
(__v64qi)(__m512i)_mm512_setzero_si512(), (__mmask64)(A)))
|
||||
#define _mm512_gf2p8affineinv_epi64_epi8(A, B, C) \
|
||||
((__m512i)__builtin_ia32_vgf2p8affineinvqb_v64qi( \
|
||||
(__v64qi)(__m512i)(A), (__v64qi)(__m512i)(B), (int)(C)))
|
||||
#define _mm512_mask_gf2p8affine_epi64_epi8(A, B, C, D, E) \
|
||||
((__m512i)__builtin_ia32_vgf2p8affineqb_v64qi_mask( \
|
||||
(__v64qi)(__m512i)(C), (__v64qi)(__m512i)(D), (int)(E), \
|
||||
(__v64qi)(__m512i)(A), (__mmask64)(B)))
|
||||
#define _mm512_maskz_gf2p8affine_epi64_epi8(A, B, C, D) \
|
||||
((__m512i)__builtin_ia32_vgf2p8affineqb_v64qi_mask( \
|
||||
(__v64qi)(__m512i)(B), (__v64qi)(__m512i)(C), (int)(D), \
|
||||
(__v64qi)(__m512i)_mm512_setzero_si512(), (__mmask64)(A)))
|
||||
#define _mm512_gf2p8affine_epi64_epi8(A, B, C) \
|
||||
((__m512i)__builtin_ia32_vgf2p8affineqb_v64qi( \
|
||||
(__v64qi)(__m512i)(A), (__v64qi)(__m512i)(B), (int)(C)))
|
||||
#endif
|
||||
|
||||
#ifdef __DISABLE_GFNIAVX512FBW__
|
||||
#undef __DISABLE_GFNIAVX512FBW__
|
||||
#pragma GCC pop_options
|
||||
#endif /* __GFNIAVX512FBW__ */
|
||||
|
||||
#endif /* _GFNIINTRIN_H_INCLUDED */
|
||||
Loading…
Add table
Add a link
Reference in a new issue