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Enable CPU exception handling w/ IDT & TSS (#640)
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09811e739f
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7 changed files with 231 additions and 7 deletions
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@ -180,6 +180,12 @@
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.stub \name\()_bcs\n,long
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.endm
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// Task State Segment Descriptor Entries.
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.macro .tssdescstub name:req
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.stub \name\()_desc_ent0,quad
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.stub \name\()_desc_ent1,quad
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.endm
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/* clang-format on */
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#elif defined(__LINKER__)
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@ -257,5 +263,22 @@
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(X) % 10 * 0x1000000 \
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: 0xffffffffffffffff)
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/**
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* Laying out the GDT entries for a TSS for bare metal operation.
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*/
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#define TSSDESCSTUB2(SYM, BASE, LIM) \
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HIDDEN(SYM##_desc_ent0 = TSSDESC_ENT0(BASE, LIM)); \
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HIDDEN(SYM##_desc_ent1 = TSSDESC_ENT1(BASE)); \
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ASSERT((LIM) >= 0 && (LIM) <= 0xffff, "bare metal TSS is suspiciously fat")
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#define TSSDESC_ENT0(BASE, LIM) \
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(((LIM) << 0 & 0x000000000000ffff) | \
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((BASE) << 16 & 0x000000ffffff0000) | \
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0x89 << 40 | \
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((LIM) >> 16 << 48 & 0x000f000000000000) | \
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0x2 << 52 | \
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((BASE) >> 24 << 56 & 0xff00000000000000))
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#define TSSDESC_ENT1(BASE) \
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((BASE) >> 32 << 0 & 0x00000000ffffffff)
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#endif /* __ASSEMBLER__ */
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#endif /* APE_MACROS_H_ */
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