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Make AARCH64 harder, better, faster, stronger
- Perform some housekeeping on scalar math function code - Import ARM's Optimized Routines for SIMD string processing - Upgrade to latest Chromium zlib and enable more SIMD optimizations
This commit is contained in:
Justine Tunney
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550b52abf6
commit
cc1732bc42
143 changed files with 15661 additions and 1329 deletions
233
libc/intrin/aarch64/memcpy.S
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233
libc/intrin/aarch64/memcpy.S
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/*-*- mode:unix-assembly; indent-tabs-mode:t; tab-width:8; coding:utf-8 -*-│
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│vi: set et ft=asm ts=8 tw=8 fenc=utf-8 :vi│
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╚──────────────────────────────────────────────────────────────────────────────╝
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│ │
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│ Optimized Routines │
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│ Copyright (c) 1999-2022, Arm Limited. │
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│ │
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│ Permission is hereby granted, free of charge, to any person obtaining │
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│ a copy of this software and associated documentation files (the │
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│ "Software"), to deal in the Software without restriction, including │
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│ without limitation the rights to use, copy, modify, merge, publish, │
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│ distribute, sublicense, and/or sell copies of the Software, and to │
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│ permit persons to whom the Software is furnished to do so, subject to │
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│ the following conditions: │
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│ │
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│ The above copyright notice and this permission notice shall be │
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│ included in all copies or substantial portions of the Software. │
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│ │
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│ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, │
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│ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF │
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│ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. │
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│ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY │
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│ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, │
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│ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE │
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│ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. │
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│ │
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╚─────────────────────────────────────────────────────────────────────────────*/
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#include "libc/intrin/aarch64/asmdefs.h"
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#define __memcpy_aarch64_simd memcpy
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#define __memmove_aarch64_simd memmove
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.ident "\n\
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Optimized Routines (MIT License)\n\
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Copyright 2022 ARM Limited\n"
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.include "libc/disclaimer.inc"
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/* Assumptions:
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*
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* ARMv8-a, AArch64, Advanced SIMD, unaligned accesses.
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*
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*/
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#define dstin x0
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#define src x1
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#define count x2
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#define dst x3
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#define srcend x4
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#define dstend x5
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#define A_l x6
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#define A_lw w6
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#define A_h x7
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#define B_l x8
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#define B_lw w8
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#define B_h x9
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#define C_lw w10
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#define tmp1 x14
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#define A_q q0
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#define B_q q1
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#define C_q q2
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#define D_q q3
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#define E_q q4
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#define F_q q5
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#define G_q q6
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#define H_q q7
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/* This implementation handles overlaps and supports both memcpy and memmove
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from a single entry point. It uses unaligned accesses and branchless
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sequences to keep the code small, simple and improve performance.
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Copies are split into 3 main cases: small copies of up to 32 bytes, medium
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copies of up to 128 bytes, and large copies. The overhead of the overlap
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check is negligible since it is only required for large copies.
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Large copies use a software pipelined loop processing 64 bytes per iteration.
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The source pointer is 16-byte aligned to minimize unaligned accesses.
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The loop tail is handled by always copying 64 bytes from the end.
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*/
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ENTRY_ALIAS (__memmove_aarch64_simd)
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ENTRY (__memcpy_aarch64_simd)
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PTR_ARG (0)
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PTR_ARG (1)
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SIZE_ARG (2)
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add srcend, src, count
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add dstend, dstin, count
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cmp count, 128
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b.hi L(copy_long)
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cmp count, 32
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b.hi L(copy32_128)
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/* Small copies: 0..32 bytes. */
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cmp count, 16
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b.lo L(copy16)
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ldr A_q, [src]
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ldr B_q, [srcend, -16]
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str A_q, [dstin]
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str B_q, [dstend, -16]
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ret
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/* Copy 8-15 bytes. */
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L(copy16):
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tbz count, 3, L(copy8)
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ldr A_l, [src]
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ldr A_h, [srcend, -8]
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str A_l, [dstin]
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str A_h, [dstend, -8]
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ret
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.p2align 3
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/* Copy 4-7 bytes. */
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L(copy8):
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tbz count, 2, L(copy4)
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ldr A_lw, [src]
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ldr B_lw, [srcend, -4]
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str A_lw, [dstin]
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str B_lw, [dstend, -4]
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ret
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/* Copy 0..3 bytes using a branchless sequence. */
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L(copy4):
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cbz count, L(copy0)
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lsr tmp1, count, 1
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ldrb A_lw, [src]
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ldrb C_lw, [srcend, -1]
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ldrb B_lw, [src, tmp1]
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strb A_lw, [dstin]
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strb B_lw, [dstin, tmp1]
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strb C_lw, [dstend, -1]
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L(copy0):
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ret
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.p2align 4
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/* Medium copies: 33..128 bytes. */
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L(copy32_128):
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ldp A_q, B_q, [src]
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ldp C_q, D_q, [srcend, -32]
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cmp count, 64
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b.hi L(copy128)
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stp A_q, B_q, [dstin]
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stp C_q, D_q, [dstend, -32]
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ret
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.p2align 4
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/* Copy 65..128 bytes. */
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L(copy128):
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ldp E_q, F_q, [src, 32]
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cmp count, 96
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b.ls L(copy96)
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ldp G_q, H_q, [srcend, -64]
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stp G_q, H_q, [dstend, -64]
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L(copy96):
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stp A_q, B_q, [dstin]
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stp E_q, F_q, [dstin, 32]
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stp C_q, D_q, [dstend, -32]
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ret
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/* Copy more than 128 bytes. */
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L(copy_long):
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/* Use backwards copy if there is an overlap. */
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sub tmp1, dstin, src
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cmp tmp1, count
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b.lo L(copy_long_backwards)
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/* Copy 16 bytes and then align src to 16-byte alignment. */
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ldr D_q, [src]
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and tmp1, src, 15
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bic src, src, 15
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sub dst, dstin, tmp1
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add count, count, tmp1 /* Count is now 16 too large. */
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ldp A_q, B_q, [src, 16]
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str D_q, [dstin]
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ldp C_q, D_q, [src, 48]
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subs count, count, 128 + 16 /* Test and readjust count. */
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b.ls L(copy64_from_end)
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L(loop64):
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stp A_q, B_q, [dst, 16]
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ldp A_q, B_q, [src, 80]
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stp C_q, D_q, [dst, 48]
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ldp C_q, D_q, [src, 112]
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add src, src, 64
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add dst, dst, 64
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subs count, count, 64
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b.hi L(loop64)
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/* Write the last iteration and copy 64 bytes from the end. */
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L(copy64_from_end):
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ldp E_q, F_q, [srcend, -64]
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stp A_q, B_q, [dst, 16]
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ldp A_q, B_q, [srcend, -32]
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stp C_q, D_q, [dst, 48]
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stp E_q, F_q, [dstend, -64]
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stp A_q, B_q, [dstend, -32]
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ret
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/* Large backwards copy for overlapping copies.
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Copy 16 bytes and then align srcend to 16-byte alignment. */
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L(copy_long_backwards):
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cbz tmp1, L(copy0)
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ldr D_q, [srcend, -16]
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and tmp1, srcend, 15
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bic srcend, srcend, 15
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sub count, count, tmp1
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ldp A_q, B_q, [srcend, -32]
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str D_q, [dstend, -16]
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ldp C_q, D_q, [srcend, -64]
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sub dstend, dstend, tmp1
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subs count, count, 128
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b.ls L(copy64_from_start)
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L(loop64_backwards):
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str B_q, [dstend, -16]
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str A_q, [dstend, -32]
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ldp A_q, B_q, [srcend, -96]
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str D_q, [dstend, -48]
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str C_q, [dstend, -64]!
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ldp C_q, D_q, [srcend, -128]
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sub srcend, srcend, 64
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subs count, count, 64
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b.hi L(loop64_backwards)
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/* Write the last iteration and copy 64 bytes from the start. */
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L(copy64_from_start):
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ldp E_q, F_q, [src, 32]
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stp A_q, B_q, [dstend, -32]
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ldp A_q, B_q, [src]
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stp C_q, D_q, [dstend, -64]
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stp E_q, F_q, [dstin, 32]
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stp A_q, B_q, [dstin]
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ret
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END (__memcpy_aarch64_simd)
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