mirror of
https://github.com/jart/cosmopolitan.git
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c9152b6f14
This change switches c++ exception handling from sjlj to standard dwarf. It's needed because clang for aarch64 doesn't support sjlj. It turns out that libunwind had a bare-metal configuration that made this easy to do. This change gets the new experimental cosmocc -mclang flag in a state of working so well that it can now be used to build all of llamafile and it goes 3x faster in terms of build latency, without trading away any perf. The int_fast16_t and int_fast32_t types are now always defined as 32-bit in the interest of having more abi consistency between cosmocc -mgcc and -mclang mode.
203 lines
6.6 KiB
C
203 lines
6.6 KiB
C
/*===----------------------- raointintrin.h - RAOINT ------------------------===
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*
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* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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* See https://llvm.org/LICENSE.txt for license information.
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* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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*
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*===-----------------------------------------------------------------------===
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*/
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#ifndef __X86GPRINTRIN_H
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#error "Never use <raointintrin.h> directly; include <x86gprintrin.h> instead."
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#endif // __X86GPRINTRIN_H
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#ifndef __RAOINTINTRIN_H
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#define __RAOINTINTRIN_H
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#define __DEFAULT_FN_ATTRS \
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__attribute__((__always_inline__, __nodebug__, __target__("raoint")))
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/// Atomically add a 32-bit value at memory operand \a __A and a 32-bit \a __B,
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/// and store the result to the same memory location.
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///
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/// This intrinsic should be used for contention or weak ordering. It may
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/// result in bad performance for hot data used by single thread only.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the \c AADD instruction.
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///
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/// \param __A
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/// A pointer to a 32-bit memory location.
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/// \param __B
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/// A 32-bit integer value.
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///
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/// \code{.operation}
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/// MEM[__A+31:__A] := MEM[__A+31:__A] + __B[31:0]
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/// \endcode
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static __inline__ void __DEFAULT_FN_ATTRS _aadd_i32(int *__A, int __B) {
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__builtin_ia32_aadd32((int *)__A, __B);
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}
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/// Atomically and a 32-bit value at memory operand \a __A and a 32-bit \a __B,
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/// and store the result to the same memory location.
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///
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/// This intrinsic should be used for contention or weak ordering. It may
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/// result in bad performance for hot data used by single thread only.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the \c AAND instruction.
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///
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/// \param __A
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/// A pointer to a 32-bit memory location.
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/// \param __B
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/// A 32-bit integer value.
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///
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/// \code{.operation}
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/// MEM[__A+31:__A] := MEM[__A+31:__A] AND __B[31:0]
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/// \endcode
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static __inline__ void __DEFAULT_FN_ATTRS _aand_i32(int *__A, int __B) {
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__builtin_ia32_aand32((int *)__A, __B);
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}
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/// Atomically or a 32-bit value at memory operand \a __A and a 32-bit \a __B,
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/// and store the result to the same memory location.
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///
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/// This intrinsic should be used for contention or weak ordering. It may
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/// result in bad performance for hot data used by single thread only.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the \c AOR instruction.
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///
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/// \param __A
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/// A pointer to a 32-bit memory location.
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/// \param __B
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/// A 32-bit integer value.
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///
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/// \code{.operation}
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/// MEM[__A+31:__A] := MEM[__A+31:__A] OR __B[31:0]
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/// \endcode
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static __inline__ void __DEFAULT_FN_ATTRS _aor_i32(int *__A, int __B) {
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__builtin_ia32_aor32((int *)__A, __B);
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}
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/// Atomically xor a 32-bit value at memory operand \a __A and a 32-bit \a __B,
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/// and store the result to the same memory location.
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///
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/// This intrinsic should be used for contention or weak ordering. It may
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/// result in bad performance for hot data used by single thread only.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the \c AXOR instruction.
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///
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/// \param __A
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/// A pointer to a 32-bit memory location.
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/// \param __B
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/// A 32-bit integer value.
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///
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/// \code{.operation}
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/// MEM[__A+31:__A] := MEM[__A+31:__A] XOR __B[31:0]
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/// \endcode
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static __inline__ void __DEFAULT_FN_ATTRS _axor_i32(int *__A, int __B) {
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__builtin_ia32_axor32((int *)__A, __B);
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}
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#ifdef __x86_64__
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/// Atomically add a 64-bit value at memory operand \a __A and a 64-bit \a __B,
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/// and store the result to the same memory location.
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///
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/// This intrinsic should be used for contention or weak ordering. It may
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/// result in bad performance for hot data used by single thread only.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the \c AADD instruction.
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///
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/// \param __A
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/// A pointer to a 64-bit memory location.
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/// \param __B
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/// A 64-bit integer value.
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///
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/// \code{.operation}
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/// MEM[__A+63:__A] := MEM[__A+63:__A] + __B[63:0]
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/// \endcode
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static __inline__ void __DEFAULT_FN_ATTRS _aadd_i64(long long *__A,
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long long __B) {
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__builtin_ia32_aadd64((long long *)__A, __B);
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}
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/// Atomically and a 64-bit value at memory operand \a __A and a 64-bit \a __B,
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/// and store the result to the same memory location.
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///
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/// This intrinsic should be used for contention or weak ordering. It may
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/// result in bad performance for hot data used by single thread only.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the \c AAND instruction.
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///
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/// \param __A
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/// A pointer to a 64-bit memory location.
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/// \param __B
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/// A 64-bit integer value.
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///
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/// \code{.operation}
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/// MEM[__A+63:__A] := MEM[__A+63:__A] AND __B[63:0]
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/// \endcode
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static __inline__ void __DEFAULT_FN_ATTRS _aand_i64(long long *__A,
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long long __B) {
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__builtin_ia32_aand64((long long *)__A, __B);
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}
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/// Atomically or a 64-bit value at memory operand \a __A and a 64-bit \a __B,
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/// and store the result to the same memory location.
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///
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/// This intrinsic should be used for contention or weak ordering. It may
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/// result in bad performance for hot data used by single thread only.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the \c AOR instruction.
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///
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/// \param __A
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/// A pointer to a 64-bit memory location.
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/// \param __B
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/// A 64-bit integer value.
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///
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/// \code{.operation}
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/// MEM[__A+63:__A] := MEM[__A+63:__A] OR __B[63:0]
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/// \endcode
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static __inline__ void __DEFAULT_FN_ATTRS _aor_i64(long long *__A,
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long long __B) {
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__builtin_ia32_aor64((long long *)__A, __B);
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}
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/// Atomically xor a 64-bit value at memory operand \a __A and a 64-bit \a __B,
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/// and store the result to the same memory location.
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///
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/// This intrinsic should be used for contention or weak ordering. It may
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/// result in bad performance for hot data used by single thread only.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the \c AXOR instruction.
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///
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/// \param __A
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/// A pointer to a 64-bit memory location.
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/// \param __B
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/// A 64-bit integer value.
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///
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/// \code{.operation}
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/// MEM[__A+63:__A] := MEM[__A+63:__A] XOR __B[63:0]
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/// \endcode
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static __inline__ void __DEFAULT_FN_ATTRS _axor_i64(long long *__A,
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long long __B) {
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__builtin_ia32_axor64((long long *)__A, __B);
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}
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#endif // __x86_64__
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#undef __DEFAULT_FN_ATTRS
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#endif // __RAOINTINTRIN_H
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