mirror of
https://github.com/jart/cosmopolitan.git
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c9152b6f14
This change switches c++ exception handling from sjlj to standard dwarf. It's needed because clang for aarch64 doesn't support sjlj. It turns out that libunwind had a bare-metal configuration that made this easy to do. This change gets the new experimental cosmocc -mclang flag in a state of working so well that it can now be used to build all of llamafile and it goes 3x faster in terms of build latency, without trading away any perf. The int_fast16_t and int_fast32_t types are now always defined as 32-bit in the interest of having more abi consistency between cosmocc -mgcc and -mclang mode.
238 lines
7.3 KiB
C
238 lines
7.3 KiB
C
/*===-------------------- sm3intrin.h - SM3 intrinsics ---------------------===
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*
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* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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* See https://llvm.org/LICENSE.txt for license information.
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* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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*
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*===-----------------------------------------------------------------------===
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*/
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#ifndef __IMMINTRIN_H
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#error "Never use <sm3intrin.h> directly; include <immintrin.h> instead."
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#endif // __IMMINTRIN_H
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#ifndef __SM3INTRIN_H
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#define __SM3INTRIN_H
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#define __DEFAULT_FN_ATTRS128 \
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__attribute__((__always_inline__, __nodebug__, __target__("sm3"), \
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__min_vector_width__(128)))
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/// This intrinisc is one of the two SM3 message scheduling intrinsics. The
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/// intrinsic performs an initial calculation for the next four SM3 message
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/// words. The calculated results are stored in \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// __m128i _mm_sm3msg1_epi32(__m128i __A, __m128i __B, __m128i __C)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c VSM3MSG1 instruction.
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///
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/// \param __A
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/// A 128-bit vector of [4 x int].
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/// \param __B
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/// A 128-bit vector of [4 x int].
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/// \param __C
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/// A 128-bit vector of [4 x int].
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/// \returns
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/// A 128-bit vector of [4 x int].
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///
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/// \code{.operation}
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/// DEFINE ROL32(dword, n) {
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/// count := n % 32
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/// dest := (dword << count) | (dword >> (32 - count))
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/// RETURN dest
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/// }
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/// DEFINE P1(x) {
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/// RETURN x ^ ROL32(x, 15) ^ ROL32(x, 23)
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/// }
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/// W[0] := __C.dword[0]
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/// W[1] := __C.dword[1]
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/// W[2] := __C.dword[2]
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/// W[3] := __C.dword[3]
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/// W[7] := __A.dword[0]
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/// W[8] := __A.dword[1]
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/// W[9] := __A.dword[2]
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/// W[10] := __A.dword[3]
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/// W[13] := __B.dword[0]
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/// W[14] := __B.dword[1]
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/// W[15] := __B.dword[2]
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/// TMP0 := W[7] ^ W[0] ^ ROL32(W[13], 15)
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/// TMP1 := W[8] ^ W[1] ^ ROL32(W[14], 15)
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/// TMP2 := W[9] ^ W[2] ^ ROL32(W[15], 15)
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/// TMP3 := W[10] ^ W[3]
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/// dst.dword[0] := P1(TMP0)
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/// dst.dword[1] := P1(TMP1)
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/// dst.dword[2] := P1(TMP2)
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/// dst.dword[3] := P1(TMP3)
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/// dst[MAX:128] := 0
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/// \endcode
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static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_sm3msg1_epi32(__m128i __A,
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__m128i __B,
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__m128i __C) {
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return (__m128i)__builtin_ia32_vsm3msg1((__v4su)__A, (__v4su)__B,
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(__v4su)__C);
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}
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/// This intrinisc is one of the two SM3 message scheduling intrinsics. The
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/// intrinsic performs the final calculation for the next four SM3 message
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/// words. The calculated results are stored in \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// __m128i _mm_sm3msg2_epi32(__m128i __A, __m128i __B, __m128i __C)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c VSM3MSG2 instruction.
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///
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/// \param __A
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/// A 128-bit vector of [4 x int].
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/// \param __B
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/// A 128-bit vector of [4 x int].
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/// \param __C
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/// A 128-bit vector of [4 x int].
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/// \returns
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/// A 128-bit vector of [4 x int].
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///
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/// \code{.operation}
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/// DEFINE ROL32(dword, n) {
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/// count := n % 32
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/// dest := (dword << count) | (dword >> (32-count))
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/// RETURN dest
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/// }
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/// WTMP[0] := __A.dword[0]
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/// WTMP[1] := __A.dword[1]
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/// WTMP[2] := __A.dword[2]
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/// WTMP[3] := __A.dword[3]
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/// W[3] := __B.dword[0]
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/// W[4] := __B.dword[1]
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/// W[5] := __B.dword[2]
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/// W[6] := __B.dword[3]
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/// W[10] := __C.dword[0]
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/// W[11] := __C.dword[1]
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/// W[12] := __C.dword[2]
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/// W[13] := __C.dword[3]
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/// W[16] := ROL32(W[3], 7) ^ W[10] ^ WTMP[0]
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/// W[17] := ROL32(W[4], 7) ^ W[11] ^ WTMP[1]
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/// W[18] := ROL32(W[5], 7) ^ W[12] ^ WTMP[2]
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/// W[19] := ROL32(W[6], 7) ^ W[13] ^ WTMP[3]
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/// W[19] := W[19] ^ ROL32(W[16], 6) ^ ROL32(W[16], 15) ^ ROL32(W[16], 30)
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/// dst.dword[0] := W[16]
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/// dst.dword[1] := W[17]
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/// dst.dword[2] := W[18]
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/// dst.dword[3] := W[19]
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/// dst[MAX:128] := 0
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/// \endcode
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static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_sm3msg2_epi32(__m128i __A,
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__m128i __B,
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__m128i __C) {
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return (__m128i)__builtin_ia32_vsm3msg2((__v4su)__A, (__v4su)__B,
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(__v4su)__C);
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}
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/// This intrinsic performs two rounds of SM3 operation using initial SM3 state
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/// (C, D, G, H) from \a __A, an initial SM3 states (A, B, E, F)
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/// from \a __B and a pre-computed words from the \a __C. \a __A with
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/// initial SM3 state of (C, D, G, H) assumes input of non-rotated left
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/// variables from previous state. The updated SM3 state (A, B, E, F) is
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/// written to \a __A. The \a imm8 should contain the even round number
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/// for the first of the two rounds computed by this instruction. The
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/// computation masks the \a imm8 value by AND’ing it with 0x3E so that only
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/// even round numbers from 0 through 62 are used for this operation. The
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/// calculated results are stored in \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// __m128i _mm_sm3rnds2_epi32(__m128i __A, __m128i __B, __m128i __C, const int
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/// imm8) \endcode
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///
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/// This intrinsic corresponds to the \c VSM3RNDS2 instruction.
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///
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/// \param __A
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/// A 128-bit vector of [4 x int].
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/// \param __B
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/// A 128-bit vector of [4 x int].
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/// \param __C
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/// A 128-bit vector of [4 x int].
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/// \param imm8
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/// A 8-bit constant integer.
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/// \returns
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/// A 128-bit vector of [4 x int].
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///
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/// \code{.operation}
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/// DEFINE ROL32(dword, n) {
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/// count := n % 32
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/// dest := (dword << count) | (dword >> (32-count))
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/// RETURN dest
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/// }
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/// DEFINE P0(dword) {
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/// RETURN dword ^ ROL32(dword, 9) ^ ROL32(dword, 17)
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/// }
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/// DEFINE FF(x,y,z, round){
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/// IF round < 16
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/// RETURN (x ^ y ^ z)
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/// ELSE
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/// RETURN (x & y) | (x & z) | (y & z)
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/// FI
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/// }
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/// DEFINE GG(x, y, z, round){
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/// IF round < 16
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/// RETURN (x ^ y ^ z)
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/// ELSE
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/// RETURN (x & y) | (~x & z)
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/// FI
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/// }
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/// A[0] := __B.dword[3]
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/// B[0] := __B.dword[2]
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/// C[0] := __A.dword[3]
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/// D[0] := __A.dword[2]
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/// E[0] := __B.dword[1]
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/// F[0] := __B.dword[0]
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/// G[0] := __A.dword[1]
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/// H[0] := __A.dword[0]
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/// W[0] := __C.dword[0]
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/// W[1] := __C.dword[1]
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/// W[4] := __C.dword[2]
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/// W[5] := __C.dword[3]
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/// C[0] := ROL32(C[0], 9)
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/// D[0] := ROL32(D[0], 9)
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/// G[0] := ROL32(G[0], 19)
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/// H[0] := ROL32(H[0], 19)
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/// ROUND := __D & 0x3E
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/// IF ROUND < 16
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/// CONST := 0x79CC4519
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/// ELSE
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/// CONST := 0x7A879D8A
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/// FI
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/// CONST := ROL32(CONST,ROUND)
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/// FOR i:= 0 to 1
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/// S1 := ROL32((ROL32(A[i], 12) + E[i] + CONST), 7)
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/// S2 := S1 ^ ROL32(A[i], 12)
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/// T1 := FF(A[i], B[i], C[i], ROUND) + D[i] + S2 + (W[i] ^ W[i+4])
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/// T2 := GG(E[i], F[i], G[i], ROUND) + H[i] + S1 + W[i]
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/// D[i+1] := C[i]
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/// C[i+1] := ROL32(B[i],9)
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/// B[i+1] := A[i]
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/// A[i+1] := T1
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/// H[i+1] := G[i]
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/// G[i+1] := ROL32(F[i], 19)
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/// F[i+1] := E[i]
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/// E[i+1] := P0(T2)
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/// CONST := ROL32(CONST, 1)
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/// ENDFOR
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/// dst.dword[3] := A[2]
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/// dst.dword[2] := B[2]
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/// dst.dword[1] := E[2]
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/// dst.dword[0] := F[2]
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/// dst[MAX:128] := 0
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/// \endcode
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#define _mm_sm3rnds2_epi32(A, B, C, D) \
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(__m128i) __builtin_ia32_vsm3rnds2((__v4su)A, (__v4su)B, (__v4su)C, (int)D)
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#undef __DEFAULT_FN_ATTRS128
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#endif // __SM3INTRIN_H
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