mirror of
https://github.com/jart/cosmopolitan.git
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c9152b6f14
This change switches c++ exception handling from sjlj to standard dwarf. It's needed because clang for aarch64 doesn't support sjlj. It turns out that libunwind had a bare-metal configuration that made this easy to do. This change gets the new experimental cosmocc -mclang flag in a state of working so well that it can now be used to build all of llamafile and it goes 3x faster in terms of build latency, without trading away any perf. The int_fast16_t and int_fast32_t types are now always defined as 32-bit in the interest of having more abi consistency between cosmocc -mgcc and -mclang mode.
200 lines
5.9 KiB
C
200 lines
5.9 KiB
C
/*===--------------- sha512intrin.h - SHA512 intrinsics -----------------===
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*
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* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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* See https://llvm.org/LICENSE.txt for license information.
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* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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*
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*===-----------------------------------------------------------------------===
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*/
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#ifndef __IMMINTRIN_H
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#error "Never use <sha512intrin.h> directly; include <immintrin.h> instead."
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#endif // __IMMINTRIN_H
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#ifndef __SHA512INTRIN_H
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#define __SHA512INTRIN_H
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#define __DEFAULT_FN_ATTRS256 \
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__attribute__((__always_inline__, __nodebug__, __target__("sha512"), \
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__min_vector_width__(256)))
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/// This intrinisc is one of the two SHA512 message scheduling instructions.
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/// The intrinsic performs an intermediate calculation for the next four
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/// SHA512 message qwords. The calculated results are stored in \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// __m256i _mm256_sha512msg1_epi64(__m256i __A, __m128i __B)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c VSHA512MSG1 instruction.
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///
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/// \param __A
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/// A 256-bit vector of [4 x long long].
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/// \param __B
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/// A 128-bit vector of [2 x long long].
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/// \returns
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/// A 256-bit vector of [4 x long long].
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///
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/// \code{.operation}
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/// DEFINE ROR64(qword, n) {
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/// count := n % 64
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/// dest := (qword >> count) | (qword << (64 - count))
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/// RETURN dest
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/// }
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/// DEFINE SHR64(qword, n) {
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/// RETURN qword >> n
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/// }
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/// DEFINE s0(qword):
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/// RETURN ROR64(qword,1) ^ ROR64(qword, 8) ^ SHR64(qword, 7)
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/// }
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/// W[4] := __B.qword[0]
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/// W[3] := __A.qword[3]
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/// W[2] := __A.qword[2]
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/// W[1] := __A.qword[1]
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/// W[0] := __A.qword[0]
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/// dst.qword[3] := W[3] + s0(W[4])
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/// dst.qword[2] := W[2] + s0(W[3])
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/// dst.qword[1] := W[1] + s0(W[2])
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/// dst.qword[0] := W[0] + s0(W[1])
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/// dst[MAX:256] := 0
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/// \endcode
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static __inline__ __m256i __DEFAULT_FN_ATTRS256
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_mm256_sha512msg1_epi64(__m256i __A, __m128i __B) {
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return (__m256i)__builtin_ia32_vsha512msg1((__v4du)__A, (__v2du)__B);
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}
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/// This intrinisc is one of the two SHA512 message scheduling instructions.
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/// The intrinsic performs the final calculation for the next four SHA512
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/// message qwords. The calculated results are stored in \a dst.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// __m256i _mm256_sha512msg2_epi64(__m256i __A, __m256i __B)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c VSHA512MSG2 instruction.
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///
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/// \param __A
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/// A 256-bit vector of [4 x long long].
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/// \param __B
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/// A 256-bit vector of [4 x long long].
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/// \returns
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/// A 256-bit vector of [4 x long long].
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///
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/// \code{.operation}
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/// DEFINE ROR64(qword, n) {
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/// count := n % 64
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/// dest := (qword >> count) | (qword << (64 - count))
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/// RETURN dest
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/// }
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/// DEFINE SHR64(qword, n) {
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/// RETURN qword >> n
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/// }
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/// DEFINE s1(qword) {
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/// RETURN ROR64(qword,19) ^ ROR64(qword, 61) ^ SHR64(qword, 6)
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/// }
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/// W[14] := __B.qword[2]
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/// W[15] := __B.qword[3]
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/// W[16] := __A.qword[0] + s1(W[14])
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/// W[17] := __A.qword[1] + s1(W[15])
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/// W[18] := __A.qword[2] + s1(W[16])
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/// W[19] := __A.qword[3] + s1(W[17])
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/// dst.qword[3] := W[19]
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/// dst.qword[2] := W[18]
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/// dst.qword[1] := W[17]
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/// dst.qword[0] := W[16]
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/// dst[MAX:256] := 0
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/// \endcode
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static __inline__ __m256i __DEFAULT_FN_ATTRS256
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_mm256_sha512msg2_epi64(__m256i __A, __m256i __B) {
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return (__m256i)__builtin_ia32_vsha512msg2((__v4du)__A, (__v4du)__B);
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}
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/// This intrinisc performs two rounds of SHA512 operation using initial SHA512
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/// state (C,D,G,H) from \a __A, an initial SHA512 state (A,B,E,F) from
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/// \a __A, and a pre-computed sum of the next two round message qwords and
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/// the corresponding round constants from \a __C (only the two lower qwords
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/// of the third operand). The updated SHA512 state (A,B,E,F) is written to
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/// \a __A, and \a __A can be used as the updated state (C,D,G,H) in later
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/// rounds.
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///
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/// \headerfile <immintrin.h>
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///
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/// \code
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/// __m256i _mm256_sha512rnds2_epi64(__m256i __A, __m256i __B, __m128i __C)
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/// \endcode
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///
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/// This intrinsic corresponds to the \c VSHA512RNDS2 instruction.
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///
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/// \param __A
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/// A 256-bit vector of [4 x long long].
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/// \param __B
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/// A 256-bit vector of [4 x long long].
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/// \param __C
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/// A 128-bit vector of [2 x long long].
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/// \returns
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/// A 256-bit vector of [4 x long long].
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///
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/// \code{.operation}
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/// DEFINE ROR64(qword, n) {
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/// count := n % 64
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/// dest := (qword >> count) | (qword << (64 - count))
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/// RETURN dest
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/// }
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/// DEFINE SHR64(qword, n) {
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/// RETURN qword >> n
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/// }
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/// DEFINE cap_sigma0(qword) {
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/// RETURN ROR64(qword,28) ^ ROR64(qword, 34) ^ ROR64(qword, 39)
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/// }
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/// DEFINE cap_sigma1(qword) {
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/// RETURN ROR64(qword,14) ^ ROR64(qword, 18) ^ ROR64(qword, 41)
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/// }
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/// DEFINE MAJ(a,b,c) {
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/// RETURN (a & b) ^ (a & c) ^ (b & c)
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/// }
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/// DEFINE CH(e,f,g) {
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/// RETURN (e & f) ^ (g & ~e)
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/// }
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/// A[0] := __B.qword[3]
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/// B[0] := __B.qword[2]
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/// C[0] := __C.qword[3]
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/// D[0] := __C.qword[2]
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/// E[0] := __B.qword[1]
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/// F[0] := __B.qword[0]
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/// G[0] := __C.qword[1]
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/// H[0] := __C.qword[0]
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/// WK[0]:= __A.qword[0]
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/// WK[1]:= __A.qword[1]
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/// FOR i := 0 to 1:
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/// A[i+1] := CH(E[i], F[i], G[i]) +
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/// cap_sigma1(E[i]) + WK[i] + H[i] +
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/// MAJ(A[i], B[i], C[i]) +
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/// cap_sigma0(A[i])
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/// B[i+1] := A[i]
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/// C[i+1] := B[i]
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/// D[i+1] := C[i]
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/// E[i+1] := CH(E[i], F[i], G[i]) +
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/// cap_sigma1(E[i]) + WK[i] + H[i] + D[i]
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/// F[i+1] := E[i]
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/// G[i+1] := F[i]
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/// H[i+1] := G[i]
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/// ENDFOR
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/// dst.qword[3] := A[2]
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/// dst.qword[2] := B[2]
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/// dst.qword[1] := E[2]
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/// dst.qword[0] := F[2]
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/// dst[MAX:256] := 0
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/// \endcode
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static __inline__ __m256i __DEFAULT_FN_ATTRS256
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_mm256_sha512rnds2_epi64(__m256i __A, __m256i __B, __m128i __C) {
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return (__m256i)__builtin_ia32_vsha512rnds2((__v4du)__A, (__v4du)__B,
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(__v2du)__C);
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}
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#undef __DEFAULT_FN_ATTRS256
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#endif // __SHA512INTRIN_H
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