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linux-stable/arch/arm/mach-shmobile/headsmp.S

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ARM: shmobile: convert to SPDX identifiers This patch updates license to use SPDX-License-Identifier instead of verbose license text. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-07 01:43:23 +00:00
/* SPDX-License-Identifier: GPL-2.0
*
ARM: mach-shmobile: SMP base support Add SMP base support for R-Mobile / SH-Mobile processors. This patch contains all base code to support CONFIG_SMP regardless of ARCH_SHMOBILE processor type. Both local timer and CPU hotplug are supported, but no processor specific code is included. At this point only the default behavior is in place, so a single core will always be used even though CONFIG_SMP is enabled on multicore systems. The SMP Kconfig entry for arch/arm/Kconfig is excluded from this patch to simplify merging. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-12-14 07:56:55 +00:00
* SMP support for R-Mobile / SH-Mobile
*
* Copyright (C) 2010 Magnus Damm
* Copyright (C) 2010 Takashi Yoshii
*
* Based on vexpress, Copyright (c) 2003 ARM Limited, All Rights Reserved
*/
#include <linux/init.h>
ARM: shmobile: Allow use of boot code for non-SMP case Allow build of platsmp.c and headsmp.S even though SMP is disabled in the kernel configuration. With this in place it is possible to share the reset vector setup code with power management code that needs to be built even though SMP is disabled. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2014-06-06 07:20:10 +00:00
#include <linux/linkage.h>
#include <linux/threads.h>
ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+ ARMv6 and greater introduced a new instruction ("bx") which can be used to return from function calls. Recent CPUs perform better when the "bx lr" instruction is used rather than the "mov pc, lr" instruction, and this sequence is strongly recommended to be used by the ARM architecture manual (section A.4.1.1). We provide a new macro "ret" with all its variants for the condition code which will resolve to the appropriate instruction. Rather than doing this piecemeal, and miss some instances, change all the "mov pc" instances to use the new macro, with the exception of the "movs" instruction and the kprobes code. This allows us to detect the "mov pc, lr" case and fix it up - and also gives us the possibility of deploying this for other registers depending on the CPU selection. Reported-by: Will Deacon <will.deacon@arm.com> Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1 Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701_bootresume.S Tested-by: Andrew Lunn <andrew@lunn.ch> # Kirkwood Tested-by: Shawn Guo <shawn.guo@freescale.com> Tested-by: Tony Lindgren <tony@atomide.com> # OMAPs Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> # Armada XP, 375, 385 Acked-by: Sekhar Nori <nsekhar@ti.com> # DaVinci Acked-by: Christoffer Dall <christoffer.dall@linaro.org> # kvm/hyp Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> # PXA3xx Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> # Xen Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> # ARMv7M Tested-by: Simon Horman <horms+renesas@verge.net.au> # Shmobile Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-06-30 15:29:12 +00:00
#include <asm/assembler.h>
ARM: mm: Make virt_to_pfn() a static inline Making virt_to_pfn() a static inline taking a strongly typed (const void *) makes the contract of a passing a pointer of that type to the function explicit and exposes any misuse of the macro virt_to_pfn() acting polymorphic and accepting many types such as (void *), (unitptr_t) or (unsigned long) as arguments without warnings. Doing this is a bit intrusive: virt_to_pfn() requires PHYS_PFN_OFFSET and PAGE_SHIFT to be defined, and this is defined in <asm/page.h>, so this must be included *before* <asm/memory.h>. The use of macros were obscuring the unclear inclusion order here, as the macros would eventually be resolved, but a static inline like this cannot be compiled with unresolved macros. The naive solution to include <asm/page.h> at the top of <asm/memory.h> does not work, because <asm/memory.h> sometimes includes <asm/page.h> at the end of itself, which would create a confusing inclusion loop. So instead, take the approach to always unconditionally include <asm/page.h> at the end of <asm/memory.h> arch/arm uses <asm/memory.h> explicitly in a lot of places, however it turns out that if we just unconditionally include <asm/memory.h> into <asm/page.h> and switch all inclusions of <asm/memory.h> to <asm/page.h> instead, we enforce the right order and <asm/memory.h> will always have access to the definitions. Put an inclusion guard in place making it impossible to include <asm/memory.h> explicitly. Link: https://lore.kernel.org/linux-mm/20220701160004.2ffff4e5ab59a55499f4c736@linux-foundation.org/ Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-02 08:18:32 +00:00
#include <asm/page.h>
ARM: mach-shmobile: SMP base support Add SMP base support for R-Mobile / SH-Mobile processors. This patch contains all base code to support CONFIG_SMP regardless of ARCH_SHMOBILE processor type. Both local timer and CPU hotplug are supported, but no processor specific code is included. At this point only the default behavior is in place, so a single core will always be used even though CONFIG_SMP is enabled on multicore systems. The SMP Kconfig entry for arch/arm/Kconfig is excluded from this patch to simplify merging. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-12-14 07:56:55 +00:00
ARM: shmobile: Add watchdog support On R-Car Gen2 and RZ/G1 platforms, we use the SBAR registers to make non boot CPUs run a routine designed to bring up SMP and deal with hot plug. The value contained in the SBAR registers is not initialized by a WDT triggered reset, which means that after a WDT triggered reset we jump to the SMP bring up routine, preventing the system from executing the bootrom code. The purpose of this patch is to jump to the bootrom code in case of a WDT triggered reset, and keep the SMP functionality untouched. In order to tell if the code had been called due to the WDT overflowing we are testing WOVF from register RWTCSRA. The new function shmobile_boot_vector_gen2 isn't replacing shmobile_boot_vector for backward compatibility reasons. The kernel will install the best option (either shmobile_boot_vector or shmobile_boot_vector_gen2) to ICRAM1 after parsing the device tree, according to the amount of memory available. Since shmobile_boot_vector has become bigger, "reg" property of nodes compatible with "renesas,smp-sram" now need to be set to a value greater or equal to "<0 0x60>". Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> [simon: dropped #ifdef from common.h] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-02-28 17:40:22 +00:00
#define SCTLR_MMU 0x01
#define BOOTROM_ADDRESS 0xE6340000
#define RWTCSRA_ADDRESS 0xE6020004
#define RWTCSRA_WOVF 0x10
ARM: mach-shmobile: SMP base support Add SMP base support for R-Mobile / SH-Mobile processors. This patch contains all base code to support CONFIG_SMP regardless of ARCH_SHMOBILE processor type. Both local timer and CPU hotplug are supported, but no processor specific code is included. At this point only the default behavior is in place, so a single core will always be used even though CONFIG_SMP is enabled on multicore systems. The SMP Kconfig entry for arch/arm/Kconfig is excluded from this patch to simplify merging. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-12-14 07:56:55 +00:00
/*
* Reset vector for secondary CPUs.
* This will be mapped at address 0 by SBAR register.
* We need _long_ jump to the physical address.
*/
ARM: shmobile: Force ARM mode to compile reset vector for secondary CPUs Instructions start from boot vector must be ARM mode. This patch specify ARM mode explicitly and use 'bx' instruction to be able to change to Thumb mode. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-07-10 01:56:36 +00:00
.arm
ARM: mach-shmobile: SMP base support Add SMP base support for R-Mobile / SH-Mobile processors. This patch contains all base code to support CONFIG_SMP regardless of ARCH_SHMOBILE processor type. Both local timer and CPU hotplug are supported, but no processor specific code is included. At this point only the default behavior is in place, so a single core will always be used even though CONFIG_SMP is enabled on multicore systems. The SMP Kconfig entry for arch/arm/Kconfig is excluded from this patch to simplify merging. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-12-14 07:56:55 +00:00
.align 12
ARM: shmobile: Add SMP boot function and argument Add code for mach-shmobile to allow specifying boot function and argument. Will initially be used for SMP together with SCU but may in the future also be used for deep sleep resume. This patch removes one inline virtual to physical address conversion. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-06-10 09:19:36 +00:00
ENTRY(shmobile_boot_vector)
ARM: shmobile: Force ARM mode to compile reset vector for secondary CPUs Instructions start from boot vector must be ARM mode. This patch specify ARM mode explicitly and use 'bx' instruction to be able to change to Thumb mode. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-07-10 01:56:36 +00:00
ldr r1, 1f
bx r1
ARM: shmobile: Add SMP boot function and argument Add code for mach-shmobile to allow specifying boot function and argument. Will initially be used for SMP together with SCU but may in the future also be used for deep sleep resume. This patch removes one inline virtual to physical address conversion. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-06-10 09:19:36 +00:00
ENDPROC(shmobile_boot_vector)
ARM: shmobile: Insert align directives before 4 bytes data In thumb2 mode instructions are not align to 4 byte. This patch insert align directives before putting 4 byte data. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-07-10 01:56:37 +00:00
.align 2
ARM: shmobile: Add SMP boot function and argument Add code for mach-shmobile to allow specifying boot function and argument. Will initially be used for SMP together with SCU but may in the future also be used for deep sleep resume. This patch removes one inline virtual to physical address conversion. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-06-10 09:19:36 +00:00
.globl shmobile_boot_fn
shmobile_boot_fn:
1: .space 4
ARM: shmobile: Introduce shmobile_boot_size Introduce shmobile_boot_size that can be used by future SMP code to determine the size of the boot code that needs to be copied to internal SRAM. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-08-07 22:14:07 +00:00
.globl shmobile_boot_size
shmobile_boot_size:
.long . - shmobile_boot_vector
ARM: shmobile: Introduce per-CPU SMP boot / sleep code Add per-CPU SMP boot / sleep code that can be used by all SoCs included in mach-shmobile. The boot code reads out the per-CPU MPIDR id value and matches it with the value stored for any CPU number, and if there is a match and the boot function is set as well then the boot function will be executed. The sleep code simply uses WFI and then jumps back to the boot code to see if anyone has asked to wake up that CPU, if not it will sleep again. Signed-off-by: Magnus Damm <damm@opensource.se> [horms+renesas@verge.net.au: Remove trailing whitespace] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-07-31 18:38:18 +00:00
ARM: shmobile: Add watchdog support On R-Car Gen2 and RZ/G1 platforms, we use the SBAR registers to make non boot CPUs run a routine designed to bring up SMP and deal with hot plug. The value contained in the SBAR registers is not initialized by a WDT triggered reset, which means that after a WDT triggered reset we jump to the SMP bring up routine, preventing the system from executing the bootrom code. The purpose of this patch is to jump to the bootrom code in case of a WDT triggered reset, and keep the SMP functionality untouched. In order to tell if the code had been called due to the WDT overflowing we are testing WOVF from register RWTCSRA. The new function shmobile_boot_vector_gen2 isn't replacing shmobile_boot_vector for backward compatibility reasons. The kernel will install the best option (either shmobile_boot_vector or shmobile_boot_vector_gen2) to ICRAM1 after parsing the device tree, according to the amount of memory available. Since shmobile_boot_vector has become bigger, "reg" property of nodes compatible with "renesas,smp-sram" now need to be set to a value greater or equal to "<0 0x60>". Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> [simon: dropped #ifdef from common.h] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-02-28 17:40:22 +00:00
#ifdef CONFIG_ARCH_RCAR_GEN2
/*
* Reset vector for R-Car Gen2 and RZ/G1 secondary CPUs.
* This will be mapped at address 0 by SBAR register.
*/
ENTRY(shmobile_boot_vector_gen2)
mrc p15, 0, r0, c0, c0, 5 @ r0 = MPIDR
ldr r1, shmobile_boot_cpu_gen2
cmp r0, r1
bne shmobile_smp_continue_gen2
mrc p15, 0, r1, c1, c0, 0 @ r1 = SCTLR
and r0, r1, #SCTLR_MMU
cmp r0, #SCTLR_MMU
beq shmobile_smp_continue_gen2
ldr r0, rwtcsra
mov r1, #0
ldrb r1, [r0]
and r0, r1, #RWTCSRA_WOVF
cmp r0, #RWTCSRA_WOVF
bne shmobile_smp_continue_gen2
ldr r0, bootrom
bx r0
shmobile_smp_continue_gen2:
ldr r1, shmobile_boot_fn_gen2
bx r1
ENDPROC(shmobile_boot_vector_gen2)
.align 4
rwtcsra:
.word RWTCSRA_ADDRESS
bootrom:
.word BOOTROM_ADDRESS
.globl shmobile_boot_cpu_gen2
shmobile_boot_cpu_gen2:
.word 0x00000000
.align 2
.globl shmobile_boot_fn_gen2
shmobile_boot_fn_gen2:
.space 4
.globl shmobile_boot_size_gen2
shmobile_boot_size_gen2:
.long . - shmobile_boot_vector_gen2
#endif /* CONFIG_ARCH_RCAR_GEN2 */
ARM: shmobile: Introduce per-CPU SMP boot / sleep code Add per-CPU SMP boot / sleep code that can be used by all SoCs included in mach-shmobile. The boot code reads out the per-CPU MPIDR id value and matches it with the value stored for any CPU number, and if there is a match and the boot function is set as well then the boot function will be executed. The sleep code simply uses WFI and then jumps back to the boot code to see if anyone has asked to wake up that CPU, if not it will sleep again. Signed-off-by: Magnus Damm <damm@opensource.se> [horms+renesas@verge.net.au: Remove trailing whitespace] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-07-31 18:38:18 +00:00
/*
* Per-CPU SMP boot function/argument selection code based on MPIDR
*/
ENTRY(shmobile_smp_boot)
mrc p15, 0, r1, c0, c0, 5 @ r1 = MPIDR
ARM: shmobile: Remove shmobile_boot_arg CPU boot configuration writes to shmobile_boot_arg, which is located in the .text section, and thus should not be written to. As of commit 1d33a354bbb618ba ("ARM: shmobile: Per-CPU SMP boot / sleep code for SCU SoCs"), and ignoring accidental remainings, shmobile_boot_arg is always set to MPIDR_HWID_BITMASK by C code. Hence we can just hardcode this in the assembler code, and remove the variable, and thus also remove the need to write to this variable. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-15 12:20:08 +00:00
and r0, r1, #0xffffff @ MPIDR_HWID_BITMASK
@ r0 = cpu_logical_map() value
ARM: shmobile: Introduce per-CPU SMP boot / sleep code Add per-CPU SMP boot / sleep code that can be used by all SoCs included in mach-shmobile. The boot code reads out the per-CPU MPIDR id value and matches it with the value stored for any CPU number, and if there is a match and the boot function is set as well then the boot function will be executed. The sleep code simply uses WFI and then jumps back to the boot code to see if anyone has asked to wake up that CPU, if not it will sleep again. Signed-off-by: Magnus Damm <damm@opensource.se> [horms+renesas@verge.net.au: Remove trailing whitespace] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-07-31 18:38:18 +00:00
mov r1, #0 @ r1 = CPU index
ARM: shmobile: Move shmobile_smp_{mpidr, fn, arg}[] from .text to .bss If CONFIG_DEBUG_RODATA=y, the kernel crashes during system suspend: Freezing user space processes ... (elapsed 0.004 seconds) done. Freezing remaining freezable tasks ... (elapsed 0.002 seconds) done. PM: suspend of devices complete after 111.948 msecs PM: late suspend of devices complete after 1.086 msecs PM: noirq suspend of devices complete after 11.576 msecs Disabling non-boot CPUs ... Kernel panic - not syncing: Attempted to kill the idle task! 1014ec ---[ end Kernel panic - not syncing: Attempted to kill the idle task! CPU0: stopping This happens because the .text section is marked read-only, while the arrays shmobile_smp_mpidr[], shmobile_smp_fn[], and shmobile_smp_arg[] are being written to. Fix this by moving these arrays from the .text to the .bss section. This requires accessing them through PC-relative offsets. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Kees Cook <keescook@chromium.org> Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-15 12:20:07 +00:00
adr r2, 1f
ldmia r2, {r5, r6, r7}
add r5, r5, r2 @ array of per-cpu mpidr values
add r6, r6, r2 @ array of per-cpu functions
add r7, r7, r2 @ array of per-cpu arguments
ARM: shmobile: Introduce per-CPU SMP boot / sleep code Add per-CPU SMP boot / sleep code that can be used by all SoCs included in mach-shmobile. The boot code reads out the per-CPU MPIDR id value and matches it with the value stored for any CPU number, and if there is a match and the boot function is set as well then the boot function will be executed. The sleep code simply uses WFI and then jumps back to the boot code to see if anyone has asked to wake up that CPU, if not it will sleep again. Signed-off-by: Magnus Damm <damm@opensource.se> [horms+renesas@verge.net.au: Remove trailing whitespace] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-07-31 18:38:18 +00:00
shmobile_smp_boot_find_mpidr:
ldr r8, [r5, r1, lsl #2]
cmp r8, r0
bne shmobile_smp_boot_next
ldr r9, [r6, r1, lsl #2]
cmp r9, #0
bne shmobile_smp_boot_found
shmobile_smp_boot_next:
add r1, r1, #1
ARM: shmobile: Allow use of boot code for non-SMP case Allow build of platsmp.c and headsmp.S even though SMP is disabled in the kernel configuration. With this in place it is possible to share the reset vector setup code with power management code that needs to be built even though SMP is disabled. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2014-06-06 07:20:10 +00:00
cmp r1, #NR_CPUS
ARM: shmobile: Introduce per-CPU SMP boot / sleep code Add per-CPU SMP boot / sleep code that can be used by all SoCs included in mach-shmobile. The boot code reads out the per-CPU MPIDR id value and matches it with the value stored for any CPU number, and if there is a match and the boot function is set as well then the boot function will be executed. The sleep code simply uses WFI and then jumps back to the boot code to see if anyone has asked to wake up that CPU, if not it will sleep again. Signed-off-by: Magnus Damm <damm@opensource.se> [horms+renesas@verge.net.au: Remove trailing whitespace] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-07-31 18:38:18 +00:00
blo shmobile_smp_boot_find_mpidr
b shmobile_smp_sleep
shmobile_smp_boot_found:
ldr r0, [r7, r1, lsl #2]
ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+ ARMv6 and greater introduced a new instruction ("bx") which can be used to return from function calls. Recent CPUs perform better when the "bx lr" instruction is used rather than the "mov pc, lr" instruction, and this sequence is strongly recommended to be used by the ARM architecture manual (section A.4.1.1). We provide a new macro "ret" with all its variants for the condition code which will resolve to the appropriate instruction. Rather than doing this piecemeal, and miss some instances, change all the "mov pc" instances to use the new macro, with the exception of the "movs" instruction and the kprobes code. This allows us to detect the "mov pc, lr" case and fix it up - and also gives us the possibility of deploying this for other registers depending on the CPU selection. Reported-by: Will Deacon <will.deacon@arm.com> Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1 Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701_bootresume.S Tested-by: Andrew Lunn <andrew@lunn.ch> # Kirkwood Tested-by: Shawn Guo <shawn.guo@freescale.com> Tested-by: Tony Lindgren <tony@atomide.com> # OMAPs Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> # Armada XP, 375, 385 Acked-by: Sekhar Nori <nsekhar@ti.com> # DaVinci Acked-by: Christoffer Dall <christoffer.dall@linaro.org> # kvm/hyp Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> # PXA3xx Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> # Xen Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> # ARMv7M Tested-by: Simon Horman <horms+renesas@verge.net.au> # Shmobile Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-06-30 15:29:12 +00:00
ret r9
ARM: shmobile: Introduce per-CPU SMP boot / sleep code Add per-CPU SMP boot / sleep code that can be used by all SoCs included in mach-shmobile. The boot code reads out the per-CPU MPIDR id value and matches it with the value stored for any CPU number, and if there is a match and the boot function is set as well then the boot function will be executed. The sleep code simply uses WFI and then jumps back to the boot code to see if anyone has asked to wake up that CPU, if not it will sleep again. Signed-off-by: Magnus Damm <damm@opensource.se> [horms+renesas@verge.net.au: Remove trailing whitespace] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-07-31 18:38:18 +00:00
ENDPROC(shmobile_smp_boot)
ENTRY(shmobile_smp_sleep)
wfi
b shmobile_smp_boot
ENDPROC(shmobile_smp_sleep)
ARM: shmobile: Move shmobile_smp_{mpidr, fn, arg}[] from .text to .bss If CONFIG_DEBUG_RODATA=y, the kernel crashes during system suspend: Freezing user space processes ... (elapsed 0.004 seconds) done. Freezing remaining freezable tasks ... (elapsed 0.002 seconds) done. PM: suspend of devices complete after 111.948 msecs PM: late suspend of devices complete after 1.086 msecs PM: noirq suspend of devices complete after 11.576 msecs Disabling non-boot CPUs ... Kernel panic - not syncing: Attempted to kill the idle task! 1014ec ---[ end Kernel panic - not syncing: Attempted to kill the idle task! CPU0: stopping This happens because the .text section is marked read-only, while the arrays shmobile_smp_mpidr[], shmobile_smp_fn[], and shmobile_smp_arg[] are being written to. Fix this by moving these arrays from the .text to the .bss section. This requires accessing them through PC-relative offsets. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Kees Cook <keescook@chromium.org> Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-15 12:20:07 +00:00
.align 2
1: .long shmobile_smp_mpidr - .
.long shmobile_smp_fn - 1b
.long shmobile_smp_arg - 1b
.bss
ARM: shmobile: Introduce per-CPU SMP boot / sleep code Add per-CPU SMP boot / sleep code that can be used by all SoCs included in mach-shmobile. The boot code reads out the per-CPU MPIDR id value and matches it with the value stored for any CPU number, and if there is a match and the boot function is set as well then the boot function will be executed. The sleep code simply uses WFI and then jumps back to the boot code to see if anyone has asked to wake up that CPU, if not it will sleep again. Signed-off-by: Magnus Damm <damm@opensource.se> [horms+renesas@verge.net.au: Remove trailing whitespace] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-07-31 18:38:18 +00:00
.globl shmobile_smp_mpidr
shmobile_smp_mpidr:
ARM: shmobile: Move shmobile_smp_{mpidr, fn, arg}[] from .text to .bss If CONFIG_DEBUG_RODATA=y, the kernel crashes during system suspend: Freezing user space processes ... (elapsed 0.004 seconds) done. Freezing remaining freezable tasks ... (elapsed 0.002 seconds) done. PM: suspend of devices complete after 111.948 msecs PM: late suspend of devices complete after 1.086 msecs PM: noirq suspend of devices complete after 11.576 msecs Disabling non-boot CPUs ... Kernel panic - not syncing: Attempted to kill the idle task! 1014ec ---[ end Kernel panic - not syncing: Attempted to kill the idle task! CPU0: stopping This happens because the .text section is marked read-only, while the arrays shmobile_smp_mpidr[], shmobile_smp_fn[], and shmobile_smp_arg[] are being written to. Fix this by moving these arrays from the .text to the .bss section. This requires accessing them through PC-relative offsets. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Kees Cook <keescook@chromium.org> Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-15 12:20:07 +00:00
.space NR_CPUS * 4
ARM: shmobile: Introduce per-CPU SMP boot / sleep code Add per-CPU SMP boot / sleep code that can be used by all SoCs included in mach-shmobile. The boot code reads out the per-CPU MPIDR id value and matches it with the value stored for any CPU number, and if there is a match and the boot function is set as well then the boot function will be executed. The sleep code simply uses WFI and then jumps back to the boot code to see if anyone has asked to wake up that CPU, if not it will sleep again. Signed-off-by: Magnus Damm <damm@opensource.se> [horms+renesas@verge.net.au: Remove trailing whitespace] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-07-31 18:38:18 +00:00
.globl shmobile_smp_fn
shmobile_smp_fn:
ARM: shmobile: Move shmobile_smp_{mpidr, fn, arg}[] from .text to .bss If CONFIG_DEBUG_RODATA=y, the kernel crashes during system suspend: Freezing user space processes ... (elapsed 0.004 seconds) done. Freezing remaining freezable tasks ... (elapsed 0.002 seconds) done. PM: suspend of devices complete after 111.948 msecs PM: late suspend of devices complete after 1.086 msecs PM: noirq suspend of devices complete after 11.576 msecs Disabling non-boot CPUs ... Kernel panic - not syncing: Attempted to kill the idle task! 1014ec ---[ end Kernel panic - not syncing: Attempted to kill the idle task! CPU0: stopping This happens because the .text section is marked read-only, while the arrays shmobile_smp_mpidr[], shmobile_smp_fn[], and shmobile_smp_arg[] are being written to. Fix this by moving these arrays from the .text to the .bss section. This requires accessing them through PC-relative offsets. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Kees Cook <keescook@chromium.org> Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-15 12:20:07 +00:00
.space NR_CPUS * 4
ARM: shmobile: Introduce per-CPU SMP boot / sleep code Add per-CPU SMP boot / sleep code that can be used by all SoCs included in mach-shmobile. The boot code reads out the per-CPU MPIDR id value and matches it with the value stored for any CPU number, and if there is a match and the boot function is set as well then the boot function will be executed. The sleep code simply uses WFI and then jumps back to the boot code to see if anyone has asked to wake up that CPU, if not it will sleep again. Signed-off-by: Magnus Damm <damm@opensource.se> [horms+renesas@verge.net.au: Remove trailing whitespace] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-07-31 18:38:18 +00:00
.globl shmobile_smp_arg
shmobile_smp_arg:
ARM: shmobile: Move shmobile_smp_{mpidr, fn, arg}[] from .text to .bss If CONFIG_DEBUG_RODATA=y, the kernel crashes during system suspend: Freezing user space processes ... (elapsed 0.004 seconds) done. Freezing remaining freezable tasks ... (elapsed 0.002 seconds) done. PM: suspend of devices complete after 111.948 msecs PM: late suspend of devices complete after 1.086 msecs PM: noirq suspend of devices complete after 11.576 msecs Disabling non-boot CPUs ... Kernel panic - not syncing: Attempted to kill the idle task! 1014ec ---[ end Kernel panic - not syncing: Attempted to kill the idle task! CPU0: stopping This happens because the .text section is marked read-only, while the arrays shmobile_smp_mpidr[], shmobile_smp_fn[], and shmobile_smp_arg[] are being written to. Fix this by moving these arrays from the .text to the .bss section. This requires accessing them through PC-relative offsets. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Kees Cook <keescook@chromium.org> Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-15 12:20:07 +00:00
.space NR_CPUS * 4
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