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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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268 lines
4.8 KiB
Text
268 lines
4.8 KiB
Text
![]() |
/*
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* Hisilicon Ltd. HiP04 SoC
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*
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* Copyright (C) 2013-2014 Hisilicon Ltd.
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* Copyright (C) 2013-2014 Linaro Ltd.
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*
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* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/ {
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/* memory bus is 64-bit */
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &uart0;
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};
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bootwrapper {
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compatible = "hisilicon,hip04-bootwrapper";
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boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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core3 {
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cpu = <&CPU7>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&CPU8>;
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};
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core1 {
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cpu = <&CPU9>;
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};
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core2 {
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cpu = <&CPU10>;
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};
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core3 {
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cpu = <&CPU11>;
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};
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};
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cluster3 {
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core0 {
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cpu = <&CPU12>;
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};
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core1 {
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cpu = <&CPU13>;
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};
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core2 {
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cpu = <&CPU14>;
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};
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core3 {
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cpu = <&CPU15>;
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};
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};
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};
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <2>;
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <3>;
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};
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CPU4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x100>;
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};
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CPU5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x101>;
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};
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CPU6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x102>;
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};
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CPU7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x103>;
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};
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CPU8: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x200>;
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};
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CPU9: cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x201>;
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};
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CPU10: cpu@202 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x202>;
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};
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CPU11: cpu@203 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x203>;
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};
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CPU12: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x300>;
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};
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CPU13: cpu@301 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x301>;
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};
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CPU14: cpu@302 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x302>;
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};
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CPU15: cpu@303 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x303>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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};
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clk_50m: clk_50m {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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};
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clk_168m: clk_168m {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <168000000>;
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};
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soc {
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/* It's a 32-bit SoC. */
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges = <0 0 0xe0000000 0x10000000>;
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gic: interrupt-controller@c01000 {
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compatible = "hisilicon,hip04-intc";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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interrupts = <1 9 0xf04>;
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reg = <0xc01000 0x1000>, <0xc02000 0x1000>,
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<0xc04000 0x2000>, <0xc06000 0x2000>;
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};
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sysctrl: sysctrl {
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compatible = "hisilicon,sysctrl";
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reg = <0x3e00000 0x00100000>;
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};
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fabric: fabric {
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compatible = "hisilicon,hip04-fabric";
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reg = <0x302a000 0x1000>;
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};
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dual_timer0: dual_timer@3000000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x3000000 0x1000>;
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interrupts = <0 224 4>;
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clocks = <&clk_50m>, <&clk_50m>;
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clock-names = "apb_pclk";
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};
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arm-pmu {
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compatible = "arm,cortex-a15-pmu";
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interrupts = <0 64 4>,
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<0 65 4>,
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<0 66 4>,
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<0 67 4>,
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<0 68 4>,
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<0 69 4>,
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<0 70 4>,
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<0 71 4>,
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<0 72 4>,
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<0 73 4>,
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<0 74 4>,
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<0 75 4>,
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<0 76 4>,
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<0 77 4>,
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<0 78 4>,
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<0 79 4>;
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};
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uart0: uart@4007000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x4007000 0x1000>;
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interrupts = <0 381 4>;
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clocks = <&clk_168m>;
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clock-names = "uartclk";
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reg-shift = <2>;
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status = "disabled";
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};
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sata0: sata@a000000 {
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compatible = "hisilicon,hisi-ahci";
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reg = <0xa000000 0x1000000>;
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interrupts = <0 372 4>;
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};
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};
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};
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