2019-06-01 08:08:37 +00:00
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// SPDX-License-Identifier: GPL-2.0-only
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2010-01-21 14:46:42 +00:00
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/*
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2011-06-06 07:16:30 +00:00
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* Memory-mapped interface driver for DW SPI Core
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2010-01-21 14:46:42 +00:00
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*
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* Copyright (c) 2010, Octasic semiconductor.
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*/
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#include <linux/clk.h>
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2011-01-11 12:43:52 +00:00
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#include <linux/err.h>
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2010-01-21 14:46:42 +00:00
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
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#include <linux/slab.h>
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2010-01-21 14:46:42 +00:00
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#include <linux/spi/spi.h>
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2011-02-28 19:47:12 +00:00
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#include <linux/scatterlist.h>
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2018-07-27 19:53:56 +00:00
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#include <linux/mfd/syscon.h>
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2011-07-03 19:44:29 +00:00
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#include <linux/module.h>
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2014-06-13 13:36:18 +00:00
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#include <linux/of.h>
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#include <linux/of_platform.h>
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2018-12-03 03:15:50 +00:00
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#include <linux/acpi.h>
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2015-10-14 20:12:25 +00:00
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#include <linux/property.h>
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2018-07-27 19:53:56 +00:00
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#include <linux/regmap.h>
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2011-02-28 19:47:12 +00:00
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2011-06-06 07:16:30 +00:00
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#include "spi-dw.h"
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2010-01-21 14:46:42 +00:00
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#define DRIVER_NAME "dw_spi_mmio"
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struct dw_spi_mmio {
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2010-01-21 16:55:42 +00:00
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struct dw_spi dws;
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struct clk *clk;
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2019-03-19 15:52:07 +00:00
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struct clk *pclk;
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2018-07-27 19:53:56 +00:00
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void *priv;
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2010-01-21 14:46:42 +00:00
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};
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2018-07-27 19:53:56 +00:00
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#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
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#define OCELOT_IF_SI_OWNER_OFFSET 4
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2018-08-29 12:45:48 +00:00
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#define JAGUAR2_IF_SI_OWNER_OFFSET 6
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2018-08-31 11:40:46 +00:00
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#define MSCC_IF_SI_OWNER_MASK GENMASK(1, 0)
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2018-07-27 19:53:56 +00:00
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#define MSCC_IF_SI_OWNER_SISL 0
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#define MSCC_IF_SI_OWNER_SIBM 1
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#define MSCC_IF_SI_OWNER_SIMC 2
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#define MSCC_SPI_MST_SW_MODE 0x14
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#define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
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#define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) (x << 5)
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struct dw_spi_mscc {
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struct regmap *syscon;
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void __iomem *spi_mst;
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};
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/*
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* The Designware SPI controller (referred to as master in the documentation)
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* automatically deasserts chip select when the tx fifo is empty. The chip
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* selects then needs to be either driven as GPIOs or, for the first 4 using the
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* the SPI boot controller registers. the final chip select is an OR gate
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* between the Designware SPI controller and the SPI boot controller.
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*/
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static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
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{
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struct dw_spi *dws = spi_master_get_devdata(spi->master);
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struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
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struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
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u32 cs = spi->chip_select;
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if (cs < 4) {
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u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;
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if (!enable)
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sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));
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writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
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}
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dw_spi_set_cs(spi, enable);
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}
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static int dw_spi_mscc_init(struct platform_device *pdev,
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2018-08-29 12:45:48 +00:00
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struct dw_spi_mmio *dwsmmio,
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const char *cpu_syscon, u32 if_si_owner_offset)
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2018-07-27 19:53:56 +00:00
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{
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struct dw_spi_mscc *dwsmscc;
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struct resource *res;
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dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
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if (!dwsmscc)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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dwsmscc->spi_mst = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(dwsmscc->spi_mst)) {
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dev_err(&pdev->dev, "SPI_MST region map failed\n");
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return PTR_ERR(dwsmscc->spi_mst);
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}
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2018-08-29 12:45:48 +00:00
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dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);
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2018-07-27 19:53:56 +00:00
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if (IS_ERR(dwsmscc->syscon))
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return PTR_ERR(dwsmscc->syscon);
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/* Deassert all CS */
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writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
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/* Select the owner of the SI interface */
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regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
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2018-08-31 11:40:46 +00:00
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MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
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2018-08-29 12:45:48 +00:00
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MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);
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2018-07-27 19:53:56 +00:00
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dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
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dwsmmio->priv = dwsmscc;
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return 0;
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}
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2018-08-29 12:45:48 +00:00
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static int dw_spi_mscc_ocelot_init(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio)
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{
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return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",
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OCELOT_IF_SI_OWNER_OFFSET);
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}
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static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio)
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{
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return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",
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JAGUAR2_IF_SI_OWNER_OFFSET);
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}
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2018-10-11 11:20:07 +00:00
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static int dw_spi_alpine_init(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio)
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{
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dwsmmio->dws.cs_override = 1;
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return 0;
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}
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2012-12-07 16:57:14 +00:00
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static int dw_spi_mmio_probe(struct platform_device *pdev)
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2010-01-21 14:46:42 +00:00
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{
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2018-07-27 19:53:56 +00:00
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int (*init_func)(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio);
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2010-01-21 14:46:42 +00:00
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struct dw_spi_mmio *dwsmmio;
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struct dw_spi *dws;
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int ret;
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2014-06-13 13:36:18 +00:00
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int num_cs;
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2010-01-21 14:46:42 +00:00
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2013-12-30 18:30:44 +00:00
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dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
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GFP_KERNEL);
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if (!dwsmmio)
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return -ENOMEM;
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2010-01-21 14:46:42 +00:00
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dws = &dwsmmio->dws;
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/* Get basic io resource and map it */
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2019-07-10 11:42:30 +00:00
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dws->regs = devm_platform_ioremap_resource(pdev, 0);
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2013-12-30 18:30:44 +00:00
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if (IS_ERR(dws->regs)) {
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dev_err(&pdev->dev, "SPI region map failed\n");
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return PTR_ERR(dws->regs);
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2010-01-21 14:46:42 +00:00
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}
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dws->irq = platform_get_irq(pdev, 0);
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if (dws->irq < 0) {
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dev_err(&pdev->dev, "no irq resource?\n");
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2013-12-30 18:30:44 +00:00
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return dws->irq; /* -ENXIO */
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2010-01-21 14:46:42 +00:00
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}
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2013-12-30 18:30:44 +00:00
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dwsmmio->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(dwsmmio->clk))
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return PTR_ERR(dwsmmio->clk);
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2013-12-30 18:30:45 +00:00
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ret = clk_prepare_enable(dwsmmio->clk);
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2013-12-30 18:30:44 +00:00
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if (ret)
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return ret;
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2010-01-21 14:46:42 +00:00
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2019-03-19 15:52:07 +00:00
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/* Optional clock needed to access the registers */
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dwsmmio->pclk = devm_clk_get_optional(&pdev->dev, "pclk");
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if (IS_ERR(dwsmmio->pclk))
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return PTR_ERR(dwsmmio->pclk);
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ret = clk_prepare_enable(dwsmmio->pclk);
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if (ret)
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goto out_clk;
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2014-01-26 08:14:32 +00:00
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dws->bus_num = pdev->id;
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2014-06-13 13:36:18 +00:00
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2010-01-21 14:46:42 +00:00
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dws->max_freq = clk_get_rate(dwsmmio->clk);
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2015-10-14 20:12:25 +00:00
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device_property_read_u32(&pdev->dev, "reg-io-width", &dws->reg_io_width);
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2015-08-18 20:21:53 +00:00
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2014-06-13 13:36:18 +00:00
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num_cs = 4;
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2015-10-14 20:12:25 +00:00
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device_property_read_u32(&pdev->dev, "num-cs", &num_cs);
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2014-06-13 13:36:18 +00:00
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dws->num_cs = num_cs;
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2018-07-27 19:53:56 +00:00
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init_func = device_get_match_data(&pdev->dev);
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if (init_func) {
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ret = init_func(pdev, dwsmmio);
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if (ret)
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goto out;
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}
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2013-12-30 18:30:44 +00:00
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ret = dw_spi_add_host(&pdev->dev, dws);
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2010-01-21 14:46:42 +00:00
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if (ret)
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2013-12-30 18:30:44 +00:00
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goto out;
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2010-01-21 14:46:42 +00:00
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platform_set_drvdata(pdev, dwsmmio);
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return 0;
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2013-12-30 18:30:44 +00:00
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out:
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2019-03-19 15:52:07 +00:00
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clk_disable_unprepare(dwsmmio->pclk);
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out_clk:
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2013-12-30 18:30:45 +00:00
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clk_disable_unprepare(dwsmmio->clk);
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2010-01-21 14:46:42 +00:00
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return ret;
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}
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2012-12-07 16:57:14 +00:00
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static int dw_spi_mmio_remove(struct platform_device *pdev)
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2010-01-21 14:46:42 +00:00
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{
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struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);
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dw_spi_remove_host(&dwsmmio->dws);
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2019-03-19 15:52:07 +00:00
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clk_disable_unprepare(dwsmmio->pclk);
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2017-04-18 18:09:06 +00:00
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clk_disable_unprepare(dwsmmio->clk);
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2010-01-21 14:46:42 +00:00
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return 0;
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}
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2014-06-13 13:36:18 +00:00
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static const struct of_device_id dw_spi_mmio_of_match[] = {
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{ .compatible = "snps,dw-apb-ssi", },
|
2018-08-29 12:45:48 +00:00
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{ .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
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{ .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
|
2018-10-11 11:20:07 +00:00
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{ .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
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2014-06-13 13:36:18 +00:00
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{ /* end of table */}
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};
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MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
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2018-12-03 03:15:50 +00:00
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static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
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{"HISI0173", 0},
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{},
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};
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MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);
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2010-01-21 14:46:42 +00:00
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static struct platform_driver dw_spi_mmio_driver = {
|
2011-10-05 17:29:49 +00:00
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.probe = dw_spi_mmio_probe,
|
2012-12-07 16:57:14 +00:00
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.remove = dw_spi_mmio_remove,
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2010-01-21 14:46:42 +00:00
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.driver = {
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.name = DRIVER_NAME,
|
2014-06-13 13:36:18 +00:00
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.of_match_table = dw_spi_mmio_of_match,
|
2018-12-03 03:15:50 +00:00
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.acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match),
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2010-01-21 14:46:42 +00:00
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},
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};
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2011-10-05 17:29:49 +00:00
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module_platform_driver(dw_spi_mmio_driver);
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2010-01-21 14:46:42 +00:00
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MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
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MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
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MODULE_LICENSE("GPL v2");
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