2013-08-16 03:08:55 +00:00
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/*
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* drivers/spi/spi-fsl-dspi.c
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*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* Freescale DSPI driver
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* This file contains a driver for the Freescale DSPI
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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2014-09-29 02:57:06 +00:00
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#include <linux/clk.h>
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#include <linux/delay.h>
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2016-11-10 12:19:15 +00:00
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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2014-09-29 02:57:06 +00:00
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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2013-08-16 03:08:55 +00:00
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#include <linux/kernel.h>
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2015-04-03 20:39:31 +00:00
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#include <linux/math64.h>
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2013-08-16 03:08:55 +00:00
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#include <linux/module.h>
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2014-09-29 02:57:06 +00:00
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#include <linux/of.h>
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#include <linux/of_device.h>
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2015-06-12 16:55:22 +00:00
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#include <linux/pinctrl/consumer.h>
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2013-08-16 03:08:55 +00:00
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#include <linux/platform_device.h>
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2014-09-29 02:57:06 +00:00
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#include <linux/pm_runtime.h>
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2014-02-12 07:29:05 +00:00
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#include <linux/regmap.h>
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2013-08-16 03:08:55 +00:00
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#include <linux/sched.h>
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#include <linux/spi/spi.h>
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2017-10-27 22:23:01 +00:00
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#include <linux/spi/spi-fsl-dspi.h>
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2013-08-16 03:08:55 +00:00
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#include <linux/spi/spi_bitbang.h>
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2015-04-03 20:39:31 +00:00
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#include <linux/time.h>
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2013-08-16 03:08:55 +00:00
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#define DRIVER_NAME "fsl-dspi"
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#define DSPI_FIFO_SIZE 4
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2016-11-10 12:19:15 +00:00
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#define DSPI_DMA_BUFSIZE (DSPI_FIFO_SIZE * 1024)
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2013-08-16 03:08:55 +00:00
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#define SPI_MCR 0x00
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#define SPI_MCR_MASTER (1 << 31)
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#define SPI_MCR_PCSIS (0x3F << 16)
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#define SPI_MCR_CLR_TXF (1 << 11)
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#define SPI_MCR_CLR_RXF (1 << 10)
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#define SPI_TCR 0x08
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2015-06-09 11:45:37 +00:00
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#define SPI_TCR_GET_TCNT(x) (((x) & 0xffff0000) >> 16)
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2013-08-16 03:08:55 +00:00
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2014-11-04 08:20:18 +00:00
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#define SPI_CTAR(x) (0x0c + (((x) & 0x3) * 4))
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2013-08-16 03:08:55 +00:00
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#define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27)
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#define SPI_CTAR_CPOL(x) ((x) << 26)
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#define SPI_CTAR_CPHA(x) ((x) << 25)
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#define SPI_CTAR_LSBFE(x) ((x) << 24)
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2015-04-03 20:39:31 +00:00
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#define SPI_CTAR_PCSSCK(x) (((x) & 0x00000003) << 22)
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2013-08-16 03:08:55 +00:00
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#define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20)
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#define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18)
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#define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16)
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#define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12)
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#define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8)
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#define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4)
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#define SPI_CTAR_BR(x) ((x) & 0x0000000f)
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2015-04-03 20:39:31 +00:00
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#define SPI_CTAR_SCALE_BITS 0xf
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2013-08-16 03:08:55 +00:00
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#define SPI_CTAR0_SLAVE 0x0c
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#define SPI_SR 0x2c
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#define SPI_SR_EOQF 0x10000000
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2015-06-09 11:45:27 +00:00
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#define SPI_SR_TCFQF 0x80000000
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2016-10-17 10:02:34 +00:00
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#define SPI_SR_CLEAR 0xdaad0000
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2013-08-16 03:08:55 +00:00
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2016-11-10 12:19:15 +00:00
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#define SPI_RSER_TFFFE BIT(25)
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#define SPI_RSER_TFFFD BIT(24)
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#define SPI_RSER_RFDFE BIT(17)
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#define SPI_RSER_RFDFD BIT(16)
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2013-08-16 03:08:55 +00:00
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#define SPI_RSER 0x30
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#define SPI_RSER_EOQFE 0x10000000
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2015-06-09 11:45:27 +00:00
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#define SPI_RSER_TCFQE 0x80000000
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2013-08-16 03:08:55 +00:00
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#define SPI_PUSHR 0x34
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2018-06-20 07:34:33 +00:00
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#define SPI_PUSHR_CMD_CONT (1 << 15)
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#define SPI_PUSHR_CONT (SPI_PUSHR_CMD_CONT << 16)
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#define SPI_PUSHR_CMD_CTAS(x) (((x) & 0x0003) << 12)
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#define SPI_PUSHR_CTAS(x) (SPI_PUSHR_CMD_CTAS(x) << 16)
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#define SPI_PUSHR_CMD_EOQ (1 << 11)
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#define SPI_PUSHR_EOQ (SPI_PUSHR_CMD_EOQ << 16)
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#define SPI_PUSHR_CMD_CTCNT (1 << 10)
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#define SPI_PUSHR_CTCNT (SPI_PUSHR_CMD_CTCNT << 16)
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#define SPI_PUSHR_CMD_PCS(x) ((1 << x) & 0x003f)
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#define SPI_PUSHR_PCS(x) (SPI_PUSHR_CMD_PCS(x) << 16)
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2013-08-16 03:08:55 +00:00
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#define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff)
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#define SPI_PUSHR_SLAVE 0x34
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#define SPI_POPR 0x38
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#define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff)
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#define SPI_TXFR0 0x3c
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#define SPI_TXFR1 0x40
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#define SPI_TXFR2 0x44
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#define SPI_TXFR3 0x48
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#define SPI_RXFR0 0x7c
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#define SPI_RXFR1 0x80
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#define SPI_RXFR2 0x84
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#define SPI_RXFR3 0x88
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#define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
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#define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf)
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#define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf)
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#define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7)
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#define SPI_CS_INIT 0x01
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#define SPI_CS_ASSERT 0x02
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#define SPI_CS_DROP 0x04
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2016-11-10 12:19:15 +00:00
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#define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
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2013-08-16 03:08:55 +00:00
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struct chip_data {
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u32 ctar_val;
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u16 void_write_data;
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};
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2015-06-09 11:45:27 +00:00
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enum dspi_trans_mode {
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DSPI_EOQ_MODE = 0,
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DSPI_TCFQ_MODE,
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2016-11-10 12:19:15 +00:00
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DSPI_DMA_MODE,
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2015-06-09 11:45:27 +00:00
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};
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struct fsl_dspi_devtype_data {
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enum dspi_trans_mode trans_mode;
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2016-03-21 20:11:52 +00:00
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u8 max_clock_factor;
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2015-06-09 11:45:27 +00:00
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};
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static const struct fsl_dspi_devtype_data vf610_data = {
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2016-11-10 12:19:15 +00:00
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.trans_mode = DSPI_DMA_MODE,
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2016-03-21 20:11:52 +00:00
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.max_clock_factor = 2,
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2015-06-09 11:45:27 +00:00
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};
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static const struct fsl_dspi_devtype_data ls1021a_v1_data = {
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.trans_mode = DSPI_TCFQ_MODE,
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2016-03-21 20:11:52 +00:00
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.max_clock_factor = 8,
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2015-06-09 11:45:27 +00:00
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};
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static const struct fsl_dspi_devtype_data ls2085a_data = {
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.trans_mode = DSPI_TCFQ_MODE,
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2016-03-21 20:11:52 +00:00
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.max_clock_factor = 8,
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2015-06-09 11:45:27 +00:00
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};
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2017-10-27 22:23:01 +00:00
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static const struct fsl_dspi_devtype_data coldfire_data = {
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.trans_mode = DSPI_EOQ_MODE,
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.max_clock_factor = 8,
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};
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2016-11-10 12:19:15 +00:00
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struct fsl_dspi_dma {
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2016-11-22 07:01:30 +00:00
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/* Length of transfer in words of DSPI_FIFO_SIZE */
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2016-11-10 12:19:15 +00:00
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u32 curr_xfer_len;
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u32 *tx_dma_buf;
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struct dma_chan *chan_tx;
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dma_addr_t tx_dma_phys;
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struct completion cmd_tx_complete;
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struct dma_async_tx_descriptor *tx_desc;
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u32 *rx_dma_buf;
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struct dma_chan *chan_rx;
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dma_addr_t rx_dma_phys;
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struct completion cmd_rx_complete;
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struct dma_async_tx_descriptor *rx_desc;
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};
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2013-08-16 03:08:55 +00:00
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struct fsl_dspi {
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2015-01-27 10:57:22 +00:00
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struct spi_master *master;
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2013-08-16 03:08:55 +00:00
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struct platform_device *pdev;
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2014-02-12 07:29:05 +00:00
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struct regmap *regmap;
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2013-08-16 03:08:55 +00:00
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int irq;
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2014-02-12 07:29:06 +00:00
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struct clk *clk;
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2013-08-16 03:08:55 +00:00
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2014-02-12 07:29:06 +00:00
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struct spi_transfer *cur_transfer;
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2015-01-27 10:57:22 +00:00
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struct spi_message *cur_msg;
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2013-08-16 03:08:55 +00:00
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struct chip_data *cur_chip;
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size_t len;
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2018-06-20 07:34:35 +00:00
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const void *tx;
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2013-08-16 03:08:55 +00:00
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void *rx;
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void *rx_end;
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u16 void_write_data;
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2018-06-20 07:34:33 +00:00
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u16 tx_cmd;
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2018-06-20 07:34:35 +00:00
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u8 bits_per_word;
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u8 bytes_per_word;
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2016-08-16 09:50:20 +00:00
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const struct fsl_dspi_devtype_data *devtype_data;
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2013-08-16 03:08:55 +00:00
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2014-02-12 07:29:06 +00:00
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wait_queue_head_t waitq;
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u32 waitflags;
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2015-06-09 11:45:37 +00:00
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2016-11-10 12:19:15 +00:00
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struct fsl_dspi_dma *dma;
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2013-08-16 03:08:55 +00:00
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};
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2018-06-20 07:34:35 +00:00
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static u16 dspi_pop_tx(struct fsl_dspi *dspi)
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{
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u16 txdata = 0;
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if (dspi->tx) {
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if (dspi->bytes_per_word == 1)
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txdata = *(u8 *)dspi->tx;
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else /* dspi->bytes_per_word == 2 */
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txdata = *(u16 *)dspi->tx;
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dspi->tx += dspi->bytes_per_word;
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}
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dspi->len -= dspi->bytes_per_word;
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return txdata;
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}
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2016-11-22 07:01:31 +00:00
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2018-06-20 07:34:35 +00:00
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static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi)
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2013-08-16 03:08:55 +00:00
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{
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2018-06-20 07:34:35 +00:00
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u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi);
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2013-08-16 03:08:55 +00:00
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2018-06-20 07:34:35 +00:00
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if (dspi->len > 0)
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cmd |= SPI_PUSHR_CMD_CONT;
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return cmd << 16 | data;
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}
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static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata)
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{
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if (!dspi->rx)
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return;
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/* Mask of undefined bits */
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rxdata &= (1 << dspi->bits_per_word) - 1;
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2013-08-16 03:08:55 +00:00
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2018-06-20 07:34:35 +00:00
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if (dspi->bytes_per_word == 1)
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*(u8 *)dspi->rx = rxdata;
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else /* dspi->bytes_per_word == 2 */
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*(u16 *)dspi->rx = rxdata;
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dspi->rx += dspi->bytes_per_word;
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2013-08-16 03:08:55 +00:00
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}
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2016-11-10 12:19:15 +00:00
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static void dspi_tx_dma_callback(void *arg)
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{
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struct fsl_dspi *dspi = arg;
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struct fsl_dspi_dma *dma = dspi->dma;
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complete(&dma->cmd_tx_complete);
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}
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static void dspi_rx_dma_callback(void *arg)
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{
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struct fsl_dspi *dspi = arg;
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struct fsl_dspi_dma *dma = dspi->dma;
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2016-11-22 07:01:30 +00:00
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int i;
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2016-11-10 12:19:15 +00:00
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2018-06-20 07:34:32 +00:00
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if (dspi->rx) {
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2018-06-20 07:34:35 +00:00
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for (i = 0; i < dma->curr_xfer_len; i++)
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dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]);
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2016-11-10 12:19:15 +00:00
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}
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complete(&dma->cmd_rx_complete);
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}
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static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
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{
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struct fsl_dspi_dma *dma = dspi->dma;
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struct device *dev = &dspi->pdev->dev;
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int time_left;
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2016-11-22 07:01:30 +00:00
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int i;
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2016-11-10 12:19:15 +00:00
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2018-06-20 07:34:35 +00:00
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for (i = 0; i < dma->curr_xfer_len; i++)
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dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi);
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2016-11-10 12:19:15 +00:00
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dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
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dma->tx_dma_phys,
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2016-11-22 07:01:30 +00:00
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dma->curr_xfer_len *
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DMA_SLAVE_BUSWIDTH_4_BYTES,
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DMA_MEM_TO_DEV,
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2016-11-10 12:19:15 +00:00
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!dma->tx_desc) {
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dev_err(dev, "Not able to get desc for DMA xfer\n");
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return -EIO;
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}
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|
dma->tx_desc->callback = dspi_tx_dma_callback;
|
|
|
|
dma->tx_desc->callback_param = dspi;
|
|
|
|
if (dma_submit_error(dmaengine_submit(dma->tx_desc))) {
|
|
|
|
dev_err(dev, "DMA submit failed\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx,
|
|
|
|
dma->rx_dma_phys,
|
2016-11-22 07:01:30 +00:00
|
|
|
dma->curr_xfer_len *
|
|
|
|
DMA_SLAVE_BUSWIDTH_4_BYTES,
|
|
|
|
DMA_DEV_TO_MEM,
|
2016-11-10 12:19:15 +00:00
|
|
|
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
|
|
|
if (!dma->rx_desc) {
|
|
|
|
dev_err(dev, "Not able to get desc for DMA xfer\n");
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
dma->rx_desc->callback = dspi_rx_dma_callback;
|
|
|
|
dma->rx_desc->callback_param = dspi;
|
|
|
|
if (dma_submit_error(dmaengine_submit(dma->rx_desc))) {
|
|
|
|
dev_err(dev, "DMA submit failed\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
reinit_completion(&dspi->dma->cmd_rx_complete);
|
|
|
|
reinit_completion(&dspi->dma->cmd_tx_complete);
|
|
|
|
|
|
|
|
dma_async_issue_pending(dma->chan_rx);
|
|
|
|
dma_async_issue_pending(dma->chan_tx);
|
|
|
|
|
|
|
|
time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
|
|
|
|
DMA_COMPLETION_TIMEOUT);
|
|
|
|
if (time_left == 0) {
|
|
|
|
dev_err(dev, "DMA tx timeout\n");
|
|
|
|
dmaengine_terminate_all(dma->chan_tx);
|
|
|
|
dmaengine_terminate_all(dma->chan_rx);
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
|
|
|
|
DMA_COMPLETION_TIMEOUT);
|
|
|
|
if (time_left == 0) {
|
|
|
|
dev_err(dev, "DMA rx timeout\n");
|
|
|
|
dmaengine_terminate_all(dma->chan_tx);
|
|
|
|
dmaengine_terminate_all(dma->chan_rx);
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dspi_dma_xfer(struct fsl_dspi *dspi)
|
|
|
|
{
|
|
|
|
struct fsl_dspi_dma *dma = dspi->dma;
|
|
|
|
struct device *dev = &dspi->pdev->dev;
|
|
|
|
int curr_remaining_bytes;
|
|
|
|
int bytes_per_buffer;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
curr_remaining_bytes = dspi->len;
|
2016-11-22 07:01:30 +00:00
|
|
|
bytes_per_buffer = DSPI_DMA_BUFSIZE / DSPI_FIFO_SIZE;
|
2016-11-10 12:19:15 +00:00
|
|
|
while (curr_remaining_bytes) {
|
|
|
|
/* Check if current transfer fits the DMA buffer */
|
2018-06-20 07:34:35 +00:00
|
|
|
dma->curr_xfer_len = curr_remaining_bytes
|
|
|
|
/ dspi->bytes_per_word;
|
2016-11-22 07:01:30 +00:00
|
|
|
if (dma->curr_xfer_len > bytes_per_buffer)
|
2016-11-10 12:19:15 +00:00
|
|
|
dma->curr_xfer_len = bytes_per_buffer;
|
|
|
|
|
|
|
|
ret = dspi_next_xfer_dma_submit(dspi);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "DMA transfer failed\n");
|
|
|
|
goto exit;
|
|
|
|
|
|
|
|
} else {
|
2018-06-20 07:34:35 +00:00
|
|
|
curr_remaining_bytes -= dma->curr_xfer_len
|
|
|
|
* dspi->bytes_per_word;
|
2016-11-10 12:19:15 +00:00
|
|
|
if (curr_remaining_bytes < 0)
|
|
|
|
curr_remaining_bytes = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
exit:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
|
|
|
|
{
|
|
|
|
struct fsl_dspi_dma *dma;
|
|
|
|
struct dma_slave_config cfg;
|
|
|
|
struct device *dev = &dspi->pdev->dev;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
|
|
|
|
if (!dma)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
dma->chan_rx = dma_request_slave_channel(dev, "rx");
|
|
|
|
if (!dma->chan_rx) {
|
|
|
|
dev_err(dev, "rx dma channel not available\n");
|
|
|
|
ret = -ENODEV;
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
dma->chan_tx = dma_request_slave_channel(dev, "tx");
|
|
|
|
if (!dma->chan_tx) {
|
|
|
|
dev_err(dev, "tx dma channel not available\n");
|
|
|
|
ret = -ENODEV;
|
|
|
|
goto err_tx_channel;
|
|
|
|
}
|
|
|
|
|
|
|
|
dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
|
|
|
|
&dma->tx_dma_phys, GFP_KERNEL);
|
|
|
|
if (!dma->tx_dma_buf) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err_tx_dma_buf;
|
|
|
|
}
|
|
|
|
|
|
|
|
dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
|
|
|
|
&dma->rx_dma_phys, GFP_KERNEL);
|
|
|
|
if (!dma->rx_dma_buf) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err_rx_dma_buf;
|
|
|
|
}
|
|
|
|
|
|
|
|
cfg.src_addr = phy_addr + SPI_POPR;
|
|
|
|
cfg.dst_addr = phy_addr + SPI_PUSHR;
|
|
|
|
cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
|
|
cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
|
|
cfg.src_maxburst = 1;
|
|
|
|
cfg.dst_maxburst = 1;
|
|
|
|
|
|
|
|
cfg.direction = DMA_DEV_TO_MEM;
|
|
|
|
ret = dmaengine_slave_config(dma->chan_rx, &cfg);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "can't configure rx dma channel\n");
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto err_slave_config;
|
|
|
|
}
|
|
|
|
|
|
|
|
cfg.direction = DMA_MEM_TO_DEV;
|
|
|
|
ret = dmaengine_slave_config(dma->chan_tx, &cfg);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "can't configure tx dma channel\n");
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto err_slave_config;
|
|
|
|
}
|
|
|
|
|
|
|
|
dspi->dma = dma;
|
|
|
|
init_completion(&dma->cmd_tx_complete);
|
|
|
|
init_completion(&dma->cmd_rx_complete);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_slave_config:
|
2016-11-22 07:01:32 +00:00
|
|
|
dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
|
|
|
|
dma->rx_dma_buf, dma->rx_dma_phys);
|
2016-11-10 12:19:15 +00:00
|
|
|
err_rx_dma_buf:
|
2016-11-22 07:01:32 +00:00
|
|
|
dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
|
|
|
|
dma->tx_dma_buf, dma->tx_dma_phys);
|
2016-11-10 12:19:15 +00:00
|
|
|
err_tx_dma_buf:
|
|
|
|
dma_release_channel(dma->chan_tx);
|
|
|
|
err_tx_channel:
|
|
|
|
dma_release_channel(dma->chan_rx);
|
|
|
|
|
|
|
|
devm_kfree(dev, dma);
|
|
|
|
dspi->dma = NULL;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dspi_release_dma(struct fsl_dspi *dspi)
|
|
|
|
{
|
|
|
|
struct fsl_dspi_dma *dma = dspi->dma;
|
|
|
|
struct device *dev = &dspi->pdev->dev;
|
|
|
|
|
|
|
|
if (dma) {
|
|
|
|
if (dma->chan_tx) {
|
|
|
|
dma_unmap_single(dev, dma->tx_dma_phys,
|
|
|
|
DSPI_DMA_BUFSIZE, DMA_TO_DEVICE);
|
|
|
|
dma_release_channel(dma->chan_tx);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dma->chan_rx) {
|
|
|
|
dma_unmap_single(dev, dma->rx_dma_phys,
|
|
|
|
DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE);
|
|
|
|
dma_release_channel(dma->chan_rx);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-08-16 03:08:55 +00:00
|
|
|
static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
|
|
|
|
unsigned long clkrate)
|
|
|
|
{
|
|
|
|
/* Valid baud rate pre-scaler values */
|
|
|
|
int pbr_tbl[4] = {2, 3, 5, 7};
|
|
|
|
int brs[16] = { 2, 4, 6, 8,
|
|
|
|
16, 32, 64, 128,
|
|
|
|
256, 512, 1024, 2048,
|
|
|
|
4096, 8192, 16384, 32768 };
|
spi: fsl-dspi: Fix clock rate scale values
Previous algorithm had an outer loop with the values {2,3,5,7} and an
inner loop with {2,4,6,8,16,32,...,32768}, and would pick the first
value over the required scaling value (where the total scale was the two
numbers multiplied).
Since the inner loop went up to 32768 it would always pick a value of 2
for PBR and a much higher than necessary value for BR. The desired
scale factor was being divided by two I believe to compensate for the
much higher scale factors (the divide by two not specified in the
reference manual).
Updated to check all values and find the smallest scale factor possible
without going over the desired clock rate.
Signed-off-by: Aaron Brice <aaron.brice@datasoft.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-30 17:49:15 +00:00
|
|
|
int scale_needed, scale, minscale = INT_MAX;
|
|
|
|
int i, j;
|
|
|
|
|
|
|
|
scale_needed = clkrate / speed_hz;
|
spi: fsl-dspi: Fix clock rate scale values
Previous algorithm had an outer loop with the values {2,3,5,7} and an
inner loop with {2,4,6,8,16,32,...,32768}, and would pick the first
value over the required scaling value (where the total scale was the two
numbers multiplied).
Since the inner loop went up to 32768 it would always pick a value of 2
for PBR and a much higher than necessary value for BR. The desired
scale factor was being divided by two I believe to compensate for the
much higher scale factors (the divide by two not specified in the
reference manual).
Updated to check all values and find the smallest scale factor possible
without going over the desired clock rate.
Signed-off-by: Aaron Brice <aaron.brice@datasoft.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-04-03 20:39:29 +00:00
|
|
|
if (clkrate % speed_hz)
|
|
|
|
scale_needed++;
|
spi: fsl-dspi: Fix clock rate scale values
Previous algorithm had an outer loop with the values {2,3,5,7} and an
inner loop with {2,4,6,8,16,32,...,32768}, and would pick the first
value over the required scaling value (where the total scale was the two
numbers multiplied).
Since the inner loop went up to 32768 it would always pick a value of 2
for PBR and a much higher than necessary value for BR. The desired
scale factor was being divided by two I believe to compensate for the
much higher scale factors (the divide by two not specified in the
reference manual).
Updated to check all values and find the smallest scale factor possible
without going over the desired clock rate.
Signed-off-by: Aaron Brice <aaron.brice@datasoft.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-30 17:49:15 +00:00
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(brs); i++)
|
|
|
|
for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
|
|
|
|
scale = brs[i] * pbr_tbl[j];
|
|
|
|
if (scale >= scale_needed) {
|
|
|
|
if (scale < minscale) {
|
|
|
|
minscale = scale;
|
|
|
|
*br = i;
|
|
|
|
*pbr = j;
|
|
|
|
}
|
|
|
|
break;
|
2013-08-16 03:08:55 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
spi: fsl-dspi: Fix clock rate scale values
Previous algorithm had an outer loop with the values {2,3,5,7} and an
inner loop with {2,4,6,8,16,32,...,32768}, and would pick the first
value over the required scaling value (where the total scale was the two
numbers multiplied).
Since the inner loop went up to 32768 it would always pick a value of 2
for PBR and a much higher than necessary value for BR. The desired
scale factor was being divided by two I believe to compensate for the
much higher scale factors (the divide by two not specified in the
reference manual).
Updated to check all values and find the smallest scale factor possible
without going over the desired clock rate.
Signed-off-by: Aaron Brice <aaron.brice@datasoft.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-03-30 17:49:15 +00:00
|
|
|
if (minscale == INT_MAX) {
|
|
|
|
pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
|
|
|
|
speed_hz, clkrate);
|
|
|
|
*pbr = ARRAY_SIZE(pbr_tbl) - 1;
|
|
|
|
*br = ARRAY_SIZE(brs) - 1;
|
|
|
|
}
|
2013-08-16 03:08:55 +00:00
|
|
|
}
|
|
|
|
|
2015-04-03 20:39:31 +00:00
|
|
|
static void ns_delay_scale(char *psc, char *sc, int delay_ns,
|
|
|
|
unsigned long clkrate)
|
|
|
|
{
|
|
|
|
int pscale_tbl[4] = {1, 3, 5, 7};
|
|
|
|
int scale_needed, scale, minscale = INT_MAX;
|
|
|
|
int i, j;
|
|
|
|
u32 remainder;
|
|
|
|
|
|
|
|
scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
|
|
|
|
&remainder);
|
|
|
|
if (remainder)
|
|
|
|
scale_needed++;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
|
|
|
|
for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
|
|
|
|
scale = pscale_tbl[i] * (2 << j);
|
|
|
|
if (scale >= scale_needed) {
|
|
|
|
if (scale < minscale) {
|
|
|
|
minscale = scale;
|
|
|
|
*psc = i;
|
|
|
|
*sc = j;
|
|
|
|
}
|
|
|
|
break;
|
2013-08-16 03:08:55 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-04-03 20:39:31 +00:00
|
|
|
if (minscale == INT_MAX) {
|
|
|
|
pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
|
|
|
|
delay_ns, clkrate);
|
|
|
|
*psc = ARRAY_SIZE(pscale_tbl) - 1;
|
|
|
|
*sc = SPI_CTAR_SCALE_BITS;
|
|
|
|
}
|
2013-08-16 03:08:55 +00:00
|
|
|
}
|
|
|
|
|
2018-06-20 07:34:35 +00:00
|
|
|
static void fifo_write(struct fsl_dspi *dspi)
|
2013-08-16 03:08:55 +00:00
|
|
|
{
|
2018-06-20 07:34:35 +00:00
|
|
|
regmap_write(dspi->regmap, SPI_PUSHR, dspi_pop_tx_pushr(dspi));
|
2015-06-09 11:45:27 +00:00
|
|
|
}
|
2013-08-16 03:08:55 +00:00
|
|
|
|
2018-06-20 07:34:35 +00:00
|
|
|
static void dspi_tcfq_write(struct fsl_dspi *dspi)
|
2015-06-09 11:45:27 +00:00
|
|
|
{
|
2018-06-20 07:34:35 +00:00
|
|
|
/* Clear transfer count */
|
|
|
|
dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT;
|
|
|
|
/* Write one entry to both TX FIFO and CMD FIFO simultaneously */
|
|
|
|
fifo_write(dspi);
|
2015-06-09 11:45:27 +00:00
|
|
|
}
|
2013-08-16 03:08:55 +00:00
|
|
|
|
2018-06-20 07:34:35 +00:00
|
|
|
static u32 fifo_read(struct fsl_dspi *dspi)
|
2015-06-09 11:45:27 +00:00
|
|
|
{
|
2018-06-20 07:34:35 +00:00
|
|
|
u32 rxdata = 0;
|
2015-06-09 11:45:27 +00:00
|
|
|
|
2018-06-20 07:34:35 +00:00
|
|
|
regmap_read(dspi->regmap, SPI_POPR, &rxdata);
|
|
|
|
return rxdata;
|
2013-08-16 03:08:55 +00:00
|
|
|
}
|
|
|
|
|
2018-06-20 07:34:35 +00:00
|
|
|
static void dspi_tcfq_read(struct fsl_dspi *dspi)
|
2013-08-16 03:08:55 +00:00
|
|
|
{
|
2018-06-20 07:34:35 +00:00
|
|
|
dspi_push_rx(dspi, fifo_read(dspi));
|
2015-06-09 11:45:27 +00:00
|
|
|
}
|
2013-08-16 03:08:55 +00:00
|
|
|
|
2018-06-20 07:34:35 +00:00
|
|
|
static void dspi_eoq_write(struct fsl_dspi *dspi)
|
2015-06-09 11:45:27 +00:00
|
|
|
{
|
2018-06-20 07:34:35 +00:00
|
|
|
int fifo_size = DSPI_FIFO_SIZE;
|
|
|
|
|
|
|
|
/* Fill TX FIFO with as many transfers as possible */
|
|
|
|
while (dspi->len && fifo_size--) {
|
|
|
|
/* Request EOQF for last transfer in FIFO */
|
|
|
|
if (dspi->len == dspi->bytes_per_word || fifo_size == 0)
|
|
|
|
dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ;
|
|
|
|
/* Clear transfer count for first transfer in FIFO */
|
|
|
|
if (fifo_size == (DSPI_FIFO_SIZE - 1))
|
|
|
|
dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT;
|
|
|
|
/* Write combined TX FIFO and CMD FIFO entry */
|
|
|
|
fifo_write(dspi);
|
2013-08-16 03:08:55 +00:00
|
|
|
}
|
2015-06-09 11:45:27 +00:00
|
|
|
}
|
|
|
|
|
2018-06-20 07:34:35 +00:00
|
|
|
static void dspi_eoq_read(struct fsl_dspi *dspi)
|
2015-06-09 11:45:27 +00:00
|
|
|
{
|
2018-06-20 07:34:35 +00:00
|
|
|
int fifo_size = DSPI_FIFO_SIZE;
|
2015-06-09 11:45:27 +00:00
|
|
|
|
2018-06-20 07:34:35 +00:00
|
|
|
/* Read one FIFO entry at and push to rx buffer */
|
|
|
|
while ((dspi->rx < dspi->rx_end) && fifo_size--)
|
|
|
|
dspi_push_rx(dspi, fifo_read(dspi));
|
2013-08-16 03:08:55 +00:00
|
|
|
}
|
|
|
|
|
2015-01-27 10:57:22 +00:00
|
|
|
static int dspi_transfer_one_message(struct spi_master *master,
|
|
|
|
struct spi_message *message)
|
2013-08-16 03:08:55 +00:00
|
|
|
{
|
2015-01-27 10:57:22 +00:00
|
|
|
struct fsl_dspi *dspi = spi_master_get_devdata(master);
|
|
|
|
struct spi_device *spi = message->spi;
|
|
|
|
struct spi_transfer *transfer;
|
|
|
|
int status = 0;
|
2015-06-09 11:45:27 +00:00
|
|
|
enum dspi_trans_mode trans_mode;
|
|
|
|
|
2015-01-27 10:57:22 +00:00
|
|
|
message->actual_length = 0;
|
|
|
|
|
|
|
|
list_for_each_entry(transfer, &message->transfers, transfer_list) {
|
|
|
|
dspi->cur_transfer = transfer;
|
|
|
|
dspi->cur_msg = message;
|
|
|
|
dspi->cur_chip = spi_get_ctldata(spi);
|
2018-06-20 07:34:33 +00:00
|
|
|
/* Prepare command word for CMD FIFO */
|
|
|
|
dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) |
|
|
|
|
SPI_PUSHR_CMD_PCS(spi->chip_select);
|
2016-04-05 12:33:14 +00:00
|
|
|
if (list_is_last(&dspi->cur_transfer->transfer_list,
|
2018-06-20 07:34:33 +00:00
|
|
|
&dspi->cur_msg->transfers)) {
|
|
|
|
/* Leave PCS activated after last transfer when
|
|
|
|
* cs_change is set.
|
|
|
|
*/
|
|
|
|
if (transfer->cs_change)
|
|
|
|
dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
|
|
|
|
} else {
|
|
|
|
/* Keep PCS active between transfers in same message
|
|
|
|
* when cs_change is not set, and de-activate PCS
|
|
|
|
* between transfers in the same message when
|
|
|
|
* cs_change is set.
|
|
|
|
*/
|
|
|
|
if (!transfer->cs_change)
|
|
|
|
dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
|
|
|
|
}
|
|
|
|
|
2015-01-27 10:57:22 +00:00
|
|
|
dspi->void_write_data = dspi->cur_chip->void_write_data;
|
|
|
|
|
2018-06-20 07:34:35 +00:00
|
|
|
dspi->tx = transfer->tx_buf;
|
2015-01-27 10:57:22 +00:00
|
|
|
dspi->rx = transfer->rx_buf;
|
|
|
|
dspi->rx_end = dspi->rx + transfer->len;
|
|
|
|
dspi->len = transfer->len;
|
2018-06-20 07:34:35 +00:00
|
|
|
/* Validated transfer specific frame size (defaults applied) */
|
|
|
|
dspi->bits_per_word = transfer->bits_per_word;
|
|
|
|
if (transfer->bits_per_word <= 8)
|
|
|
|
dspi->bytes_per_word = 1;
|
|
|
|
else
|
|
|
|
dspi->bytes_per_word = 2;
|
2015-01-27 10:57:22 +00:00
|
|
|
|
|
|
|
regmap_update_bits(dspi->regmap, SPI_MCR,
|
2018-06-20 07:34:37 +00:00
|
|
|
SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
|
|
|
|
SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
|
2015-12-10 05:55:30 +00:00
|
|
|
regmap_write(dspi->regmap, SPI_CTAR(0),
|
2018-06-20 07:34:35 +00:00
|
|
|
dspi->cur_chip->ctar_val |
|
|
|
|
SPI_FRAME_BITS(transfer->bits_per_word));
|
2013-08-16 03:08:55 +00:00
|
|
|
|
2015-06-09 11:45:27 +00:00
|
|
|
trans_mode = dspi->devtype_data->trans_mode;
|
|
|
|
switch (trans_mode) {
|
|
|
|
case DSPI_EOQ_MODE:
|
|
|
|
regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
|
2015-06-09 11:45:37 +00:00
|
|
|
dspi_eoq_write(dspi);
|
2015-06-09 11:45:27 +00:00
|
|
|
break;
|
|
|
|
case DSPI_TCFQ_MODE:
|
|
|
|
regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE);
|
2015-06-09 11:45:37 +00:00
|
|
|
dspi_tcfq_write(dspi);
|
2015-06-09 11:45:27 +00:00
|
|
|
break;
|
2016-11-10 12:19:15 +00:00
|
|
|
case DSPI_DMA_MODE:
|
|
|
|
regmap_write(dspi->regmap, SPI_RSER,
|
|
|
|
SPI_RSER_TFFFE | SPI_RSER_TFFFD |
|
|
|
|
SPI_RSER_RFDFE | SPI_RSER_RFDFD);
|
|
|
|
status = dspi_dma_xfer(dspi);
|
2016-11-17 12:16:48 +00:00
|
|
|
break;
|
2015-06-09 11:45:27 +00:00
|
|
|
default:
|
|
|
|
dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
|
|
|
|
trans_mode);
|
|
|
|
status = -EINVAL;
|
|
|
|
goto out;
|
|
|
|
}
|
2014-02-12 07:29:05 +00:00
|
|
|
|
2016-11-17 12:16:48 +00:00
|
|
|
if (trans_mode != DSPI_DMA_MODE) {
|
|
|
|
if (wait_event_interruptible(dspi->waitq,
|
|
|
|
dspi->waitflags))
|
|
|
|
dev_err(&dspi->pdev->dev,
|
|
|
|
"wait transfer complete fail!\n");
|
|
|
|
dspi->waitflags = 0;
|
|
|
|
}
|
2013-08-16 03:08:55 +00:00
|
|
|
|
2015-01-27 10:57:22 +00:00
|
|
|
if (transfer->delay_usecs)
|
|
|
|
udelay(transfer->delay_usecs);
|
2013-08-16 03:08:55 +00:00
|
|
|
}
|
|
|
|
|
2015-06-09 11:45:27 +00:00
|
|
|
out:
|
2015-01-27 10:57:22 +00:00
|
|
|
message->status = status;
|
|
|
|
spi_finalize_current_message(master);
|
|
|
|
|
|
|
|
return status;
|
2013-08-16 03:08:55 +00:00
|
|
|
}
|
|
|
|
|
2015-01-27 10:57:22 +00:00
|
|
|
static int dspi_setup(struct spi_device *spi)
|
2013-08-16 03:08:55 +00:00
|
|
|
{
|
|
|
|
struct chip_data *chip;
|
|
|
|
struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
|
2017-10-27 22:23:01 +00:00
|
|
|
struct fsl_dspi_platform_data *pdata;
|
2015-04-03 20:39:31 +00:00
|
|
|
u32 cs_sck_delay = 0, sck_cs_delay = 0;
|
|
|
|
unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
|
2018-06-20 07:34:35 +00:00
|
|
|
unsigned char pasc = 0, asc = 0;
|
2015-04-03 20:39:31 +00:00
|
|
|
unsigned long clkrate;
|
2013-08-16 03:08:55 +00:00
|
|
|
|
|
|
|
/* Only alloc on first setup */
|
|
|
|
chip = spi_get_ctldata(spi);
|
|
|
|
if (chip == NULL) {
|
2015-01-27 10:57:20 +00:00
|
|
|
chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
|
2013-08-16 03:08:55 +00:00
|
|
|
if (!chip)
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2017-10-27 22:23:01 +00:00
|
|
|
pdata = dev_get_platdata(&dspi->pdev->dev);
|
2015-04-03 20:39:31 +00:00
|
|
|
|
2017-10-27 22:23:01 +00:00
|
|
|
if (!pdata) {
|
|
|
|
of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
|
|
|
|
&cs_sck_delay);
|
|
|
|
|
|
|
|
of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
|
|
|
|
&sck_cs_delay);
|
|
|
|
} else {
|
|
|
|
cs_sck_delay = pdata->cs_sck_delay;
|
|
|
|
sck_cs_delay = pdata->sck_cs_delay;
|
|
|
|
}
|
2015-04-03 20:39:31 +00:00
|
|
|
|
2013-08-16 03:08:55 +00:00
|
|
|
chip->void_write_data = 0;
|
|
|
|
|
2015-04-03 20:39:31 +00:00
|
|
|
clkrate = clk_get_rate(dspi->clk);
|
|
|
|
hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
|
|
|
|
|
|
|
|
/* Set PCS to SCK delay scale values */
|
|
|
|
ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
|
|
|
|
|
|
|
|
/* Set After SCK delay scale values */
|
|
|
|
ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
|
2013-08-16 03:08:55 +00:00
|
|
|
|
2018-06-20 07:34:35 +00:00
|
|
|
chip->ctar_val = SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
|
2013-08-16 03:08:55 +00:00
|
|
|
| SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
|
|
|
|
| SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
|
2015-04-03 20:39:31 +00:00
|
|
|
| SPI_CTAR_PCSSCK(pcssck)
|
|
|
|
| SPI_CTAR_CSSCK(cssck)
|
|
|
|
| SPI_CTAR_PASC(pasc)
|
|
|
|
| SPI_CTAR_ASC(asc)
|
2013-08-16 03:08:55 +00:00
|
|
|
| SPI_CTAR_PBR(pbr)
|
|
|
|
| SPI_CTAR_BR(br);
|
|
|
|
|
|
|
|
spi_set_ctldata(spi, chip);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-01-27 10:57:20 +00:00
|
|
|
static void dspi_cleanup(struct spi_device *spi)
|
|
|
|
{
|
|
|
|
struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
|
|
|
|
|
|
|
|
dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
|
|
|
|
spi->master->bus_num, spi->chip_select);
|
|
|
|
|
|
|
|
kfree(chip);
|
|
|
|
}
|
|
|
|
|
2013-08-16 03:08:55 +00:00
|
|
|
static irqreturn_t dspi_interrupt(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
|
2015-01-27 10:57:22 +00:00
|
|
|
struct spi_message *msg = dspi->cur_msg;
|
2015-06-09 11:45:27 +00:00
|
|
|
enum dspi_trans_mode trans_mode;
|
2015-06-09 11:45:37 +00:00
|
|
|
u32 spi_sr, spi_tcr;
|
2018-06-20 07:34:34 +00:00
|
|
|
u16 spi_tcnt;
|
2015-06-09 11:45:27 +00:00
|
|
|
|
|
|
|
regmap_read(dspi->regmap, SPI_SR, &spi_sr);
|
|
|
|
regmap_write(dspi->regmap, SPI_SR, spi_sr);
|
|
|
|
|
2013-08-16 03:08:55 +00:00
|
|
|
|
2015-06-09 11:45:37 +00:00
|
|
|
if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) {
|
2018-06-20 07:34:34 +00:00
|
|
|
/* Get transfer counter (in number of SPI transfers). It was
|
|
|
|
* reset to 0 when transfer(s) were started.
|
|
|
|
*/
|
2015-06-09 11:45:37 +00:00
|
|
|
regmap_read(dspi->regmap, SPI_TCR, &spi_tcr);
|
|
|
|
spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr);
|
2018-06-20 07:34:34 +00:00
|
|
|
/* Update total number of bytes that were transferred */
|
2018-06-20 07:34:35 +00:00
|
|
|
msg->actual_length += spi_tcnt * dspi->bytes_per_word;
|
2015-06-09 11:45:37 +00:00
|
|
|
|
|
|
|
trans_mode = dspi->devtype_data->trans_mode;
|
2015-06-09 11:45:27 +00:00
|
|
|
switch (trans_mode) {
|
|
|
|
case DSPI_EOQ_MODE:
|
2015-06-09 11:45:37 +00:00
|
|
|
dspi_eoq_read(dspi);
|
2015-06-09 11:45:27 +00:00
|
|
|
break;
|
|
|
|
case DSPI_TCFQ_MODE:
|
2015-06-09 11:45:37 +00:00
|
|
|
dspi_tcfq_read(dspi);
|
2015-06-09 11:45:27 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
|
|
|
|
trans_mode);
|
2015-06-09 11:45:37 +00:00
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!dspi->len) {
|
|
|
|
dspi->waitflags = 1;
|
|
|
|
wake_up_interruptible(&dspi->waitq);
|
|
|
|
} else {
|
|
|
|
switch (trans_mode) {
|
|
|
|
case DSPI_EOQ_MODE:
|
|
|
|
dspi_eoq_write(dspi);
|
|
|
|
break;
|
|
|
|
case DSPI_TCFQ_MODE:
|
|
|
|
dspi_tcfq_write(dspi);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_err(&dspi->pdev->dev,
|
|
|
|
"unsupported trans_mode %u\n",
|
|
|
|
trans_mode);
|
|
|
|
}
|
2015-06-09 11:45:27 +00:00
|
|
|
}
|
|
|
|
}
|
2015-06-09 11:45:37 +00:00
|
|
|
|
2013-08-16 03:08:55 +00:00
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2014-05-07 07:45:41 +00:00
|
|
|
static const struct of_device_id fsl_dspi_dt_ids[] = {
|
2018-01-02 13:28:06 +00:00
|
|
|
{ .compatible = "fsl,vf610-dspi", .data = &vf610_data, },
|
|
|
|
{ .compatible = "fsl,ls1021a-v1.0-dspi", .data = &ls1021a_v1_data, },
|
|
|
|
{ .compatible = "fsl,ls2085a-dspi", .data = &ls2085a_data, },
|
2013-08-16 03:08:55 +00:00
|
|
|
{ /* sentinel */ }
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
|
|
|
|
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
|
|
static int dspi_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
|
|
struct fsl_dspi *dspi = spi_master_get_devdata(master);
|
|
|
|
|
|
|
|
spi_master_suspend(master);
|
|
|
|
clk_disable_unprepare(dspi->clk);
|
|
|
|
|
2015-06-12 16:55:22 +00:00
|
|
|
pinctrl_pm_select_sleep_state(dev);
|
|
|
|
|
2013-08-16 03:08:55 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dspi_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
|
|
struct fsl_dspi *dspi = spi_master_get_devdata(master);
|
2016-08-22 02:05:30 +00:00
|
|
|
int ret;
|
2013-08-16 03:08:55 +00:00
|
|
|
|
2015-06-12 16:55:22 +00:00
|
|
|
pinctrl_pm_select_default_state(dev);
|
|
|
|
|
2016-08-22 02:05:30 +00:00
|
|
|
ret = clk_prepare_enable(dspi->clk);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2013-08-16 03:08:55 +00:00
|
|
|
spi_master_resume(master);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_PM_SLEEP */
|
|
|
|
|
2014-02-26 01:30:14 +00:00
|
|
|
static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
|
2013-08-16 03:08:55 +00:00
|
|
|
|
2018-06-20 07:34:36 +00:00
|
|
|
static const struct regmap_range dspi_volatile_ranges[] = {
|
|
|
|
regmap_reg_range(SPI_MCR, SPI_TCR),
|
|
|
|
regmap_reg_range(SPI_SR, SPI_SR),
|
|
|
|
regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct regmap_access_table dspi_volatile_table = {
|
|
|
|
.yes_ranges = dspi_volatile_ranges,
|
|
|
|
.n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges),
|
|
|
|
};
|
|
|
|
|
2014-10-09 03:27:45 +00:00
|
|
|
static const struct regmap_config dspi_regmap_config = {
|
2014-02-12 07:29:05 +00:00
|
|
|
.reg_bits = 32,
|
|
|
|
.val_bits = 32,
|
|
|
|
.reg_stride = 4,
|
|
|
|
.max_register = 0x88,
|
2018-06-20 07:34:36 +00:00
|
|
|
.volatile_table = &dspi_volatile_table,
|
2013-08-16 03:08:55 +00:00
|
|
|
};
|
|
|
|
|
2016-10-17 10:02:34 +00:00
|
|
|
static void dspi_init(struct fsl_dspi *dspi)
|
|
|
|
{
|
2018-06-20 07:34:37 +00:00
|
|
|
regmap_write(dspi->regmap, SPI_MCR, SPI_MCR_MASTER | SPI_MCR_PCSIS);
|
2016-10-17 10:02:34 +00:00
|
|
|
regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
|
|
|
|
}
|
|
|
|
|
2013-08-16 03:08:55 +00:00
|
|
|
static int dspi_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct device_node *np = pdev->dev.of_node;
|
|
|
|
struct spi_master *master;
|
|
|
|
struct fsl_dspi *dspi;
|
|
|
|
struct resource *res;
|
2014-02-12 07:29:05 +00:00
|
|
|
void __iomem *base;
|
2017-10-27 22:23:01 +00:00
|
|
|
struct fsl_dspi_platform_data *pdata;
|
2013-08-16 03:08:55 +00:00
|
|
|
int ret = 0, cs_num, bus_num;
|
|
|
|
|
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
|
|
|
|
if (!master)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
dspi = spi_master_get_devdata(master);
|
|
|
|
dspi->pdev = pdev;
|
2015-01-27 10:57:22 +00:00
|
|
|
dspi->master = master;
|
|
|
|
|
|
|
|
master->transfer = NULL;
|
|
|
|
master->setup = dspi_setup;
|
|
|
|
master->transfer_one_message = dspi_transfer_one_message;
|
|
|
|
master->dev.of_node = pdev->dev.of_node;
|
2013-08-16 03:08:55 +00:00
|
|
|
|
2015-01-27 10:57:20 +00:00
|
|
|
master->cleanup = dspi_cleanup;
|
2017-11-13 07:47:21 +00:00
|
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
|
2018-06-20 07:34:35 +00:00
|
|
|
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
|
2013-08-16 03:08:55 +00:00
|
|
|
|
2017-10-27 22:23:01 +00:00
|
|
|
pdata = dev_get_platdata(&pdev->dev);
|
|
|
|
if (pdata) {
|
|
|
|
master->num_chipselect = pdata->cs_num;
|
|
|
|
master->bus_num = pdata->bus_num;
|
2013-08-16 03:08:55 +00:00
|
|
|
|
2017-10-27 22:23:01 +00:00
|
|
|
dspi->devtype_data = &coldfire_data;
|
|
|
|
} else {
|
2013-08-16 03:08:55 +00:00
|
|
|
|
2017-10-27 22:23:01 +00:00
|
|
|
ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
|
|
|
|
goto out_master_put;
|
|
|
|
}
|
|
|
|
master->num_chipselect = cs_num;
|
|
|
|
|
|
|
|
ret = of_property_read_u32(np, "bus-num", &bus_num);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&pdev->dev, "can't get bus-num\n");
|
|
|
|
goto out_master_put;
|
|
|
|
}
|
|
|
|
master->bus_num = bus_num;
|
|
|
|
|
|
|
|
dspi->devtype_data = of_device_get_match_data(&pdev->dev);
|
|
|
|
if (!dspi->devtype_data) {
|
|
|
|
dev_err(&pdev->dev, "can't get devtype_data\n");
|
|
|
|
ret = -EFAULT;
|
|
|
|
goto out_master_put;
|
|
|
|
}
|
2015-06-09 11:45:27 +00:00
|
|
|
}
|
|
|
|
|
2013-08-16 03:08:55 +00:00
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
2014-02-12 07:29:05 +00:00
|
|
|
base = devm_ioremap_resource(&pdev->dev, res);
|
|
|
|
if (IS_ERR(base)) {
|
|
|
|
ret = PTR_ERR(base);
|
2013-08-16 03:08:55 +00:00
|
|
|
goto out_master_put;
|
|
|
|
}
|
|
|
|
|
2015-04-24 10:54:47 +00:00
|
|
|
dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
|
2014-02-12 07:29:05 +00:00
|
|
|
&dspi_regmap_config);
|
|
|
|
if (IS_ERR(dspi->regmap)) {
|
|
|
|
dev_err(&pdev->dev, "failed to init regmap: %ld\n",
|
|
|
|
PTR_ERR(dspi->regmap));
|
2017-02-19 13:19:02 +00:00
|
|
|
ret = PTR_ERR(dspi->regmap);
|
|
|
|
goto out_master_put;
|
2014-02-12 07:29:05 +00:00
|
|
|
}
|
|
|
|
|
2016-10-17 10:02:34 +00:00
|
|
|
dspi_init(dspi);
|
2013-08-16 03:08:55 +00:00
|
|
|
dspi->irq = platform_get_irq(pdev, 0);
|
|
|
|
if (dspi->irq < 0) {
|
|
|
|
dev_err(&pdev->dev, "can't get platform irq\n");
|
|
|
|
ret = dspi->irq;
|
|
|
|
goto out_master_put;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
|
|
|
|
pdev->name, dspi);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
|
|
|
|
goto out_master_put;
|
|
|
|
}
|
|
|
|
|
|
|
|
dspi->clk = devm_clk_get(&pdev->dev, "dspi");
|
|
|
|
if (IS_ERR(dspi->clk)) {
|
|
|
|
ret = PTR_ERR(dspi->clk);
|
|
|
|
dev_err(&pdev->dev, "unable to get clock\n");
|
|
|
|
goto out_master_put;
|
|
|
|
}
|
2016-08-22 02:05:30 +00:00
|
|
|
ret = clk_prepare_enable(dspi->clk);
|
|
|
|
if (ret)
|
|
|
|
goto out_master_put;
|
2013-08-16 03:08:55 +00:00
|
|
|
|
2016-11-10 12:19:15 +00:00
|
|
|
if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
|
2017-05-22 13:19:20 +00:00
|
|
|
ret = dspi_request_dma(dspi, res->start);
|
|
|
|
if (ret < 0) {
|
2016-11-10 12:19:15 +00:00
|
|
|
dev_err(&pdev->dev, "can't get dma channels\n");
|
|
|
|
goto out_clk_put;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-03-21 20:11:52 +00:00
|
|
|
master->max_speed_hz =
|
|
|
|
clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
|
|
|
|
|
2013-08-16 03:08:55 +00:00
|
|
|
init_waitqueue_head(&dspi->waitq);
|
2014-02-14 04:49:12 +00:00
|
|
|
platform_set_drvdata(pdev, master);
|
2013-08-16 03:08:55 +00:00
|
|
|
|
2015-01-27 10:57:22 +00:00
|
|
|
ret = spi_register_master(master);
|
2013-08-16 03:08:55 +00:00
|
|
|
if (ret != 0) {
|
|
|
|
dev_err(&pdev->dev, "Problem registering DSPI master\n");
|
|
|
|
goto out_clk_put;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
out_clk_put:
|
|
|
|
clk_disable_unprepare(dspi->clk);
|
|
|
|
out_master_put:
|
|
|
|
spi_master_put(master);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dspi_remove(struct platform_device *pdev)
|
|
|
|
{
|
2014-02-14 04:49:12 +00:00
|
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
|
|
struct fsl_dspi *dspi = spi_master_get_devdata(master);
|
2013-08-16 03:08:55 +00:00
|
|
|
|
|
|
|
/* Disconnect from the SPI framework */
|
2016-11-10 12:19:15 +00:00
|
|
|
dspi_release_dma(dspi);
|
2013-10-12 07:15:31 +00:00
|
|
|
clk_disable_unprepare(dspi->clk);
|
2015-01-27 10:57:22 +00:00
|
|
|
spi_unregister_master(dspi->master);
|
2013-08-16 03:08:55 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver fsl_dspi_driver = {
|
|
|
|
.driver.name = DRIVER_NAME,
|
|
|
|
.driver.of_match_table = fsl_dspi_dt_ids,
|
|
|
|
.driver.owner = THIS_MODULE,
|
|
|
|
.driver.pm = &dspi_pm,
|
|
|
|
.probe = dspi_probe,
|
|
|
|
.remove = dspi_remove,
|
|
|
|
};
|
|
|
|
module_platform_driver(fsl_dspi_driver);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
|
2013-09-10 08:46:33 +00:00
|
|
|
MODULE_LICENSE("GPL");
|
2013-08-16 03:08:55 +00:00
|
|
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|