2019-05-27 06:55:05 +00:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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2005-04-16 22:20:36 +00:00
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/*
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* linux/include/asm-arm/hardware/serial_amba.h
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*
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* Internal header file for AMBA serial ports
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*
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* Copyright (C) ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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*/
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#ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H
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#define ASM_ARM_HARDWARE_SERIAL_AMBA_H
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2012-02-23 03:41:05 +00:00
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#include <linux/types.h>
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2005-04-16 22:20:36 +00:00
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/* -------------------------------------------------------------------------------
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* From AMBA UART (PL010) Block Specification
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* -------------------------------------------------------------------------------
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* UART Register Offsets.
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*/
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#define UART01x_DR 0x00 /* Data read or written from the interface. */
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#define UART01x_RSR 0x04 /* Receive status register (Read). */
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#define UART01x_ECR 0x04 /* Error clear register (Write). */
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#define UART010_LCRH 0x08 /* Line control register, high byte. */
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2010-10-01 08:15:41 +00:00
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#define ST_UART011_DMAWM 0x08 /* DMA watermark configure register. */
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2005-04-16 22:20:36 +00:00
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#define UART010_LCRM 0x0C /* Line control register, middle byte. */
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2010-10-01 08:15:41 +00:00
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#define ST_UART011_TIMEOUT 0x0C /* Timeout period register. */
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2005-04-16 22:20:36 +00:00
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#define UART010_LCRL 0x10 /* Line control register, low byte. */
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#define UART010_CR 0x14 /* Control register. */
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#define UART01x_FR 0x18 /* Flag register (Read only). */
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2013-10-11 23:29:46 +00:00
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#define UART010_IIR 0x1C /* Interrupt identification register (Read). */
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2005-04-16 22:20:36 +00:00
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#define UART010_ICR 0x1C /* Interrupt clear register (Write). */
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2010-06-02 07:13:52 +00:00
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#define ST_UART011_LCRH_RX 0x1C /* Rx line control register. */
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2005-04-16 22:20:36 +00:00
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#define UART01x_ILPR 0x20 /* IrDA low power counter register. */
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#define UART011_IBRD 0x24 /* Integer baud rate divisor register. */
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#define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */
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#define UART011_LCRH 0x2c /* Line control register. */
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2010-06-02 07:13:52 +00:00
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#define ST_UART011_LCRH_TX 0x2c /* Tx Line control register. */
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2005-04-16 22:20:36 +00:00
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#define UART011_CR 0x30 /* Control register. */
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#define UART011_IFLS 0x34 /* Interrupt fifo level select. */
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#define UART011_IMSC 0x38 /* Interrupt mask. */
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#define UART011_RIS 0x3c /* Raw interrupt status. */
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#define UART011_MIS 0x40 /* Masked interrupt status. */
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#define UART011_ICR 0x44 /* Interrupt clear register. */
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#define UART011_DMACR 0x48 /* DMA control register. */
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2010-10-01 08:15:41 +00:00
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#define ST_UART011_XFCR 0x50 /* XON/XOFF control register. */
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#define ST_UART011_XON1 0x54 /* XON1 register. */
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#define ST_UART011_XON2 0x58 /* XON2 register. */
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#define ST_UART011_XOFF1 0x5C /* XON1 register. */
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#define ST_UART011_XOFF2 0x60 /* XON2 register. */
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#define ST_UART011_ITCR 0x80 /* Integration test control register. */
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#define ST_UART011_ITIP 0x84 /* Integration test input register. */
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#define ST_UART011_ABCR 0x100 /* Autobaud control register. */
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#define ST_UART011_ABIMSC 0x15C /* Autobaud interrupt mask/clear register. */
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2005-04-16 22:20:36 +00:00
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2015-11-16 17:40:57 +00:00
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/*
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* ZTE UART register offsets. This UART has a radically different address
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* allocation from the ARM and ST variants, so we list all registers here.
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* We assume unlisted registers do not exist.
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*/
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#define ZX_UART011_DR 0x04
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#define ZX_UART011_FR 0x14
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#define ZX_UART011_IBRD 0x24
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#define ZX_UART011_FBRD 0x28
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#define ZX_UART011_LCRH 0x30
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#define ZX_UART011_CR 0x34
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#define ZX_UART011_IFLS 0x38
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#define ZX_UART011_IMSC 0x40
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#define ZX_UART011_RIS 0x44
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#define ZX_UART011_MIS 0x48
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#define ZX_UART011_ICR 0x4c
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#define ZX_UART011_DMACR 0x50
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2005-11-19 11:10:35 +00:00
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#define UART011_DR_OE (1 << 11)
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#define UART011_DR_BE (1 << 10)
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#define UART011_DR_PE (1 << 9)
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#define UART011_DR_FE (1 << 8)
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2005-04-16 22:20:36 +00:00
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#define UART01x_RSR_OE 0x08
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#define UART01x_RSR_BE 0x04
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#define UART01x_RSR_PE 0x02
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#define UART01x_RSR_FE 0x01
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#define UART011_FR_RI 0x100
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#define UART011_FR_TXFE 0x080
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#define UART011_FR_RXFF 0x040
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#define UART01x_FR_TXFF 0x020
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#define UART01x_FR_RXFE 0x010
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#define UART01x_FR_BUSY 0x008
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#define UART01x_FR_DCD 0x004
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#define UART01x_FR_DSR 0x002
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#define UART01x_FR_CTS 0x001
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#define UART01x_FR_TMSK (UART01x_FR_TXFF + UART01x_FR_BUSY)
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2016-07-08 09:00:39 +00:00
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/*
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* Some bits of Flag Register on ZTE device have different position from
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* standard ones.
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*/
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#define ZX_UART01x_FR_BUSY 0x100
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#define ZX_UART01x_FR_DSR 0x008
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#define ZX_UART01x_FR_CTS 0x002
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#define ZX_UART011_FR_RI 0x001
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2005-04-16 22:20:36 +00:00
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#define UART011_CR_CTSEN 0x8000 /* CTS hardware flow control */
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#define UART011_CR_RTSEN 0x4000 /* RTS hardware flow control */
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#define UART011_CR_OUT2 0x2000 /* OUT2 */
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#define UART011_CR_OUT1 0x1000 /* OUT1 */
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#define UART011_CR_RTS 0x0800 /* RTS */
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#define UART011_CR_DTR 0x0400 /* DTR */
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#define UART011_CR_RXE 0x0200 /* receive enable */
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#define UART011_CR_TXE 0x0100 /* transmit enable */
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#define UART011_CR_LBE 0x0080 /* loopback enable */
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#define UART010_CR_RTIE 0x0040
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#define UART010_CR_TIE 0x0020
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#define UART010_CR_RIE 0x0010
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#define UART010_CR_MSIE 0x0008
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2010-06-02 19:40:22 +00:00
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#define ST_UART011_CR_OVSFACT 0x0008 /* Oversampling factor */
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2005-04-16 22:20:36 +00:00
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#define UART01x_CR_IIRLP 0x0004 /* SIR low power mode */
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#define UART01x_CR_SIREN 0x0002 /* SIR enable */
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#define UART01x_CR_UARTEN 0x0001 /* UART enable */
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#define UART011_LCRH_SPS 0x80
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#define UART01x_LCRH_WLEN_8 0x60
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#define UART01x_LCRH_WLEN_7 0x40
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#define UART01x_LCRH_WLEN_6 0x20
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#define UART01x_LCRH_WLEN_5 0x00
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#define UART01x_LCRH_FEN 0x10
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#define UART01x_LCRH_STP2 0x08
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#define UART01x_LCRH_EPS 0x04
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#define UART01x_LCRH_PEN 0x02
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#define UART01x_LCRH_BRK 0x01
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2010-12-22 17:59:16 +00:00
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#define ST_UART011_DMAWM_RX_1 (0 << 3)
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#define ST_UART011_DMAWM_RX_2 (1 << 3)
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#define ST_UART011_DMAWM_RX_4 (2 << 3)
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#define ST_UART011_DMAWM_RX_8 (3 << 3)
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#define ST_UART011_DMAWM_RX_16 (4 << 3)
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#define ST_UART011_DMAWM_RX_32 (5 << 3)
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#define ST_UART011_DMAWM_RX_48 (6 << 3)
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#define ST_UART011_DMAWM_TX_1 0
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#define ST_UART011_DMAWM_TX_2 1
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#define ST_UART011_DMAWM_TX_4 2
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#define ST_UART011_DMAWM_TX_8 3
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#define ST_UART011_DMAWM_TX_16 4
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#define ST_UART011_DMAWM_TX_32 5
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#define ST_UART011_DMAWM_TX_48 6
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2005-04-16 22:20:36 +00:00
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#define UART010_IIR_RTIS 0x08
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#define UART010_IIR_TIS 0x04
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#define UART010_IIR_RIS 0x02
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#define UART010_IIR_MIS 0x01
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#define UART011_IFLS_RX1_8 (0 << 3)
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#define UART011_IFLS_RX2_8 (1 << 3)
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#define UART011_IFLS_RX4_8 (2 << 3)
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#define UART011_IFLS_RX6_8 (3 << 3)
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#define UART011_IFLS_RX7_8 (4 << 3)
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#define UART011_IFLS_TX1_8 (0 << 0)
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#define UART011_IFLS_TX2_8 (1 << 0)
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#define UART011_IFLS_TX4_8 (2 << 0)
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#define UART011_IFLS_TX6_8 (3 << 0)
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#define UART011_IFLS_TX7_8 (4 << 0)
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2009-06-04 16:43:04 +00:00
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/* special values for ST vendor with deeper fifo */
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#define UART011_IFLS_RX_HALF (5 << 3)
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#define UART011_IFLS_TX_HALF (5 << 0)
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2005-04-16 22:20:36 +00:00
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#define UART011_OEIM (1 << 10) /* overrun error interrupt mask */
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#define UART011_BEIM (1 << 9) /* break error interrupt mask */
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#define UART011_PEIM (1 << 8) /* parity error interrupt mask */
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#define UART011_FEIM (1 << 7) /* framing error interrupt mask */
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#define UART011_RTIM (1 << 6) /* receive timeout interrupt mask */
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#define UART011_TXIM (1 << 5) /* transmit interrupt mask */
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#define UART011_RXIM (1 << 4) /* receive interrupt mask */
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#define UART011_DSRMIM (1 << 3) /* DSR interrupt mask */
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#define UART011_DCDMIM (1 << 2) /* DCD interrupt mask */
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#define UART011_CTSMIM (1 << 1) /* CTS interrupt mask */
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#define UART011_RIMIM (1 << 0) /* RI interrupt mask */
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#define UART011_OEIS (1 << 10) /* overrun error interrupt status */
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#define UART011_BEIS (1 << 9) /* break error interrupt status */
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#define UART011_PEIS (1 << 8) /* parity error interrupt status */
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#define UART011_FEIS (1 << 7) /* framing error interrupt status */
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#define UART011_RTIS (1 << 6) /* receive timeout interrupt status */
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#define UART011_TXIS (1 << 5) /* transmit interrupt status */
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#define UART011_RXIS (1 << 4) /* receive interrupt status */
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#define UART011_DSRMIS (1 << 3) /* DSR interrupt status */
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#define UART011_DCDMIS (1 << 2) /* DCD interrupt status */
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#define UART011_CTSMIS (1 << 1) /* CTS interrupt status */
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#define UART011_RIMIS (1 << 0) /* RI interrupt status */
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#define UART011_OEIC (1 << 10) /* overrun error interrupt clear */
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#define UART011_BEIC (1 << 9) /* break error interrupt clear */
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#define UART011_PEIC (1 << 8) /* parity error interrupt clear */
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#define UART011_FEIC (1 << 7) /* framing error interrupt clear */
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#define UART011_RTIC (1 << 6) /* receive timeout interrupt clear */
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#define UART011_TXIC (1 << 5) /* transmit interrupt clear */
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#define UART011_RXIC (1 << 4) /* receive interrupt clear */
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#define UART011_DSRMIC (1 << 3) /* DSR interrupt clear */
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#define UART011_DCDMIC (1 << 2) /* DCD interrupt clear */
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#define UART011_CTSMIC (1 << 1) /* CTS interrupt clear */
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#define UART011_RIMIC (1 << 0) /* RI interrupt clear */
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#define UART011_DMAONERR (1 << 2) /* disable dma on error */
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#define UART011_TXDMAE (1 << 1) /* enable transmit dma */
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#define UART011_RXDMAE (1 << 0) /* enable receive dma */
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#define UART01x_RSR_ANY (UART01x_RSR_OE|UART01x_RSR_BE|UART01x_RSR_PE|UART01x_RSR_FE)
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#define UART01x_FR_MODEM_ANY (UART01x_FR_DCD|UART01x_FR_DSR|UART01x_FR_CTS)
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2006-03-26 22:13:39 +00:00
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#ifndef __ASSEMBLY__
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2009-06-06 09:17:57 +00:00
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struct amba_device; /* in uncompress this is included but amba/bus.h is not */
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2006-03-26 22:13:39 +00:00
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struct amba_pl010_data {
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void (*set_mctrl)(struct amba_device *dev, void __iomem *base, unsigned int mctrl);
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};
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ARM: PL011: Add support for transmit DMA
Add DMA engine support for transmit to the PL011 driver. Based on a
patch from Linus Walliej, with the following changes:
- remove RX DMA support. As PL011 doesn't give us receive timeout
interrupts, we only get notified of received data when the RX DMA
has completed. This rather sucks for interactive use of the TTY.
- remove abuse of completions. Completions are supposed to be for
events, not to tell what condition buffers are in. Replace it with
a simple 'queued' bool.
- fix locking - it is only safe to access the circular buffer with the
port lock held.
- only map the DMA buffer when required - if we're ever behind an IOMMU
this helps keep IOMMU usage down, and also ensures that we're legal
when we change the scatterlist entry length.
- fix XON/XOFF sending - we must send XON/XOFF characters out as soon
as possible - waiting for up to 4095 characters in the DMA buffer
to be sent first is not acceptable.
- fix XON/XOFF receive handling - we need to stop DMA when instructed
to by the TTY layer, and restart it again when instructed to. There
is a subtle problem here: we must not completely empty the circular
buffer with DMA, otherwise we will not be notified of XON.
- change the 'enable_dma' flag into a 'using DMA' flag, and track
whether we can use TX DMA by whether the channel pointer is non-NULL.
This gives us more control over whether we use DMA in the driver.
- we don't need to have the TX DMA buffer continually allocated for
each port - instead, allocate it when the port starts up, and free
it when it's shut down. Update the 'using DMA' flag if we get
the buffer, and adjust the TTY FIFO size appropriately.
- if we're going to use PIO to send characters, use the existing IRQ
based functionality rather than reimplementing it. This also ensures
we call uart_write_wakeup() at the appropriate time, otherwise we'll
stall.
- use DMA engine helper functions for type safety.
- fix init when built as a module - we can't have to initcall functions,
so we must settle on one. This means we can eliminate the deferred
DMA initialization.
- there is no need to terminate transfers on a failed prep_slave_sg()
call - nothing has been setup, so nothing needs to be terminated.
This avoids a potential deadlock in the DMA engine code
(tasklet->callback->failed prepare->terminate->tasklet_disable
which then ends up waiting for the tasklet to finish running.)
- Dan says that the submission callback should not return an error:
| dma_submit_error() is something I should have removed after commit
| a0587bcf "ioat1: move descriptor allocation from submit to prep" all
| errors should be notified by prep failing to return a descriptor
| handle. Negative dma_cookie_t values are only returned by the
| dma_async_memcpy* calls which translate a prep failure into -ENOMEM.
So remove the error handling at that point. This also solves the
potential deadlock mentioned in the previous comment.
Acked-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-22 17:24:39 +00:00
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struct dma_chan;
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struct amba_pl011_data {
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bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
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void *dma_rx_param;
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void *dma_tx_param;
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2013-03-27 09:38:11 +00:00
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bool dma_rx_poll_enable;
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unsigned int dma_rx_poll_rate;
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unsigned int dma_rx_poll_timeout;
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2011-06-13 08:11:33 +00:00
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void (*init) (void);
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void (*exit) (void);
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ARM: PL011: Add support for transmit DMA
Add DMA engine support for transmit to the PL011 driver. Based on a
patch from Linus Walliej, with the following changes:
- remove RX DMA support. As PL011 doesn't give us receive timeout
interrupts, we only get notified of received data when the RX DMA
has completed. This rather sucks for interactive use of the TTY.
- remove abuse of completions. Completions are supposed to be for
events, not to tell what condition buffers are in. Replace it with
a simple 'queued' bool.
- fix locking - it is only safe to access the circular buffer with the
port lock held.
- only map the DMA buffer when required - if we're ever behind an IOMMU
this helps keep IOMMU usage down, and also ensures that we're legal
when we change the scatterlist entry length.
- fix XON/XOFF sending - we must send XON/XOFF characters out as soon
as possible - waiting for up to 4095 characters in the DMA buffer
to be sent first is not acceptable.
- fix XON/XOFF receive handling - we need to stop DMA when instructed
to by the TTY layer, and restart it again when instructed to. There
is a subtle problem here: we must not completely empty the circular
buffer with DMA, otherwise we will not be notified of XON.
- change the 'enable_dma' flag into a 'using DMA' flag, and track
whether we can use TX DMA by whether the channel pointer is non-NULL.
This gives us more control over whether we use DMA in the driver.
- we don't need to have the TX DMA buffer continually allocated for
each port - instead, allocate it when the port starts up, and free
it when it's shut down. Update the 'using DMA' flag if we get
the buffer, and adjust the TTY FIFO size appropriately.
- if we're going to use PIO to send characters, use the existing IRQ
based functionality rather than reimplementing it. This also ensures
we call uart_write_wakeup() at the appropriate time, otherwise we'll
stall.
- use DMA engine helper functions for type safety.
- fix init when built as a module - we can't have to initcall functions,
so we must settle on one. This means we can eliminate the deferred
DMA initialization.
- there is no need to terminate transfers on a failed prep_slave_sg()
call - nothing has been setup, so nothing needs to be terminated.
This avoids a potential deadlock in the DMA engine code
(tasklet->callback->failed prepare->terminate->tasklet_disable
which then ends up waiting for the tasklet to finish running.)
- Dan says that the submission callback should not return an error:
| dma_submit_error() is something I should have removed after commit
| a0587bcf "ioat1: move descriptor allocation from submit to prep" all
| errors should be notified by prep failing to return a descriptor
| handle. Negative dma_cookie_t values are only returned by the
| dma_async_memcpy* calls which translate a prep failure into -ENOMEM.
So remove the error handling at that point. This also solves the
potential deadlock mentioned in the previous comment.
Acked-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-22 17:24:39 +00:00
|
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};
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2006-03-26 22:13:39 +00:00
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#endif
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2005-04-16 22:20:36 +00:00
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#endif
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