2020-09-07 13:15:20 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* AMD Encrypted Register State Support
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*
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* Author: Joerg Roedel <jroedel@suse.de>
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*/
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#ifndef __ASM_ENCRYPTED_STATE_H
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#define __ASM_ENCRYPTED_STATE_H
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#include <linux/types.h>
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2020-09-07 13:15:24 +00:00
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#include <asm/insn.h>
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2021-04-27 11:16:35 +00:00
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#include <asm/sev-common.h>
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2020-09-07 13:15:20 +00:00
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2022-02-09 18:10:05 +00:00
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#define GHCB_PROTOCOL_MIN 1ULL
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2022-02-09 18:10:06 +00:00
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#define GHCB_PROTOCOL_MAX 2ULL
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2021-04-27 11:16:35 +00:00
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#define GHCB_DEFAULT_USAGE 0ULL
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2020-09-07 13:15:20 +00:00
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#define VMGEXIT() { asm volatile("rep; vmmcall\n\r"); }
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2020-09-07 13:15:24 +00:00
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enum es_result {
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ES_OK, /* All good */
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ES_UNSUPPORTED, /* Requested operation not supported */
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ES_VMM_ERROR, /* Unexpected state from the VMM */
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ES_DECODE_FAILED, /* Instruction decoding failed */
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ES_EXCEPTION, /* Instruction caused exception */
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ES_RETRY, /* Retry instruction emulation */
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};
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struct es_fault_info {
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unsigned long vector;
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unsigned long error_code;
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unsigned long cr2;
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};
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struct pt_regs;
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/* ES instruction emulation context */
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struct es_em_ctxt {
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struct pt_regs *regs;
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struct insn insn;
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struct es_fault_info fi;
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};
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2020-09-07 13:15:20 +00:00
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void do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code);
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static inline u64 lower_bits(u64 val, unsigned int bits)
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{
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u64 mask = (1ULL << bits) - 1;
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return (val & mask);
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}
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2020-09-07 13:16:07 +00:00
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struct real_mode_header;
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enum stack_type;
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2021-10-25 12:21:10 +00:00
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struct ghcb;
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2020-09-07 13:16:07 +00:00
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2020-09-08 12:35:17 +00:00
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/* Early IDT entry points for #VC handler */
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extern void vc_no_ghcb(void);
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2020-09-08 12:38:16 +00:00
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extern void vc_boot_ghcb(void);
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extern bool handle_vc_boot_ghcb(struct pt_regs *regs);
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2020-09-08 12:35:17 +00:00
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2022-02-09 18:10:07 +00:00
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/* Software defined (when rFlags.CF = 1) */
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#define PVALIDATE_FAIL_NOUPDATE 255
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2022-02-09 18:10:08 +00:00
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/* RMP page size */
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#define RMP_PG_SIZE_4K 0
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2022-03-07 21:33:32 +00:00
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#define RMPADJUST_VMSA_PAGE_BIT BIT(16)
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2020-09-07 13:15:44 +00:00
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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extern struct static_key_false sev_es_enable_key;
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extern void __sev_es_ist_enter(struct pt_regs *regs);
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extern void __sev_es_ist_exit(void);
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static __always_inline void sev_es_ist_enter(struct pt_regs *regs)
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{
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if (static_branch_unlikely(&sev_es_enable_key))
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__sev_es_ist_enter(regs);
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}
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static __always_inline void sev_es_ist_exit(void)
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{
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if (static_branch_unlikely(&sev_es_enable_key))
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__sev_es_ist_exit();
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}
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2020-09-07 13:16:07 +00:00
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extern int sev_es_setup_ap_jump_table(struct real_mode_header *rmh);
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2020-09-07 13:16:11 +00:00
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extern void __sev_es_nmi_complete(void);
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static __always_inline void sev_es_nmi_complete(void)
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{
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if (static_branch_unlikely(&sev_es_enable_key))
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__sev_es_nmi_complete();
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}
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2020-09-07 13:16:12 +00:00
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extern int __init sev_es_efi_map_ghcbs(pgd_t *pgd);
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2021-10-25 12:21:10 +00:00
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extern enum es_result sev_es_ghcb_hv_call(struct ghcb *ghcb,
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bool set_ghcb_msr,
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struct es_em_ctxt *ctxt,
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u64 exit_code, u64 exit_info_1,
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u64 exit_info_2);
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2022-02-09 18:10:08 +00:00
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static inline int rmpadjust(unsigned long vaddr, bool rmp_psize, unsigned long attrs)
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{
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int rc;
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/* "rmpadjust" mnemonic support in binutils 2.36 and newer */
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asm volatile(".byte 0xF3,0x0F,0x01,0xFE\n\t"
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: "=a"(rc)
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: "a"(vaddr), "c"(rmp_psize), "d"(attrs)
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: "memory", "cc");
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return rc;
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}
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2022-02-09 18:10:07 +00:00
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static inline int pvalidate(unsigned long vaddr, bool rmp_psize, bool validate)
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{
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bool no_rmpupdate;
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int rc;
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/* "pvalidate" mnemonic support in binutils 2.36 and newer */
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asm volatile(".byte 0xF2, 0x0F, 0x01, 0xFF\n\t"
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CC_SET(c)
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: CC_OUT(c) (no_rmpupdate), "=a"(rc)
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: "a"(vaddr), "c"(rmp_psize), "d"(validate)
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: "memory", "cc");
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if (no_rmpupdate)
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return PVALIDATE_FAIL_NOUPDATE;
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return rc;
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}
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2022-02-09 18:10:11 +00:00
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void setup_ghcb(void);
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2022-02-09 18:10:12 +00:00
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void __init early_snp_set_memory_private(unsigned long vaddr, unsigned long paddr,
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unsigned int npages);
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void __init early_snp_set_memory_shared(unsigned long vaddr, unsigned long paddr,
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unsigned int npages);
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void __init snp_prep_memory(unsigned long paddr, unsigned int sz, enum psc_op op);
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2022-02-24 16:56:01 +00:00
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void snp_set_memory_shared(unsigned long vaddr, unsigned int npages);
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void snp_set_memory_private(unsigned long vaddr, unsigned int npages);
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2022-03-07 21:33:32 +00:00
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void snp_set_wakeup_secondary_cpu(void);
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2020-09-07 13:15:44 +00:00
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#else
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static inline void sev_es_ist_enter(struct pt_regs *regs) { }
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static inline void sev_es_ist_exit(void) { }
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2020-09-07 13:16:07 +00:00
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static inline int sev_es_setup_ap_jump_table(struct real_mode_header *rmh) { return 0; }
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2020-09-07 13:16:11 +00:00
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static inline void sev_es_nmi_complete(void) { }
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2020-09-07 13:16:12 +00:00
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static inline int sev_es_efi_map_ghcbs(pgd_t *pgd) { return 0; }
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2022-02-09 18:10:07 +00:00
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static inline int pvalidate(unsigned long vaddr, bool rmp_psize, bool validate) { return 0; }
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2022-02-09 18:10:08 +00:00
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static inline int rmpadjust(unsigned long vaddr, bool rmp_psize, unsigned long attrs) { return 0; }
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2022-02-09 18:10:11 +00:00
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static inline void setup_ghcb(void) { }
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2022-02-09 18:10:12 +00:00
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static inline void __init
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early_snp_set_memory_private(unsigned long vaddr, unsigned long paddr, unsigned int npages) { }
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static inline void __init
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early_snp_set_memory_shared(unsigned long vaddr, unsigned long paddr, unsigned int npages) { }
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static inline void __init snp_prep_memory(unsigned long paddr, unsigned int sz, enum psc_op op) { }
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2022-02-24 16:56:01 +00:00
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static inline void snp_set_memory_shared(unsigned long vaddr, unsigned int npages) { }
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static inline void snp_set_memory_private(unsigned long vaddr, unsigned int npages) { }
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2022-03-07 21:33:32 +00:00
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static inline void snp_set_wakeup_secondary_cpu(void) { }
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2020-09-07 13:15:44 +00:00
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#endif
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2020-09-07 13:15:20 +00:00
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#endif
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