2018-02-02 02:16:11 +00:00
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// SPDX-License-Identifier: GPL-2.0
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2018-02-26 15:48:14 +00:00
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/*
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* Copyright (c) 2015-2018, Intel Corporation.
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*/
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2018-02-02 02:16:11 +00:00
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#define pr_fmt(fmt) "aspeed-kcs-bmc: " fmt
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#include <linux/atomic.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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2021-06-08 10:47:55 +00:00
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#include <linux/irq.h>
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2018-02-02 02:16:11 +00:00
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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2019-12-16 02:27:42 +00:00
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#include <linux/of_address.h>
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2021-06-08 10:47:42 +00:00
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#include <linux/of_device.h>
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2018-02-02 02:16:11 +00:00
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#include <linux/platform_device.h>
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#include <linux/poll.h>
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#include <linux/regmap.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/timer.h>
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2021-06-08 10:47:47 +00:00
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#include "kcs_bmc_device.h"
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2018-02-02 02:16:11 +00:00
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#define DEVICE_NAME "ast-kcs-bmc"
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#define KCS_CHANNEL_MAX 4
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2021-06-08 10:47:55 +00:00
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/*
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* Field class descriptions
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*
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* LPCyE Enable LPC channel y
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* IBFIEy Input Buffer Full IRQ Enable for LPC channel y
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* IRQxEy Assert SerIRQ x for LPC channel y (Deprecated, use IDyIRQX, IRQXEy)
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* IDyIRQX Use the specified 4-bit SerIRQ for LPC channel y
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* SELyIRQX SerIRQ polarity for LPC channel y (low: 0, high: 1)
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* IRQXEy Assert the SerIRQ specified in IDyIRQX for LPC channel y
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*/
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#define LPC_TYIRQX_LOW 0b00
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#define LPC_TYIRQX_HIGH 0b01
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#define LPC_TYIRQX_RSVD 0b10
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#define LPC_TYIRQX_RISING 0b11
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2018-02-02 02:16:11 +00:00
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#define LPC_HICR0 0x000
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#define LPC_HICR0_LPC3E BIT(7)
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#define LPC_HICR0_LPC2E BIT(6)
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#define LPC_HICR0_LPC1E BIT(5)
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#define LPC_HICR2 0x008
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2021-06-08 10:47:56 +00:00
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#define LPC_HICR2_IBFIE3 BIT(3)
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#define LPC_HICR2_IBFIE2 BIT(2)
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#define LPC_HICR2_IBFIE1 BIT(1)
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2018-02-02 02:16:11 +00:00
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#define LPC_HICR4 0x010
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#define LPC_HICR4_LADR12AS BIT(7)
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#define LPC_HICR4_KCSENBL BIT(2)
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2021-06-08 10:47:55 +00:00
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#define LPC_SIRQCR0 0x070
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/* IRQ{12,1}E1 are deprecated as of AST2600 A3 but necessary for prior chips */
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#define LPC_SIRQCR0_IRQ12E1 BIT(1)
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#define LPC_SIRQCR0_IRQ1E1 BIT(0)
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#define LPC_HICR5 0x080
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#define LPC_HICR5_ID3IRQX_MASK GENMASK(23, 20)
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#define LPC_HICR5_ID3IRQX_SHIFT 20
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#define LPC_HICR5_ID2IRQX_MASK GENMASK(19, 16)
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#define LPC_HICR5_ID2IRQX_SHIFT 16
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#define LPC_HICR5_SEL3IRQX BIT(15)
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#define LPC_HICR5_IRQXE3 BIT(14)
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#define LPC_HICR5_SEL2IRQX BIT(13)
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#define LPC_HICR5_IRQXE2 BIT(12)
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2018-02-02 02:16:11 +00:00
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#define LPC_LADR3H 0x014
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#define LPC_LADR3L 0x018
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#define LPC_LADR12H 0x01C
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#define LPC_LADR12L 0x020
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#define LPC_IDR1 0x024
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#define LPC_IDR2 0x028
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#define LPC_IDR3 0x02C
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#define LPC_ODR1 0x030
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#define LPC_ODR2 0x034
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#define LPC_ODR3 0x038
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#define LPC_STR1 0x03C
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#define LPC_STR2 0x040
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#define LPC_STR3 0x044
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2021-03-19 06:27:34 +00:00
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#define LPC_HICRB 0x100
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2021-06-08 10:47:57 +00:00
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#define LPC_HICRB_EN16LADR2 BIT(5)
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#define LPC_HICRB_EN16LADR1 BIT(4)
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2021-06-08 10:47:56 +00:00
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#define LPC_HICRB_IBFIE4 BIT(1)
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2018-02-02 02:16:11 +00:00
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#define LPC_HICRB_LPC4E BIT(0)
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2021-06-08 10:47:55 +00:00
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#define LPC_HICRC 0x104
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#define LPC_HICRC_ID4IRQX_MASK GENMASK(7, 4)
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#define LPC_HICRC_ID4IRQX_SHIFT 4
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#define LPC_HICRC_TY4IRQX_MASK GENMASK(3, 2)
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#define LPC_HICRC_TY4IRQX_SHIFT 2
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#define LPC_HICRC_OBF4_AUTO_CLR BIT(1)
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#define LPC_HICRC_IRQXE4 BIT(0)
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2021-03-19 06:27:34 +00:00
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#define LPC_LADR4 0x110
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#define LPC_IDR4 0x114
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#define LPC_ODR4 0x118
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#define LPC_STR4 0x11C
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2021-06-08 10:47:57 +00:00
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#define LPC_LSADR12 0x120
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#define LPC_LSADR12_LSADR2_MASK GENMASK(31, 16)
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#define LPC_LSADR12_LSADR2_SHIFT 16
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#define LPC_LSADR12_LSADR1_MASK GENMASK(15, 0)
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#define LPC_LSADR12_LSADR1_SHIFT 0
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2018-02-02 02:16:11 +00:00
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2021-06-08 10:47:50 +00:00
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#define OBE_POLL_PERIOD (HZ / 2)
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2021-06-08 10:47:55 +00:00
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enum aspeed_kcs_irq_mode {
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aspeed_kcs_irq_none,
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aspeed_kcs_irq_serirq,
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};
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2018-02-02 02:16:11 +00:00
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struct aspeed_kcs_bmc {
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2021-06-08 10:47:48 +00:00
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struct kcs_bmc_device kcs_bmc;
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2021-06-08 10:47:46 +00:00
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2018-02-02 02:16:11 +00:00
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struct regmap *map;
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2021-06-08 10:47:50 +00:00
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2021-06-08 10:47:55 +00:00
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struct {
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enum aspeed_kcs_irq_mode mode;
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int id;
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} upstream_irq;
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2021-06-08 10:47:50 +00:00
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struct {
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spinlock_t lock;
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bool remove;
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struct timer_list timer;
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} obe;
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2018-02-02 02:16:11 +00:00
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};
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2021-06-08 10:47:42 +00:00
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struct aspeed_kcs_of_ops {
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int (*get_channel)(struct platform_device *pdev);
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2021-06-08 10:47:57 +00:00
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int (*get_io_address)(struct platform_device *pdev, u32 addrs[2]);
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2021-06-08 10:47:42 +00:00
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};
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2018-02-02 02:16:11 +00:00
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2021-06-08 10:47:48 +00:00
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static inline struct aspeed_kcs_bmc *to_aspeed_kcs_bmc(struct kcs_bmc_device *kcs_bmc)
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2021-06-08 10:47:46 +00:00
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{
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return container_of(kcs_bmc, struct aspeed_kcs_bmc, kcs_bmc);
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}
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2021-06-08 10:47:48 +00:00
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static u8 aspeed_kcs_inb(struct kcs_bmc_device *kcs_bmc, u32 reg)
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2018-02-02 02:16:11 +00:00
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{
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2021-06-08 10:47:46 +00:00
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struct aspeed_kcs_bmc *priv = to_aspeed_kcs_bmc(kcs_bmc);
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2018-02-02 02:16:11 +00:00
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u32 val = 0;
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int rc;
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rc = regmap_read(priv->map, reg, &val);
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WARN(rc != 0, "regmap_read() failed: %d\n", rc);
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return rc == 0 ? (u8) val : 0;
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}
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2021-06-08 10:47:48 +00:00
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static void aspeed_kcs_outb(struct kcs_bmc_device *kcs_bmc, u32 reg, u8 data)
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2018-02-02 02:16:11 +00:00
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{
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2021-06-08 10:47:46 +00:00
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struct aspeed_kcs_bmc *priv = to_aspeed_kcs_bmc(kcs_bmc);
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2018-02-02 02:16:11 +00:00
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int rc;
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rc = regmap_write(priv->map, reg, data);
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WARN(rc != 0, "regmap_write() failed: %d\n", rc);
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2021-06-08 10:47:55 +00:00
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/* Trigger the upstream IRQ on ODR writes, if enabled */
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switch (reg) {
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case LPC_ODR1:
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case LPC_ODR2:
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case LPC_ODR3:
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case LPC_ODR4:
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break;
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default:
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return;
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}
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if (priv->upstream_irq.mode != aspeed_kcs_irq_serirq)
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return;
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switch (kcs_bmc->channel) {
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case 1:
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switch (priv->upstream_irq.id) {
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case 12:
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regmap_update_bits(priv->map, LPC_SIRQCR0, LPC_SIRQCR0_IRQ12E1,
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LPC_SIRQCR0_IRQ12E1);
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break;
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case 1:
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regmap_update_bits(priv->map, LPC_SIRQCR0, LPC_SIRQCR0_IRQ1E1,
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LPC_SIRQCR0_IRQ1E1);
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break;
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default:
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break;
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}
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break;
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case 2:
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regmap_update_bits(priv->map, LPC_HICR5, LPC_HICR5_IRQXE2, LPC_HICR5_IRQXE2);
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break;
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case 3:
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regmap_update_bits(priv->map, LPC_HICR5, LPC_HICR5_IRQXE3, LPC_HICR5_IRQXE3);
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break;
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case 4:
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regmap_update_bits(priv->map, LPC_HICRC, LPC_HICRC_IRQXE4, LPC_HICRC_IRQXE4);
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break;
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default:
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break;
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}
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2018-02-02 02:16:11 +00:00
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}
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2021-06-08 10:47:48 +00:00
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static void aspeed_kcs_updateb(struct kcs_bmc_device *kcs_bmc, u32 reg, u8 mask, u8 val)
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2021-06-08 10:47:43 +00:00
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{
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2021-06-08 10:47:46 +00:00
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struct aspeed_kcs_bmc *priv = to_aspeed_kcs_bmc(kcs_bmc);
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2021-06-08 10:47:43 +00:00
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int rc;
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rc = regmap_update_bits(priv->map, reg, mask, val);
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WARN(rc != 0, "regmap_update_bits() failed: %d\n", rc);
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}
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2018-02-02 02:16:11 +00:00
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/*
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* AST_usrGuide_KCS.pdf
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* 2. Background:
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* we note D for Data, and C for Cmd/Status, default rules are
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* A. KCS1 / KCS2 ( D / C:X / X+4 )
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* D / C : CA0h / CA4h
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* D / C : CA8h / CACh
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* B. KCS3 ( D / C:XX2h / XX3h )
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* D / C : CA2h / CA3h
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* D / C : CB2h / CB3h
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* C. KCS4
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* D / C : CA4h / CA5h
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*/
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2021-06-08 10:47:57 +00:00
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static int aspeed_kcs_set_address(struct kcs_bmc_device *kcs_bmc, u32 addrs[2], int nr_addrs)
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2018-02-02 02:16:11 +00:00
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{
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2021-06-08 10:47:46 +00:00
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struct aspeed_kcs_bmc *priv = to_aspeed_kcs_bmc(kcs_bmc);
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2018-02-02 02:16:11 +00:00
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2021-06-08 10:47:57 +00:00
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if (WARN_ON(nr_addrs < 1 || nr_addrs > 2))
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return -EINVAL;
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switch (priv->kcs_bmc.channel) {
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2018-02-02 02:16:11 +00:00
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case 1:
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2021-06-08 10:47:57 +00:00
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regmap_update_bits(priv->map, LPC_HICR4, LPC_HICR4_LADR12AS, 0);
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regmap_write(priv->map, LPC_LADR12H, addrs[0] >> 8);
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regmap_write(priv->map, LPC_LADR12L, addrs[0] & 0xFF);
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if (nr_addrs == 2) {
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regmap_update_bits(priv->map, LPC_LSADR12, LPC_LSADR12_LSADR1_MASK,
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addrs[1] << LPC_LSADR12_LSADR1_SHIFT);
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regmap_update_bits(priv->map, LPC_HICRB, LPC_HICRB_EN16LADR1,
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LPC_HICRB_EN16LADR1);
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}
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2018-02-02 02:16:11 +00:00
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break;
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case 2:
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2021-06-08 10:47:57 +00:00
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regmap_update_bits(priv->map, LPC_HICR4, LPC_HICR4_LADR12AS, LPC_HICR4_LADR12AS);
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regmap_write(priv->map, LPC_LADR12H, addrs[0] >> 8);
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regmap_write(priv->map, LPC_LADR12L, addrs[0] & 0xFF);
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if (nr_addrs == 2) {
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regmap_update_bits(priv->map, LPC_LSADR12, LPC_LSADR12_LSADR2_MASK,
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addrs[1] << LPC_LSADR12_LSADR2_SHIFT);
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regmap_update_bits(priv->map, LPC_HICRB, LPC_HICRB_EN16LADR2,
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LPC_HICRB_EN16LADR2);
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}
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2018-02-02 02:16:11 +00:00
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break;
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case 3:
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2021-06-08 10:47:57 +00:00
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if (nr_addrs == 2) {
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dev_err(priv->kcs_bmc.dev,
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"Channel 3 only supports inferred status IO address\n");
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return -EINVAL;
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}
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regmap_write(priv->map, LPC_LADR3H, addrs[0] >> 8);
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regmap_write(priv->map, LPC_LADR3L, addrs[0] & 0xFF);
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2018-02-02 02:16:11 +00:00
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break;
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case 4:
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2021-06-08 10:47:57 +00:00
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if (nr_addrs == 1)
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regmap_write(priv->map, LPC_LADR4, ((addrs[0] + 1) << 16) | addrs[0]);
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else
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regmap_write(priv->map, LPC_LADR4, (addrs[1] << 16) | addrs[0]);
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2018-02-02 02:16:11 +00:00
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break;
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default:
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2021-06-08 10:47:57 +00:00
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return -EINVAL;
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2018-02-02 02:16:11 +00:00
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}
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2021-06-08 10:47:57 +00:00
|
|
|
|
|
|
|
return 0;
|
2018-02-02 02:16:11 +00:00
|
|
|
}
|
|
|
|
|
2021-06-08 10:47:55 +00:00
|
|
|
static inline int aspeed_kcs_map_serirq_type(u32 dt_type)
|
|
|
|
{
|
|
|
|
switch (dt_type) {
|
|
|
|
case IRQ_TYPE_EDGE_RISING:
|
|
|
|
return LPC_TYIRQX_RISING;
|
|
|
|
case IRQ_TYPE_LEVEL_HIGH:
|
|
|
|
return LPC_TYIRQX_HIGH;
|
|
|
|
case IRQ_TYPE_LEVEL_LOW:
|
|
|
|
return LPC_TYIRQX_LOW;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int aspeed_kcs_config_upstream_irq(struct aspeed_kcs_bmc *priv, u32 id, u32 dt_type)
|
|
|
|
{
|
|
|
|
unsigned int mask, val, hw_type;
|
2021-06-16 16:29:13 +00:00
|
|
|
int ret;
|
2021-06-08 10:47:55 +00:00
|
|
|
|
|
|
|
if (id > 15)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2021-06-16 16:29:13 +00:00
|
|
|
ret = aspeed_kcs_map_serirq_type(dt_type);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
hw_type = ret;
|
2021-06-08 10:47:55 +00:00
|
|
|
|
|
|
|
priv->upstream_irq.mode = aspeed_kcs_irq_serirq;
|
|
|
|
priv->upstream_irq.id = id;
|
|
|
|
|
|
|
|
switch (priv->kcs_bmc.channel) {
|
|
|
|
case 1:
|
|
|
|
/* Needs IRQxE1 rather than (ID1IRQX, SEL1IRQX, IRQXE1) before AST2600 A3 */
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
if (!(hw_type == LPC_TYIRQX_LOW || hw_type == LPC_TYIRQX_HIGH))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
mask = LPC_HICR5_SEL2IRQX | LPC_HICR5_ID2IRQX_MASK;
|
|
|
|
val = (id << LPC_HICR5_ID2IRQX_SHIFT);
|
|
|
|
val |= (hw_type == LPC_TYIRQX_HIGH) ? LPC_HICR5_SEL2IRQX : 0;
|
|
|
|
regmap_update_bits(priv->map, LPC_HICR5, mask, val);
|
|
|
|
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
if (!(hw_type == LPC_TYIRQX_LOW || hw_type == LPC_TYIRQX_HIGH))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
mask = LPC_HICR5_SEL3IRQX | LPC_HICR5_ID3IRQX_MASK;
|
|
|
|
val = (id << LPC_HICR5_ID3IRQX_SHIFT);
|
|
|
|
val |= (hw_type == LPC_TYIRQX_HIGH) ? LPC_HICR5_SEL3IRQX : 0;
|
|
|
|
regmap_update_bits(priv->map, LPC_HICR5, mask, val);
|
|
|
|
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
mask = LPC_HICRC_ID4IRQX_MASK | LPC_HICRC_TY4IRQX_MASK | LPC_HICRC_OBF4_AUTO_CLR;
|
|
|
|
val = (id << LPC_HICRC_ID4IRQX_SHIFT) | (hw_type << LPC_HICRC_TY4IRQX_SHIFT);
|
|
|
|
regmap_update_bits(priv->map, LPC_HICRC, mask, val);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_warn(priv->kcs_bmc.dev,
|
|
|
|
"SerIRQ configuration not supported on KCS channel %d\n",
|
|
|
|
priv->kcs_bmc.channel);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-06-08 10:47:48 +00:00
|
|
|
static void aspeed_kcs_enable_channel(struct kcs_bmc_device *kcs_bmc, bool enable)
|
2018-02-02 02:16:11 +00:00
|
|
|
{
|
2021-06-08 10:47:46 +00:00
|
|
|
struct aspeed_kcs_bmc *priv = to_aspeed_kcs_bmc(kcs_bmc);
|
2018-02-02 02:16:11 +00:00
|
|
|
|
|
|
|
switch (kcs_bmc->channel) {
|
|
|
|
case 1:
|
2021-06-08 10:47:50 +00:00
|
|
|
regmap_update_bits(priv->map, LPC_HICR0, LPC_HICR0_LPC1E, enable * LPC_HICR0_LPC1E);
|
|
|
|
return;
|
2018-02-02 02:16:11 +00:00
|
|
|
case 2:
|
2021-06-08 10:47:50 +00:00
|
|
|
regmap_update_bits(priv->map, LPC_HICR0, LPC_HICR0_LPC2E, enable * LPC_HICR0_LPC2E);
|
|
|
|
return;
|
2018-02-02 02:16:11 +00:00
|
|
|
case 3:
|
2021-06-08 10:47:50 +00:00
|
|
|
regmap_update_bits(priv->map, LPC_HICR0, LPC_HICR0_LPC3E, enable * LPC_HICR0_LPC3E);
|
|
|
|
regmap_update_bits(priv->map, LPC_HICR4,
|
|
|
|
LPC_HICR4_KCSENBL, enable * LPC_HICR4_KCSENBL);
|
|
|
|
return;
|
2018-02-02 02:16:11 +00:00
|
|
|
case 4:
|
2021-06-08 10:47:50 +00:00
|
|
|
regmap_update_bits(priv->map, LPC_HICRB, LPC_HICRB_LPC4E, enable * LPC_HICRB_LPC4E);
|
|
|
|
return;
|
|
|
|
default:
|
|
|
|
pr_warn("%s: Unsupported channel: %d", __func__, kcs_bmc->channel);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void aspeed_kcs_check_obe(struct timer_list *timer)
|
|
|
|
{
|
|
|
|
struct aspeed_kcs_bmc *priv = container_of(timer, struct aspeed_kcs_bmc, obe.timer);
|
|
|
|
unsigned long flags;
|
|
|
|
u8 str;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&priv->obe.lock, flags);
|
|
|
|
if (priv->obe.remove) {
|
|
|
|
spin_unlock_irqrestore(&priv->obe.lock, flags);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
str = aspeed_kcs_inb(&priv->kcs_bmc, priv->kcs_bmc.ioreg.str);
|
|
|
|
if (str & KCS_BMC_STR_OBF) {
|
|
|
|
mod_timer(timer, jiffies + OBE_POLL_PERIOD);
|
|
|
|
spin_unlock_irqrestore(&priv->obe.lock, flags);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&priv->obe.lock, flags);
|
|
|
|
|
|
|
|
kcs_bmc_handle_event(&priv->kcs_bmc);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void aspeed_kcs_irq_mask_update(struct kcs_bmc_device *kcs_bmc, u8 mask, u8 state)
|
|
|
|
{
|
|
|
|
struct aspeed_kcs_bmc *priv = to_aspeed_kcs_bmc(kcs_bmc);
|
|
|
|
|
|
|
|
/* We don't have an OBE IRQ, emulate it */
|
|
|
|
if (mask & KCS_BMC_EVENT_TYPE_OBE) {
|
|
|
|
if (KCS_BMC_EVENT_TYPE_OBE & state)
|
|
|
|
mod_timer(&priv->obe.timer, jiffies + OBE_POLL_PERIOD);
|
2018-02-02 02:16:11 +00:00
|
|
|
else
|
2021-06-08 10:47:50 +00:00
|
|
|
del_timer(&priv->obe.timer);
|
|
|
|
}
|
2018-02-02 02:16:11 +00:00
|
|
|
|
2021-06-08 10:47:50 +00:00
|
|
|
if (mask & KCS_BMC_EVENT_TYPE_IBF) {
|
|
|
|
const bool enable = !!(state & KCS_BMC_EVENT_TYPE_IBF);
|
|
|
|
|
|
|
|
switch (kcs_bmc->channel) {
|
|
|
|
case 1:
|
2021-06-08 10:47:56 +00:00
|
|
|
regmap_update_bits(priv->map, LPC_HICR2, LPC_HICR2_IBFIE1,
|
|
|
|
enable * LPC_HICR2_IBFIE1);
|
2021-06-08 10:47:50 +00:00
|
|
|
return;
|
|
|
|
case 2:
|
2021-06-08 10:47:56 +00:00
|
|
|
regmap_update_bits(priv->map, LPC_HICR2, LPC_HICR2_IBFIE2,
|
|
|
|
enable * LPC_HICR2_IBFIE2);
|
2021-06-08 10:47:50 +00:00
|
|
|
return;
|
|
|
|
case 3:
|
2021-06-08 10:47:56 +00:00
|
|
|
regmap_update_bits(priv->map, LPC_HICR2, LPC_HICR2_IBFIE3,
|
|
|
|
enable * LPC_HICR2_IBFIE3);
|
2021-06-08 10:47:50 +00:00
|
|
|
return;
|
|
|
|
case 4:
|
2021-06-08 10:47:56 +00:00
|
|
|
regmap_update_bits(priv->map, LPC_HICRB, LPC_HICRB_IBFIE4,
|
|
|
|
enable * LPC_HICRB_IBFIE4);
|
2021-06-08 10:47:50 +00:00
|
|
|
return;
|
|
|
|
default:
|
|
|
|
pr_warn("%s: Unsupported channel: %d", __func__, kcs_bmc->channel);
|
|
|
|
return;
|
|
|
|
}
|
2018-02-02 02:16:11 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-06-08 10:47:47 +00:00
|
|
|
static const struct kcs_bmc_device_ops aspeed_kcs_ops = {
|
2021-06-08 10:47:50 +00:00
|
|
|
.irq_mask_update = aspeed_kcs_irq_mask_update,
|
2021-06-08 10:47:47 +00:00
|
|
|
.io_inputb = aspeed_kcs_inb,
|
|
|
|
.io_outputb = aspeed_kcs_outb,
|
|
|
|
.io_updateb = aspeed_kcs_updateb,
|
|
|
|
};
|
|
|
|
|
2018-02-02 02:16:11 +00:00
|
|
|
static irqreturn_t aspeed_kcs_irq(int irq, void *arg)
|
|
|
|
{
|
2021-06-08 10:47:48 +00:00
|
|
|
struct kcs_bmc_device *kcs_bmc = arg;
|
2018-02-02 02:16:11 +00:00
|
|
|
|
2021-06-08 10:47:47 +00:00
|
|
|
return kcs_bmc_handle_event(kcs_bmc);
|
2018-02-02 02:16:11 +00:00
|
|
|
}
|
|
|
|
|
2021-06-08 10:47:55 +00:00
|
|
|
static int aspeed_kcs_config_downstream_irq(struct kcs_bmc_device *kcs_bmc,
|
2018-02-02 02:16:11 +00:00
|
|
|
struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
int irq;
|
|
|
|
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
if (irq < 0)
|
|
|
|
return irq;
|
|
|
|
|
|
|
|
return devm_request_irq(dev, irq, aspeed_kcs_irq, IRQF_SHARED,
|
|
|
|
dev_name(dev), kcs_bmc);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct kcs_ioreg ast_kcs_bmc_ioregs[KCS_CHANNEL_MAX] = {
|
|
|
|
{ .idr = LPC_IDR1, .odr = LPC_ODR1, .str = LPC_STR1 },
|
|
|
|
{ .idr = LPC_IDR2, .odr = LPC_ODR2, .str = LPC_STR2 },
|
|
|
|
{ .idr = LPC_IDR3, .odr = LPC_ODR3, .str = LPC_STR3 },
|
|
|
|
{ .idr = LPC_IDR4, .odr = LPC_ODR4, .str = LPC_STR4 },
|
|
|
|
};
|
|
|
|
|
2021-06-08 10:47:42 +00:00
|
|
|
static int aspeed_kcs_of_v1_get_channel(struct platform_device *pdev)
|
2018-02-02 02:16:11 +00:00
|
|
|
{
|
2019-12-16 02:27:42 +00:00
|
|
|
struct device_node *np;
|
|
|
|
u32 channel;
|
2018-02-02 02:16:11 +00:00
|
|
|
int rc;
|
|
|
|
|
2019-12-16 02:27:42 +00:00
|
|
|
np = pdev->dev.of_node;
|
|
|
|
|
|
|
|
rc = of_property_read_u32(np, "kcs_chan", &channel);
|
|
|
|
if ((rc != 0) || (channel == 0 || channel > KCS_CHANNEL_MAX)) {
|
|
|
|
dev_err(&pdev->dev, "no valid 'kcs_chan' configured\n");
|
2021-06-08 10:47:42 +00:00
|
|
|
return -EINVAL;
|
2018-02-02 02:16:11 +00:00
|
|
|
}
|
|
|
|
|
2021-06-08 10:47:42 +00:00
|
|
|
return channel;
|
2019-12-16 02:27:42 +00:00
|
|
|
}
|
|
|
|
|
2021-06-08 10:47:57 +00:00
|
|
|
static int
|
|
|
|
aspeed_kcs_of_v1_get_io_address(struct platform_device *pdev, u32 addrs[2])
|
2019-12-16 02:27:42 +00:00
|
|
|
{
|
2021-06-08 10:47:42 +00:00
|
|
|
int rc;
|
2019-12-16 02:27:42 +00:00
|
|
|
|
2021-06-08 10:47:57 +00:00
|
|
|
rc = of_property_read_u32(pdev->dev.of_node, "kcs_addr", addrs);
|
|
|
|
if (rc || addrs[0] > 0xffff) {
|
2021-06-08 10:47:42 +00:00
|
|
|
dev_err(&pdev->dev, "no valid 'kcs_addr' configured\n");
|
|
|
|
return -EINVAL;
|
2019-12-16 02:27:42 +00:00
|
|
|
}
|
|
|
|
|
2021-06-08 10:47:57 +00:00
|
|
|
return 1;
|
2019-12-16 02:27:42 +00:00
|
|
|
}
|
|
|
|
|
2021-06-08 10:47:42 +00:00
|
|
|
static int aspeed_kcs_of_v2_get_channel(struct platform_device *pdev)
|
2019-12-16 02:27:42 +00:00
|
|
|
{
|
|
|
|
struct device_node *np;
|
|
|
|
struct kcs_ioreg ioreg;
|
|
|
|
const __be32 *reg;
|
2021-06-08 10:47:42 +00:00
|
|
|
int i;
|
2018-02-02 02:16:11 +00:00
|
|
|
|
2019-12-16 02:27:42 +00:00
|
|
|
np = pdev->dev.of_node;
|
|
|
|
|
|
|
|
/* Don't translate addresses, we want offsets for the regmaps */
|
|
|
|
reg = of_get_address(np, 0, NULL, NULL);
|
|
|
|
if (!reg)
|
2021-06-08 10:47:42 +00:00
|
|
|
return -EINVAL;
|
2019-12-16 02:27:42 +00:00
|
|
|
ioreg.idr = be32_to_cpup(reg);
|
|
|
|
|
|
|
|
reg = of_get_address(np, 1, NULL, NULL);
|
|
|
|
if (!reg)
|
2021-06-08 10:47:42 +00:00
|
|
|
return -EINVAL;
|
2019-12-16 02:27:42 +00:00
|
|
|
ioreg.odr = be32_to_cpup(reg);
|
|
|
|
|
|
|
|
reg = of_get_address(np, 2, NULL, NULL);
|
|
|
|
if (!reg)
|
2021-06-08 10:47:42 +00:00
|
|
|
return -EINVAL;
|
2019-12-16 02:27:42 +00:00
|
|
|
ioreg.str = be32_to_cpup(reg);
|
|
|
|
|
2021-06-08 10:47:42 +00:00
|
|
|
for (i = 0; i < ARRAY_SIZE(ast_kcs_bmc_ioregs); i++) {
|
|
|
|
if (!memcmp(&ast_kcs_bmc_ioregs[i], &ioreg, sizeof(ioreg)))
|
|
|
|
return i + 1;
|
|
|
|
}
|
2019-12-16 02:27:42 +00:00
|
|
|
|
2021-06-08 10:47:42 +00:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
2019-12-16 02:27:42 +00:00
|
|
|
|
2021-06-08 10:47:57 +00:00
|
|
|
static int
|
|
|
|
aspeed_kcs_of_v2_get_io_address(struct platform_device *pdev, u32 addrs[2])
|
2021-06-08 10:47:42 +00:00
|
|
|
{
|
|
|
|
int rc;
|
2019-12-16 02:27:42 +00:00
|
|
|
|
2021-06-08 10:47:57 +00:00
|
|
|
rc = of_property_read_variable_u32_array(pdev->dev.of_node,
|
|
|
|
"aspeed,lpc-io-reg",
|
|
|
|
addrs, 1, 2);
|
|
|
|
if (rc < 0) {
|
|
|
|
dev_err(&pdev->dev, "No valid 'aspeed,lpc-io-reg' configured\n");
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (addrs[0] > 0xffff) {
|
|
|
|
dev_err(&pdev->dev, "Invalid data address in 'aspeed,lpc-io-reg'\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (rc == 2 && addrs[1] > 0xffff) {
|
|
|
|
dev_err(&pdev->dev, "Invalid status address in 'aspeed,lpc-io-reg'\n");
|
2021-06-08 10:47:42 +00:00
|
|
|
return -EINVAL;
|
2018-02-02 02:16:11 +00:00
|
|
|
}
|
|
|
|
|
2021-06-08 10:47:57 +00:00
|
|
|
return rc;
|
2019-12-16 02:27:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int aspeed_kcs_probe(struct platform_device *pdev)
|
|
|
|
{
|
2021-06-08 10:47:42 +00:00
|
|
|
const struct aspeed_kcs_of_ops *ops;
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2021-06-08 10:47:48 +00:00
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struct kcs_bmc_device *kcs_bmc;
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2021-06-08 10:47:42 +00:00
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struct aspeed_kcs_bmc *priv;
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2019-12-16 02:27:42 +00:00
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struct device_node *np;
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2021-06-08 10:47:55 +00:00
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bool have_upstream_irq;
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u32 upstream_irq[2];
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2021-06-08 10:47:57 +00:00
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int rc, channel;
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int nr_addrs;
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u32 addrs[2];
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2019-12-16 02:27:42 +00:00
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2021-06-08 10:47:46 +00:00
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np = pdev->dev.of_node->parent;
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2021-03-19 06:27:34 +00:00
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if (!of_device_is_compatible(np, "aspeed,ast2400-lpc-v2") &&
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!of_device_is_compatible(np, "aspeed,ast2500-lpc-v2") &&
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!of_device_is_compatible(np, "aspeed,ast2600-lpc-v2")) {
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2021-06-08 10:47:46 +00:00
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dev_err(&pdev->dev, "unsupported LPC device binding\n");
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2021-03-19 06:27:34 +00:00
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return -ENODEV;
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}
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2021-06-08 10:47:55 +00:00
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2021-06-08 10:47:42 +00:00
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ops = of_device_get_match_data(&pdev->dev);
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if (!ops)
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2019-12-16 02:27:42 +00:00
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return -EINVAL;
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2021-06-08 10:47:42 +00:00
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channel = ops->get_channel(pdev);
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if (channel < 0)
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return channel;
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2021-06-08 10:47:57 +00:00
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nr_addrs = ops->get_io_address(pdev, addrs);
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if (nr_addrs < 0)
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return nr_addrs;
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2021-06-08 10:47:46 +00:00
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2021-06-08 10:47:55 +00:00
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np = pdev->dev.of_node;
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rc = of_property_read_u32_array(np, "aspeed,lpc-interrupts", upstream_irq, 2);
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if (rc && rc != -EINVAL)
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return -EINVAL;
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have_upstream_irq = !rc;
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2021-06-08 10:47:46 +00:00
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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2021-06-08 10:47:42 +00:00
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return -ENOMEM;
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2019-12-16 02:27:42 +00:00
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2021-06-08 10:47:46 +00:00
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kcs_bmc = &priv->kcs_bmc;
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kcs_bmc->dev = &pdev->dev;
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kcs_bmc->channel = channel;
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2021-06-08 10:47:42 +00:00
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kcs_bmc->ioreg = ast_kcs_bmc_ioregs[channel - 1];
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2021-06-08 10:47:47 +00:00
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kcs_bmc->ops = &aspeed_kcs_ops;
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2018-02-02 02:16:11 +00:00
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2021-06-08 10:47:42 +00:00
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priv->map = syscon_node_to_regmap(pdev->dev.parent->of_node);
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if (IS_ERR(priv->map)) {
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dev_err(&pdev->dev, "Couldn't get regmap\n");
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return -ENODEV;
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}
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2021-06-08 10:47:50 +00:00
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spin_lock_init(&priv->obe.lock);
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priv->obe.remove = false;
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timer_setup(&priv->obe.timer, aspeed_kcs_check_obe, 0);
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2021-06-08 10:47:57 +00:00
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rc = aspeed_kcs_set_address(kcs_bmc, addrs, nr_addrs);
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if (rc)
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return rc;
|
2021-06-08 10:47:42 +00:00
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|
2021-06-08 10:47:55 +00:00
|
|
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/* Host to BMC IRQ */
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rc = aspeed_kcs_config_downstream_irq(kcs_bmc, pdev);
|
2019-12-16 02:27:41 +00:00
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if (rc)
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return rc;
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|
2021-06-08 10:47:55 +00:00
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/* BMC to Host IRQ */
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|
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if (have_upstream_irq) {
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|
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rc = aspeed_kcs_config_upstream_irq(priv, upstream_irq[0], upstream_irq[1]);
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|
|
if (rc < 0)
|
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return rc;
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|
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} else {
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|
|
priv->upstream_irq.mode = aspeed_kcs_irq_none;
|
|
|
|
}
|
|
|
|
|
2021-06-08 10:47:46 +00:00
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|
|
platform_set_drvdata(pdev, priv);
|
2018-02-02 02:16:11 +00:00
|
|
|
|
2021-06-08 10:47:51 +00:00
|
|
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aspeed_kcs_irq_mask_update(kcs_bmc, (KCS_BMC_EVENT_TYPE_IBF | KCS_BMC_EVENT_TYPE_OBE), 0);
|
2018-02-02 02:16:11 +00:00
|
|
|
aspeed_kcs_enable_channel(kcs_bmc, true);
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|
|
|
|
2021-06-08 10:47:46 +00:00
|
|
|
rc = kcs_bmc_add_device(&priv->kcs_bmc);
|
2018-02-02 02:16:11 +00:00
|
|
|
if (rc) {
|
2021-06-08 10:47:46 +00:00
|
|
|
dev_warn(&pdev->dev, "Failed to register channel %d: %d\n", kcs_bmc->channel, rc);
|
2018-02-02 02:16:11 +00:00
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|
|
return rc;
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|
|
|
}
|
|
|
|
|
2021-06-08 10:47:57 +00:00
|
|
|
dev_info(&pdev->dev, "Initialised channel %d at 0x%x\n",
|
|
|
|
kcs_bmc->channel, addrs[0]);
|
2018-02-02 02:16:11 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int aspeed_kcs_remove(struct platform_device *pdev)
|
|
|
|
{
|
2021-06-08 10:47:46 +00:00
|
|
|
struct aspeed_kcs_bmc *priv = platform_get_drvdata(pdev);
|
2021-06-08 10:47:48 +00:00
|
|
|
struct kcs_bmc_device *kcs_bmc = &priv->kcs_bmc;
|
2018-02-02 02:16:11 +00:00
|
|
|
|
2021-06-08 10:47:46 +00:00
|
|
|
kcs_bmc_remove_device(kcs_bmc);
|
2018-02-02 02:16:11 +00:00
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|
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|
2021-06-08 10:47:50 +00:00
|
|
|
aspeed_kcs_enable_channel(kcs_bmc, false);
|
|
|
|
aspeed_kcs_irq_mask_update(kcs_bmc, (KCS_BMC_EVENT_TYPE_IBF | KCS_BMC_EVENT_TYPE_OBE), 0);
|
|
|
|
|
|
|
|
/* Make sure it's proper dead */
|
|
|
|
spin_lock_irq(&priv->obe.lock);
|
|
|
|
priv->obe.remove = true;
|
|
|
|
spin_unlock_irq(&priv->obe.lock);
|
|
|
|
del_timer_sync(&priv->obe.timer);
|
|
|
|
|
2018-02-02 02:16:11 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-06-08 10:47:42 +00:00
|
|
|
static const struct aspeed_kcs_of_ops of_v1_ops = {
|
|
|
|
.get_channel = aspeed_kcs_of_v1_get_channel,
|
|
|
|
.get_io_address = aspeed_kcs_of_v1_get_io_address,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct aspeed_kcs_of_ops of_v2_ops = {
|
|
|
|
.get_channel = aspeed_kcs_of_v2_get_channel,
|
|
|
|
.get_io_address = aspeed_kcs_of_v2_get_io_address,
|
|
|
|
};
|
|
|
|
|
2018-02-02 02:16:11 +00:00
|
|
|
static const struct of_device_id ast_kcs_bmc_match[] = {
|
2021-06-08 10:47:42 +00:00
|
|
|
{ .compatible = "aspeed,ast2400-kcs-bmc", .data = &of_v1_ops },
|
|
|
|
{ .compatible = "aspeed,ast2500-kcs-bmc", .data = &of_v1_ops },
|
|
|
|
{ .compatible = "aspeed,ast2400-kcs-bmc-v2", .data = &of_v2_ops },
|
|
|
|
{ .compatible = "aspeed,ast2500-kcs-bmc-v2", .data = &of_v2_ops },
|
2018-02-02 02:16:11 +00:00
|
|
|
{ }
|
|
|
|
};
|
2018-02-26 15:48:14 +00:00
|
|
|
MODULE_DEVICE_TABLE(of, ast_kcs_bmc_match);
|
2018-02-02 02:16:11 +00:00
|
|
|
|
|
|
|
static struct platform_driver ast_kcs_bmc_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = DEVICE_NAME,
|
|
|
|
.of_match_table = ast_kcs_bmc_match,
|
|
|
|
},
|
2018-02-26 15:48:14 +00:00
|
|
|
.probe = aspeed_kcs_probe,
|
2018-02-02 02:16:11 +00:00
|
|
|
.remove = aspeed_kcs_remove,
|
|
|
|
};
|
|
|
|
module_platform_driver(ast_kcs_bmc_driver);
|
|
|
|
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_AUTHOR("Haiyue Wang <haiyue.wang@linux.intel.com>");
|
2021-06-08 10:47:55 +00:00
|
|
|
MODULE_AUTHOR("Andrew Jeffery <andrew@aj.id.au>");
|
2018-02-02 02:16:11 +00:00
|
|
|
MODULE_DESCRIPTION("Aspeed device interface to the KCS BMC device");
|