2020-03-06 04:28:24 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
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2021-03-24 13:15:25 +00:00
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* Copyright (C) 2019-2021 Linaro Ltd.
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2020-03-06 04:28:24 +00:00
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*/
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#include <linux/types.h>
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/bitfield.h>
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#include <linux/if_rmnet.h>
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#include <linux/dma-direction.h>
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#include "gsi.h"
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#include "gsi_trans.h"
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#include "ipa.h"
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#include "ipa_data.h"
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#include "ipa_endpoint.h"
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#include "ipa_cmd.h"
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#include "ipa_mem.h"
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#include "ipa_modem.h"
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#include "ipa_table.h"
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#include "ipa_gsi.h"
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2021-08-20 16:01:29 +00:00
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#include "ipa_power.h"
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2020-03-06 04:28:24 +00:00
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#define atomic_dec_not_zero(v) atomic_add_unless((v), -1, 0)
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#define IPA_REPLENISH_BATCH 16
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2020-03-20 16:02:20 +00:00
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/* RX buffer is 1 page (or a power-of-2 contiguous pages) */
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#define IPA_RX_BUFFER_SIZE 8192 /* PAGE_SIZE > 4096 wastes a LOT */
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2020-03-06 04:28:24 +00:00
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/* The amount of RX buffer space consumed by standard skb overhead */
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#define IPA_RX_BUFFER_OVERHEAD (PAGE_SIZE - SKB_MAX_ORDER(NET_SKB_PAD, 0))
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2020-06-11 19:48:30 +00:00
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/* Where to find the QMAP mux_id for a packet within modem-supplied metadata */
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#define IPA_ENDPOINT_QMAP_METADATA_MASK 0x000000ff /* host byte order */
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2020-03-06 04:28:24 +00:00
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#define IPA_ENDPOINT_RESET_AGGR_RETRY_MAX 3
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net: ipa: update IPA aggregation registers for IPA v4.5
IPA v4.5 significantly changes the format of the configuration
register used for endpoint aggregation. The AGGR_BYTE_LIMIT field
is now larger, and the positions of other fields are shifted. This
complicates the way we have to access this register because functions
like u32_encode_bits() require their field mask argument to be constant.
A further complication is that we want to know the maximum value
representable by at least one of these fields, and that too requires
a constant field mask.
This patch adds support for IPA v4.5 endpoint aggregation registers
in a way that continues to support "legacy" IPA hardware. It does
so in a way that keeps field masks constant.
First, for each variable field mask, we define an inline function
whose return value is either the legacy value or the IPA v4.5 value.
Second, we define functions for these fields that encode a value
to use in each field based on the IPA version (this approach is
already used elsewhere). The field mask provided is supplied by
the function mentioned above.
Finally, for the aggregation byte limit fields where we want to
know the maximum representable value, we define a function that
returns that maximum, computed from the appropriate field mask.
We can no longer verify at build time that our buffer size is
in the range that can be represented by the aggregation byte
limit field. So remove the test done by a BUILD_BUG_ON() call
in ipa_endpoint_validate_build(), and implement a comparable check
at the top of ipa_endpoint_data_valid().
Doing that makes ipa_endpoint_validate_build() contain a single
line BUILD_BUG_ON() call, so just remove that function and move
the remaining line into ipa_endpoint_data_valid().
One final note: the aggregation time limit value for IPA v4.5 needs
to be computed differently. That is handled in an upcoming patch.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-30 23:37:09 +00:00
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#define IPA_AGGR_TIME_LIMIT 500 /* microseconds */
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2020-03-06 04:28:24 +00:00
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/** enum ipa_status_opcode - status element opcode hardware values */
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enum ipa_status_opcode {
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IPA_STATUS_OPCODE_PACKET = 0x01,
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IPA_STATUS_OPCODE_DROPPED_PACKET = 0x04,
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IPA_STATUS_OPCODE_SUSPENDED_PACKET = 0x08,
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IPA_STATUS_OPCODE_PACKET_2ND_PASS = 0x40,
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};
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/** enum ipa_status_exception - status element exception type */
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enum ipa_status_exception {
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/* 0 means no exception */
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IPA_STATUS_EXCEPTION_DEAGGR = 0x01,
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};
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/* Status element provided by hardware */
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struct ipa_status {
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u8 opcode; /* enum ipa_status_opcode */
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u8 exception; /* enum ipa_status_exception */
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__le16 mask;
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__le16 pkt_len;
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u8 endp_src_idx;
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u8 endp_dst_idx;
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__le32 metadata;
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__le32 flags1;
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__le64 flags2;
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__le32 flags3;
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__le32 flags4;
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};
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/* Field masks for struct ipa_status structure fields */
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2021-01-26 18:57:00 +00:00
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#define IPA_STATUS_MASK_TAG_VALID_FMASK GENMASK(4, 4)
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#define IPA_STATUS_SRC_IDX_FMASK GENMASK(4, 0)
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2020-03-06 04:28:24 +00:00
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#define IPA_STATUS_DST_IDX_FMASK GENMASK(4, 0)
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#define IPA_STATUS_FLAGS1_RT_RULE_ID_FMASK GENMASK(31, 22)
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2021-01-26 18:57:00 +00:00
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#define IPA_STATUS_FLAGS2_TAG_FMASK GENMASK_ULL(63, 16)
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2020-03-06 04:28:24 +00:00
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static bool ipa_endpoint_data_valid_one(struct ipa *ipa, u32 count,
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const struct ipa_gsi_endpoint_data *all_data,
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const struct ipa_gsi_endpoint_data *data)
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{
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const struct ipa_gsi_endpoint_data *other_data;
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struct device *dev = &ipa->pdev->dev;
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enum ipa_endpoint_name other_name;
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if (ipa_gsi_endpoint_data_empty(data))
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return true;
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if (!data->toward_ipa) {
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if (data->endpoint.filter_support) {
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dev_err(dev, "filtering not supported for "
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"RX endpoint %u\n",
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data->endpoint_id);
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return false;
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}
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return true; /* Nothing more to check for RX */
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}
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if (data->endpoint.config.status_enable) {
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other_name = data->endpoint.config.tx.status_endpoint;
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if (other_name >= count) {
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dev_err(dev, "status endpoint name %u out of range "
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"for endpoint %u\n",
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other_name, data->endpoint_id);
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return false;
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}
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/* Status endpoint must be defined... */
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other_data = &all_data[other_name];
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if (ipa_gsi_endpoint_data_empty(other_data)) {
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dev_err(dev, "DMA endpoint name %u undefined "
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"for endpoint %u\n",
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other_name, data->endpoint_id);
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return false;
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}
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/* ...and has to be an RX endpoint... */
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if (other_data->toward_ipa) {
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dev_err(dev,
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"status endpoint for endpoint %u not RX\n",
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data->endpoint_id);
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return false;
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}
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/* ...and if it's to be an AP endpoint... */
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if (other_data->ee_id == GSI_EE_AP) {
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/* ...make sure it has status enabled. */
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if (!other_data->endpoint.config.status_enable) {
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dev_err(dev,
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"status not enabled for endpoint %u\n",
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other_data->endpoint_id);
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return false;
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}
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}
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}
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if (data->endpoint.config.dma_mode) {
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other_name = data->endpoint.config.dma_endpoint;
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if (other_name >= count) {
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dev_err(dev, "DMA endpoint name %u out of range "
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"for endpoint %u\n",
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other_name, data->endpoint_id);
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return false;
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}
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other_data = &all_data[other_name];
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if (ipa_gsi_endpoint_data_empty(other_data)) {
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dev_err(dev, "DMA endpoint name %u undefined "
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"for endpoint %u\n",
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other_name, data->endpoint_id);
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return false;
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}
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}
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return true;
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}
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net: ipa: update IPA aggregation registers for IPA v4.5
IPA v4.5 significantly changes the format of the configuration
register used for endpoint aggregation. The AGGR_BYTE_LIMIT field
is now larger, and the positions of other fields are shifted. This
complicates the way we have to access this register because functions
like u32_encode_bits() require their field mask argument to be constant.
A further complication is that we want to know the maximum value
representable by at least one of these fields, and that too requires
a constant field mask.
This patch adds support for IPA v4.5 endpoint aggregation registers
in a way that continues to support "legacy" IPA hardware. It does
so in a way that keeps field masks constant.
First, for each variable field mask, we define an inline function
whose return value is either the legacy value or the IPA v4.5 value.
Second, we define functions for these fields that encode a value
to use in each field based on the IPA version (this approach is
already used elsewhere). The field mask provided is supplied by
the function mentioned above.
Finally, for the aggregation byte limit fields where we want to
know the maximum representable value, we define a function that
returns that maximum, computed from the appropriate field mask.
We can no longer verify at build time that our buffer size is
in the range that can be represented by the aggregation byte
limit field. So remove the test done by a BUILD_BUG_ON() call
in ipa_endpoint_validate_build(), and implement a comparable check
at the top of ipa_endpoint_data_valid().
Doing that makes ipa_endpoint_validate_build() contain a single
line BUILD_BUG_ON() call, so just remove that function and move
the remaining line into ipa_endpoint_data_valid().
One final note: the aggregation time limit value for IPA v4.5 needs
to be computed differently. That is handled in an upcoming patch.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-30 23:37:09 +00:00
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static u32 aggr_byte_limit_max(enum ipa_version version)
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{
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if (version < IPA_VERSION_4_5)
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return field_max(aggr_byte_limit_fmask(true));
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return field_max(aggr_byte_limit_fmask(false));
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}
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2020-03-06 04:28:24 +00:00
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static bool ipa_endpoint_data_valid(struct ipa *ipa, u32 count,
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const struct ipa_gsi_endpoint_data *data)
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{
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const struct ipa_gsi_endpoint_data *dp = data;
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struct device *dev = &ipa->pdev->dev;
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enum ipa_endpoint_name name;
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net: ipa: update IPA aggregation registers for IPA v4.5
IPA v4.5 significantly changes the format of the configuration
register used for endpoint aggregation. The AGGR_BYTE_LIMIT field
is now larger, and the positions of other fields are shifted. This
complicates the way we have to access this register because functions
like u32_encode_bits() require their field mask argument to be constant.
A further complication is that we want to know the maximum value
representable by at least one of these fields, and that too requires
a constant field mask.
This patch adds support for IPA v4.5 endpoint aggregation registers
in a way that continues to support "legacy" IPA hardware. It does
so in a way that keeps field masks constant.
First, for each variable field mask, we define an inline function
whose return value is either the legacy value or the IPA v4.5 value.
Second, we define functions for these fields that encode a value
to use in each field based on the IPA version (this approach is
already used elsewhere). The field mask provided is supplied by
the function mentioned above.
Finally, for the aggregation byte limit fields where we want to
know the maximum representable value, we define a function that
returns that maximum, computed from the appropriate field mask.
We can no longer verify at build time that our buffer size is
in the range that can be represented by the aggregation byte
limit field. So remove the test done by a BUILD_BUG_ON() call
in ipa_endpoint_validate_build(), and implement a comparable check
at the top of ipa_endpoint_data_valid().
Doing that makes ipa_endpoint_validate_build() contain a single
line BUILD_BUG_ON() call, so just remove that function and move
the remaining line into ipa_endpoint_data_valid().
One final note: the aggregation time limit value for IPA v4.5 needs
to be computed differently. That is handled in an upcoming patch.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-30 23:37:09 +00:00
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u32 limit;
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2020-03-06 04:28:24 +00:00
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if (count > IPA_ENDPOINT_COUNT) {
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dev_err(dev, "too many endpoints specified (%u > %u)\n",
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count, IPA_ENDPOINT_COUNT);
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return false;
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}
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net: ipa: update IPA aggregation registers for IPA v4.5
IPA v4.5 significantly changes the format of the configuration
register used for endpoint aggregation. The AGGR_BYTE_LIMIT field
is now larger, and the positions of other fields are shifted. This
complicates the way we have to access this register because functions
like u32_encode_bits() require their field mask argument to be constant.
A further complication is that we want to know the maximum value
representable by at least one of these fields, and that too requires
a constant field mask.
This patch adds support for IPA v4.5 endpoint aggregation registers
in a way that continues to support "legacy" IPA hardware. It does
so in a way that keeps field masks constant.
First, for each variable field mask, we define an inline function
whose return value is either the legacy value or the IPA v4.5 value.
Second, we define functions for these fields that encode a value
to use in each field based on the IPA version (this approach is
already used elsewhere). The field mask provided is supplied by
the function mentioned above.
Finally, for the aggregation byte limit fields where we want to
know the maximum representable value, we define a function that
returns that maximum, computed from the appropriate field mask.
We can no longer verify at build time that our buffer size is
in the range that can be represented by the aggregation byte
limit field. So remove the test done by a BUILD_BUG_ON() call
in ipa_endpoint_validate_build(), and implement a comparable check
at the top of ipa_endpoint_data_valid().
Doing that makes ipa_endpoint_validate_build() contain a single
line BUILD_BUG_ON() call, so just remove that function and move
the remaining line into ipa_endpoint_data_valid().
One final note: the aggregation time limit value for IPA v4.5 needs
to be computed differently. That is handled in an upcoming patch.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-30 23:37:09 +00:00
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/* The aggregation byte limit defines the point at which an
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* aggregation window will close. It is programmed into the
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* IPA hardware as a number of KB. We don't use "hard byte
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* limit" aggregation, which means that we need to supply
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* enough space in a receive buffer to hold a complete MTU
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* plus normal skb overhead *after* that aggregation byte
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* limit has been crossed.
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*
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* This check ensures we don't define a receive buffer size
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* that would exceed what we can represent in the field that
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* is used to program its size.
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*/
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limit = aggr_byte_limit_max(ipa->version) * SZ_1K;
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limit += IPA_MTU + IPA_RX_BUFFER_OVERHEAD;
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if (limit < IPA_RX_BUFFER_SIZE) {
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dev_err(dev, "buffer size too big for aggregation (%u > %u)\n",
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IPA_RX_BUFFER_SIZE, limit);
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return false;
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}
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2020-03-06 04:28:24 +00:00
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/* Make sure needed endpoints have defined data */
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if (ipa_gsi_endpoint_data_empty(&data[IPA_ENDPOINT_AP_COMMAND_TX])) {
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dev_err(dev, "command TX endpoint not defined\n");
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return false;
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}
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if (ipa_gsi_endpoint_data_empty(&data[IPA_ENDPOINT_AP_LAN_RX])) {
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dev_err(dev, "LAN RX endpoint not defined\n");
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return false;
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}
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if (ipa_gsi_endpoint_data_empty(&data[IPA_ENDPOINT_AP_MODEM_TX])) {
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dev_err(dev, "AP->modem TX endpoint not defined\n");
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return false;
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}
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if (ipa_gsi_endpoint_data_empty(&data[IPA_ENDPOINT_AP_MODEM_RX])) {
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dev_err(dev, "AP<-modem RX endpoint not defined\n");
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return false;
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}
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for (name = 0; name < count; name++, dp++)
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if (!ipa_endpoint_data_valid_one(ipa, count, data, dp))
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return false;
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return true;
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}
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/* Allocate a transaction to use on a non-command endpoint */
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static struct gsi_trans *ipa_endpoint_trans_alloc(struct ipa_endpoint *endpoint,
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u32 tre_count)
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{
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struct gsi *gsi = &endpoint->ipa->gsi;
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u32 channel_id = endpoint->channel_id;
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enum dma_data_direction direction;
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direction = endpoint->toward_ipa ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
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return gsi_channel_trans_alloc(gsi, channel_id, tre_count, direction);
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}
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/* suspend_delay represents suspend for RX, delay for TX endpoints.
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* Note that suspend is not supported starting with IPA v4.0.
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*/
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2020-05-04 23:37:11 +00:00
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static bool
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2020-03-06 04:28:24 +00:00
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ipa_endpoint_init_ctrl(struct ipa_endpoint *endpoint, bool suspend_delay)
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{
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u32 offset = IPA_REG_ENDP_INIT_CTRL_N_OFFSET(endpoint->endpoint_id);
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struct ipa *ipa = endpoint->ipa;
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2020-05-04 23:37:11 +00:00
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bool state;
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2020-03-06 04:28:24 +00:00
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u32 mask;
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u32 val;
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2020-05-04 23:37:12 +00:00
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|
|
/* Suspend is not supported for IPA v4.0+. Delay doesn't work
|
|
|
|
* correctly on IPA v4.2.
|
|
|
|
*/
|
2021-07-26 17:40:10 +00:00
|
|
|
if (endpoint->toward_ipa)
|
|
|
|
WARN_ON(ipa->version == IPA_VERSION_4_2);
|
|
|
|
else
|
|
|
|
WARN_ON(ipa->version >= IPA_VERSION_4_0);
|
|
|
|
|
2020-03-06 04:28:24 +00:00
|
|
|
mask = endpoint->toward_ipa ? ENDP_DELAY_FMASK : ENDP_SUSPEND_FMASK;
|
|
|
|
|
|
|
|
val = ioread32(ipa->reg_virt + offset);
|
2020-05-04 23:37:11 +00:00
|
|
|
state = !!(val & mask);
|
2021-07-26 17:40:10 +00:00
|
|
|
|
|
|
|
/* Don't bother if it's already in the requested state */
|
2020-05-04 23:37:11 +00:00
|
|
|
if (suspend_delay != state) {
|
|
|
|
val ^= mask;
|
|
|
|
iowrite32(val, ipa->reg_virt + offset);
|
|
|
|
}
|
2020-03-06 04:28:24 +00:00
|
|
|
|
2020-05-04 23:37:11 +00:00
|
|
|
return state;
|
2020-03-06 04:28:24 +00:00
|
|
|
}
|
|
|
|
|
2020-05-04 23:37:12 +00:00
|
|
|
/* We currently don't care what the previous state was for delay mode */
|
|
|
|
static void
|
|
|
|
ipa_endpoint_program_delay(struct ipa_endpoint *endpoint, bool enable)
|
|
|
|
{
|
2021-07-26 17:40:10 +00:00
|
|
|
WARN_ON(!endpoint->toward_ipa);
|
2020-05-04 23:37:12 +00:00
|
|
|
|
2020-07-02 11:25:34 +00:00
|
|
|
/* Delay mode doesn't work properly for IPA v4.2 */
|
|
|
|
if (endpoint->ipa->version != IPA_VERSION_4_2)
|
|
|
|
(void)ipa_endpoint_init_ctrl(endpoint, enable);
|
2020-05-04 23:37:12 +00:00
|
|
|
}
|
|
|
|
|
2020-07-02 11:25:35 +00:00
|
|
|
static bool ipa_endpoint_aggr_active(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
u32 mask = BIT(endpoint->endpoint_id);
|
|
|
|
struct ipa *ipa = endpoint->ipa;
|
|
|
|
u32 offset;
|
|
|
|
u32 val;
|
|
|
|
|
2021-07-26 17:40:10 +00:00
|
|
|
WARN_ON(!(mask & ipa->available));
|
|
|
|
|
2020-07-02 11:25:35 +00:00
|
|
|
offset = ipa_reg_state_aggr_active_offset(ipa->version);
|
|
|
|
val = ioread32(ipa->reg_virt + offset);
|
|
|
|
|
|
|
|
return !!(val & mask);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ipa_endpoint_force_close(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
u32 mask = BIT(endpoint->endpoint_id);
|
|
|
|
struct ipa *ipa = endpoint->ipa;
|
|
|
|
|
2021-07-26 17:40:10 +00:00
|
|
|
WARN_ON(!(mask & ipa->available));
|
|
|
|
|
2020-07-02 11:25:35 +00:00
|
|
|
iowrite32(mask, ipa->reg_virt + IPA_REG_AGGR_FORCE_CLOSE_OFFSET);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* ipa_endpoint_suspend_aggr() - Emulate suspend interrupt
|
2020-07-13 12:24:18 +00:00
|
|
|
* @endpoint: Endpoint on which to emulate a suspend
|
2020-07-02 11:25:35 +00:00
|
|
|
*
|
|
|
|
* Emulate suspend IPA interrupt to unsuspend an endpoint suspended
|
|
|
|
* with an open aggregation frame. This is to work around a hardware
|
|
|
|
* issue in IPA version 3.5.1 where the suspend interrupt will not be
|
|
|
|
* generated when it should be.
|
|
|
|
*/
|
|
|
|
static void ipa_endpoint_suspend_aggr(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
struct ipa *ipa = endpoint->ipa;
|
|
|
|
|
|
|
|
if (!endpoint->data->aggregation)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* Nothing to do if the endpoint doesn't have aggregation open */
|
|
|
|
if (!ipa_endpoint_aggr_active(endpoint))
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* Force close aggregation */
|
|
|
|
ipa_endpoint_force_close(endpoint);
|
|
|
|
|
|
|
|
ipa_interrupt_simulate_suspend(ipa->interrupt);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Returns previous suspend state (true means suspend was enabled) */
|
2020-05-04 23:37:12 +00:00
|
|
|
static bool
|
|
|
|
ipa_endpoint_program_suspend(struct ipa_endpoint *endpoint, bool enable)
|
|
|
|
{
|
2020-07-02 11:25:35 +00:00
|
|
|
bool suspended;
|
|
|
|
|
2021-03-24 13:15:23 +00:00
|
|
|
if (endpoint->ipa->version >= IPA_VERSION_4_0)
|
2020-07-02 11:25:36 +00:00
|
|
|
return enable; /* For IPA v4.0+, no change made */
|
|
|
|
|
2021-07-26 17:40:10 +00:00
|
|
|
WARN_ON(endpoint->toward_ipa);
|
2020-05-04 23:37:12 +00:00
|
|
|
|
2020-07-02 11:25:35 +00:00
|
|
|
suspended = ipa_endpoint_init_ctrl(endpoint, enable);
|
|
|
|
|
|
|
|
/* A client suspended with an open aggregation frame will not
|
|
|
|
* generate a SUSPEND IPA interrupt. If enabling suspend, have
|
|
|
|
* ipa_endpoint_suspend_aggr() handle this.
|
|
|
|
*/
|
|
|
|
if (enable && !suspended)
|
|
|
|
ipa_endpoint_suspend_aggr(endpoint);
|
|
|
|
|
|
|
|
return suspended;
|
2020-05-04 23:37:12 +00:00
|
|
|
}
|
|
|
|
|
2020-03-06 04:28:24 +00:00
|
|
|
/* Enable or disable delay or suspend mode on all modem endpoints */
|
|
|
|
void ipa_endpoint_modem_pause_all(struct ipa *ipa, bool enable)
|
|
|
|
{
|
|
|
|
u32 endpoint_id;
|
|
|
|
|
2020-05-04 23:37:12 +00:00
|
|
|
/* DELAY mode doesn't work correctly on IPA v4.2 */
|
2020-03-06 04:28:24 +00:00
|
|
|
if (ipa->version == IPA_VERSION_4_2)
|
|
|
|
return;
|
|
|
|
|
|
|
|
for (endpoint_id = 0; endpoint_id < IPA_ENDPOINT_MAX; endpoint_id++) {
|
|
|
|
struct ipa_endpoint *endpoint = &ipa->endpoint[endpoint_id];
|
|
|
|
|
|
|
|
if (endpoint->ee_id != GSI_EE_MODEM)
|
|
|
|
continue;
|
|
|
|
|
2020-07-02 11:25:36 +00:00
|
|
|
/* Set TX delay mode or RX suspend mode */
|
2020-05-04 23:37:12 +00:00
|
|
|
if (endpoint->toward_ipa)
|
|
|
|
ipa_endpoint_program_delay(endpoint, enable);
|
2020-07-02 11:25:36 +00:00
|
|
|
else
|
2020-05-04 23:37:12 +00:00
|
|
|
(void)ipa_endpoint_program_suspend(endpoint, enable);
|
2020-03-06 04:28:24 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Reset all modem endpoints to use the default exception endpoint */
|
|
|
|
int ipa_endpoint_modem_exception_reset_all(struct ipa *ipa)
|
|
|
|
{
|
|
|
|
u32 initialized = ipa->initialized;
|
|
|
|
struct gsi_trans *trans;
|
|
|
|
u32 count;
|
|
|
|
|
|
|
|
/* We need one command per modem TX endpoint. We can get an upper
|
|
|
|
* bound on that by assuming all initialized endpoints are modem->IPA.
|
|
|
|
* That won't happen, and we could be more precise, but this is fine
|
2021-04-09 18:07:22 +00:00
|
|
|
* for now. End the transaction with commands to clear the pipeline.
|
2020-03-06 04:28:24 +00:00
|
|
|
*/
|
2021-01-26 18:56:58 +00:00
|
|
|
count = hweight32(initialized) + ipa_cmd_pipeline_clear_count();
|
2020-03-06 04:28:24 +00:00
|
|
|
trans = ipa_cmd_trans_alloc(ipa, count);
|
|
|
|
if (!trans) {
|
|
|
|
dev_err(&ipa->pdev->dev,
|
|
|
|
"no transaction to reset modem exception endpoints\n");
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (initialized) {
|
|
|
|
u32 endpoint_id = __ffs(initialized);
|
|
|
|
struct ipa_endpoint *endpoint;
|
|
|
|
u32 offset;
|
|
|
|
|
|
|
|
initialized ^= BIT(endpoint_id);
|
|
|
|
|
|
|
|
/* We only reset modem TX endpoints */
|
|
|
|
endpoint = &ipa->endpoint[endpoint_id];
|
|
|
|
if (!(endpoint->ee_id == GSI_EE_MODEM && endpoint->toward_ipa))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
offset = IPA_REG_ENDP_STATUS_N_OFFSET(endpoint_id);
|
|
|
|
|
|
|
|
/* Value written is 0, and all bits are updated. That
|
|
|
|
* means status is disabled on the endpoint, and as a
|
|
|
|
* result all other fields in the register are ignored.
|
|
|
|
*/
|
|
|
|
ipa_cmd_register_write_add(trans, offset, 0, ~0, false);
|
|
|
|
}
|
|
|
|
|
2021-01-26 18:56:58 +00:00
|
|
|
ipa_cmd_pipeline_clear_add(trans);
|
2020-03-06 04:28:24 +00:00
|
|
|
|
|
|
|
/* XXX This should have a 1 second timeout */
|
|
|
|
gsi_trans_commit_wait(trans);
|
|
|
|
|
2021-01-26 18:57:01 +00:00
|
|
|
ipa_cmd_pipeline_clear_wait(ipa);
|
|
|
|
|
2020-03-06 04:28:24 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ipa_endpoint_init_cfg(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
u32 offset = IPA_REG_ENDP_INIT_CFG_N_OFFSET(endpoint->endpoint_id);
|
2021-06-02 12:41:30 +00:00
|
|
|
enum ipa_cs_offload_en enabled;
|
2020-03-06 04:28:24 +00:00
|
|
|
u32 val = 0;
|
|
|
|
|
|
|
|
/* FRAG_OFFLOAD_EN is 0 */
|
|
|
|
if (endpoint->data->checksum) {
|
2021-06-02 12:41:30 +00:00
|
|
|
enum ipa_version version = endpoint->ipa->version;
|
|
|
|
|
2020-03-06 04:28:24 +00:00
|
|
|
if (endpoint->toward_ipa) {
|
|
|
|
u32 checksum_offset;
|
|
|
|
|
|
|
|
/* Checksum header offset is in 4-byte units */
|
|
|
|
checksum_offset = sizeof(struct rmnet_map_header);
|
|
|
|
checksum_offset /= sizeof(u32);
|
|
|
|
val |= u32_encode_bits(checksum_offset,
|
|
|
|
CS_METADATA_HDR_OFFSET_FMASK);
|
2021-06-02 12:41:30 +00:00
|
|
|
|
|
|
|
enabled = version < IPA_VERSION_4_5
|
|
|
|
? IPA_CS_OFFLOAD_UL
|
|
|
|
: IPA_CS_OFFLOAD_INLINE;
|
2020-03-06 04:28:24 +00:00
|
|
|
} else {
|
2021-06-02 12:41:30 +00:00
|
|
|
enabled = version < IPA_VERSION_4_5
|
|
|
|
? IPA_CS_OFFLOAD_DL
|
|
|
|
: IPA_CS_OFFLOAD_INLINE;
|
2020-03-06 04:28:24 +00:00
|
|
|
}
|
|
|
|
} else {
|
2021-06-02 12:41:30 +00:00
|
|
|
enabled = IPA_CS_OFFLOAD_NONE;
|
2020-03-06 04:28:24 +00:00
|
|
|
}
|
2021-06-02 12:41:30 +00:00
|
|
|
val |= u32_encode_bits(enabled, CS_OFFLOAD_EN_FMASK);
|
2020-03-06 04:28:24 +00:00
|
|
|
/* CS_GEN_QMB_MASTER_SEL is 0 */
|
|
|
|
|
|
|
|
iowrite32(val, endpoint->ipa->reg_virt + offset);
|
|
|
|
}
|
|
|
|
|
2021-03-24 13:15:25 +00:00
|
|
|
static void ipa_endpoint_init_nat(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
u32 offset;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
if (!endpoint->toward_ipa)
|
|
|
|
return;
|
|
|
|
|
|
|
|
offset = IPA_REG_ENDP_INIT_NAT_N_OFFSET(endpoint->endpoint_id);
|
|
|
|
val = u32_encode_bits(IPA_NAT_BYPASS, NAT_EN_FMASK);
|
|
|
|
|
|
|
|
iowrite32(val, endpoint->ipa->reg_virt + offset);
|
|
|
|
}
|
|
|
|
|
2021-06-02 12:41:30 +00:00
|
|
|
static u32
|
|
|
|
ipa_qmap_header_size(enum ipa_version version, struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
u32 header_size = sizeof(struct rmnet_map_header);
|
|
|
|
|
|
|
|
/* Without checksum offload, we just have the MAP header */
|
|
|
|
if (!endpoint->data->checksum)
|
|
|
|
return header_size;
|
|
|
|
|
|
|
|
if (version < IPA_VERSION_4_5) {
|
|
|
|
/* Checksum header inserted for AP TX endpoints only */
|
|
|
|
if (endpoint->toward_ipa)
|
|
|
|
header_size += sizeof(struct rmnet_map_ul_csum_header);
|
|
|
|
} else {
|
|
|
|
/* Checksum header is used in both directions */
|
|
|
|
header_size += sizeof(struct rmnet_map_v5_csum_header);
|
|
|
|
}
|
|
|
|
|
|
|
|
return header_size;
|
|
|
|
}
|
|
|
|
|
2020-06-11 19:48:30 +00:00
|
|
|
/**
|
2020-07-13 12:24:18 +00:00
|
|
|
* ipa_endpoint_init_hdr() - Initialize HDR endpoint configuration register
|
|
|
|
* @endpoint: Endpoint pointer
|
|
|
|
*
|
2020-06-11 19:48:30 +00:00
|
|
|
* We program QMAP endpoints so each packet received is preceded by a QMAP
|
|
|
|
* header structure. The QMAP header contains a 1-byte mux_id and 2-byte
|
|
|
|
* packet size field, and we have the IPA hardware populate both for each
|
|
|
|
* received packet. The header is configured (in the HDR_EXT register)
|
|
|
|
* to use big endian format.
|
|
|
|
*
|
|
|
|
* The packet size is written into the QMAP header's pkt_len field. That
|
|
|
|
* location is defined here using the HDR_OFST_PKT_SIZE field.
|
|
|
|
*
|
|
|
|
* The mux_id comes from a 4-byte metadata value supplied with each packet
|
|
|
|
* by the modem. It is *not* a QMAP header, but it does contain the mux_id
|
|
|
|
* value that we want, in its low-order byte. A bitmask defined in the
|
|
|
|
* endpoint's METADATA_MASK register defines which byte within the modem
|
|
|
|
* metadata contains the mux_id. And the OFST_METADATA field programmed
|
|
|
|
* here indicates where the extracted byte should be placed within the QMAP
|
|
|
|
* header.
|
|
|
|
*/
|
2020-03-06 04:28:24 +00:00
|
|
|
static void ipa_endpoint_init_hdr(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
u32 offset = IPA_REG_ENDP_INIT_HDR_N_OFFSET(endpoint->endpoint_id);
|
2020-11-25 20:45:19 +00:00
|
|
|
struct ipa *ipa = endpoint->ipa;
|
2020-03-06 04:28:24 +00:00
|
|
|
u32 val = 0;
|
|
|
|
|
|
|
|
if (endpoint->data->qmap) {
|
2020-11-25 20:45:19 +00:00
|
|
|
enum ipa_version version = ipa->version;
|
2021-06-02 12:41:30 +00:00
|
|
|
size_t header_size;
|
2020-03-06 04:28:24 +00:00
|
|
|
|
2021-06-02 12:41:30 +00:00
|
|
|
header_size = ipa_qmap_header_size(version, endpoint);
|
|
|
|
val = ipa_header_size_encoded(version, header_size);
|
2020-06-11 19:48:30 +00:00
|
|
|
|
2020-06-11 19:48:33 +00:00
|
|
|
/* Define how to fill fields in a received QMAP header */
|
2020-03-06 04:28:24 +00:00
|
|
|
if (!endpoint->toward_ipa) {
|
2020-11-25 20:45:19 +00:00
|
|
|
u32 offset; /* Field offset within header */
|
2020-06-11 19:48:30 +00:00
|
|
|
|
|
|
|
/* Where IPA will write the metadata value */
|
2020-11-25 20:45:19 +00:00
|
|
|
offset = offsetof(struct rmnet_map_header, mux_id);
|
|
|
|
val |= ipa_metadata_offset_encoded(version, offset);
|
2020-03-06 04:28:24 +00:00
|
|
|
|
2020-06-11 19:48:30 +00:00
|
|
|
/* Where IPA will write the length */
|
2020-11-25 20:45:19 +00:00
|
|
|
offset = offsetof(struct rmnet_map_header, pkt_len);
|
|
|
|
/* Upper bits are stored in HDR_EXT with IPA v4.5 */
|
2021-03-24 13:15:23 +00:00
|
|
|
if (version >= IPA_VERSION_4_5)
|
2020-11-25 20:45:19 +00:00
|
|
|
offset &= field_mask(HDR_OFST_PKT_SIZE_FMASK);
|
|
|
|
|
2020-03-06 04:28:24 +00:00
|
|
|
val |= HDR_OFST_PKT_SIZE_VALID_FMASK;
|
2020-11-25 20:45:19 +00:00
|
|
|
val |= u32_encode_bits(offset, HDR_OFST_PKT_SIZE_FMASK);
|
2020-03-06 04:28:24 +00:00
|
|
|
}
|
2020-06-11 19:48:30 +00:00
|
|
|
/* For QMAP TX, metadata offset is 0 (modem assumes this) */
|
|
|
|
val |= HDR_OFST_METADATA_VALID_FMASK;
|
|
|
|
|
|
|
|
/* HDR_ADDITIONAL_CONST_LEN is 0; (RX only) */
|
2020-03-06 04:28:24 +00:00
|
|
|
/* HDR_A5_MUX is 0 */
|
|
|
|
/* HDR_LEN_INC_DEAGG_HDR is 0 */
|
2020-11-25 20:45:20 +00:00
|
|
|
/* HDR_METADATA_REG_VALID is 0 (TX only, version < v4.5) */
|
2020-03-06 04:28:24 +00:00
|
|
|
}
|
|
|
|
|
2020-11-25 20:45:19 +00:00
|
|
|
iowrite32(val, ipa->reg_virt + offset);
|
2020-03-06 04:28:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
u32 offset = IPA_REG_ENDP_INIT_HDR_EXT_N_OFFSET(endpoint->endpoint_id);
|
|
|
|
u32 pad_align = endpoint->data->rx.pad_align;
|
2020-11-25 20:45:19 +00:00
|
|
|
struct ipa *ipa = endpoint->ipa;
|
2020-03-06 04:28:24 +00:00
|
|
|
u32 val = 0;
|
|
|
|
|
|
|
|
val |= HDR_ENDIANNESS_FMASK; /* big endian */
|
2020-06-11 19:48:33 +00:00
|
|
|
|
|
|
|
/* A QMAP header contains a 6 bit pad field at offset 0. The RMNet
|
|
|
|
* driver assumes this field is meaningful in packets it receives,
|
|
|
|
* and assumes the header's payload length includes that padding.
|
|
|
|
* The RMNet driver does *not* pad packets it sends, however, so
|
|
|
|
* the pad field (although 0) should be ignored.
|
|
|
|
*/
|
|
|
|
if (endpoint->data->qmap && !endpoint->toward_ipa) {
|
|
|
|
val |= HDR_TOTAL_LEN_OR_PAD_VALID_FMASK;
|
|
|
|
/* HDR_TOTAL_LEN_OR_PAD is 0 (pad, not total_len) */
|
|
|
|
val |= HDR_PAYLOAD_LEN_INC_PADDING_FMASK;
|
|
|
|
/* HDR_TOTAL_LEN_OR_PAD_OFFSET is 0 */
|
|
|
|
}
|
|
|
|
|
2020-03-06 04:28:24 +00:00
|
|
|
/* HDR_PAYLOAD_LEN_INC_PADDING is 0 */
|
|
|
|
if (!endpoint->toward_ipa)
|
|
|
|
val |= u32_encode_bits(pad_align, HDR_PAD_TO_ALIGNMENT_FMASK);
|
|
|
|
|
2020-11-25 20:45:19 +00:00
|
|
|
/* IPA v4.5 adds some most-significant bits to a few fields,
|
|
|
|
* two of which are defined in the HDR (not HDR_EXT) register.
|
|
|
|
*/
|
2021-03-24 13:15:23 +00:00
|
|
|
if (ipa->version >= IPA_VERSION_4_5) {
|
2020-11-25 20:45:19 +00:00
|
|
|
/* HDR_TOTAL_LEN_OR_PAD_OFFSET is 0, so MSB is 0 */
|
|
|
|
if (endpoint->data->qmap && !endpoint->toward_ipa) {
|
|
|
|
u32 offset;
|
|
|
|
|
|
|
|
offset = offsetof(struct rmnet_map_header, pkt_len);
|
|
|
|
offset >>= hweight32(HDR_OFST_PKT_SIZE_FMASK);
|
|
|
|
val |= u32_encode_bits(offset,
|
|
|
|
HDR_OFST_PKT_SIZE_MSB_FMASK);
|
|
|
|
/* HDR_ADDITIONAL_CONST_LEN is 0 so MSB is 0 */
|
|
|
|
}
|
|
|
|
}
|
|
|
|
iowrite32(val, ipa->reg_virt + offset);
|
2020-03-06 04:28:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void ipa_endpoint_init_hdr_metadata_mask(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
u32 endpoint_id = endpoint->endpoint_id;
|
|
|
|
u32 val = 0;
|
|
|
|
u32 offset;
|
|
|
|
|
2020-07-02 11:25:37 +00:00
|
|
|
if (endpoint->toward_ipa)
|
|
|
|
return; /* Register not valid for TX endpoints */
|
|
|
|
|
2020-03-06 04:28:24 +00:00
|
|
|
offset = IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(endpoint_id);
|
|
|
|
|
2020-06-11 19:48:30 +00:00
|
|
|
/* Note that HDR_ENDIANNESS indicates big endian header fields */
|
2020-06-30 13:33:01 +00:00
|
|
|
if (endpoint->data->qmap)
|
2021-02-01 23:26:07 +00:00
|
|
|
val = (__force u32)cpu_to_be32(IPA_ENDPOINT_QMAP_METADATA_MASK);
|
2020-03-06 04:28:24 +00:00
|
|
|
|
|
|
|
iowrite32(val, endpoint->ipa->reg_virt + offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ipa_endpoint_init_mode(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
u32 offset = IPA_REG_ENDP_INIT_MODE_N_OFFSET(endpoint->endpoint_id);
|
|
|
|
u32 val;
|
|
|
|
|
2020-07-02 11:25:37 +00:00
|
|
|
if (!endpoint->toward_ipa)
|
|
|
|
return; /* Register not valid for RX endpoints */
|
|
|
|
|
2020-06-30 13:33:02 +00:00
|
|
|
if (endpoint->data->dma_mode) {
|
2020-03-06 04:28:24 +00:00
|
|
|
enum ipa_endpoint_name name = endpoint->data->dma_endpoint;
|
|
|
|
u32 dma_endpoint_id;
|
|
|
|
|
|
|
|
dma_endpoint_id = endpoint->ipa->name_map[name]->endpoint_id;
|
|
|
|
|
|
|
|
val = u32_encode_bits(IPA_DMA, MODE_FMASK);
|
|
|
|
val |= u32_encode_bits(dma_endpoint_id, DEST_PIPE_INDEX_FMASK);
|
|
|
|
} else {
|
|
|
|
val = u32_encode_bits(IPA_BASIC, MODE_FMASK);
|
|
|
|
}
|
2020-06-30 13:33:02 +00:00
|
|
|
/* All other bits unspecified (and 0) */
|
2020-03-06 04:28:24 +00:00
|
|
|
|
|
|
|
iowrite32(val, endpoint->ipa->reg_virt + offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Compute the aggregation size value to use for a given buffer size */
|
|
|
|
static u32 ipa_aggr_size_kb(u32 rx_buffer_size)
|
|
|
|
{
|
|
|
|
/* We don't use "hard byte limit" aggregation, so we define the
|
|
|
|
* aggregation limit such that our buffer has enough space *after*
|
|
|
|
* that limit to receive a full MTU of data, plus overhead.
|
|
|
|
*/
|
|
|
|
rx_buffer_size -= IPA_MTU + IPA_RX_BUFFER_OVERHEAD;
|
|
|
|
|
|
|
|
return rx_buffer_size / SZ_1K;
|
|
|
|
}
|
|
|
|
|
net: ipa: update IPA aggregation registers for IPA v4.5
IPA v4.5 significantly changes the format of the configuration
register used for endpoint aggregation. The AGGR_BYTE_LIMIT field
is now larger, and the positions of other fields are shifted. This
complicates the way we have to access this register because functions
like u32_encode_bits() require their field mask argument to be constant.
A further complication is that we want to know the maximum value
representable by at least one of these fields, and that too requires
a constant field mask.
This patch adds support for IPA v4.5 endpoint aggregation registers
in a way that continues to support "legacy" IPA hardware. It does
so in a way that keeps field masks constant.
First, for each variable field mask, we define an inline function
whose return value is either the legacy value or the IPA v4.5 value.
Second, we define functions for these fields that encode a value
to use in each field based on the IPA version (this approach is
already used elsewhere). The field mask provided is supplied by
the function mentioned above.
Finally, for the aggregation byte limit fields where we want to
know the maximum representable value, we define a function that
returns that maximum, computed from the appropriate field mask.
We can no longer verify at build time that our buffer size is
in the range that can be represented by the aggregation byte
limit field. So remove the test done by a BUILD_BUG_ON() call
in ipa_endpoint_validate_build(), and implement a comparable check
at the top of ipa_endpoint_data_valid().
Doing that makes ipa_endpoint_validate_build() contain a single
line BUILD_BUG_ON() call, so just remove that function and move
the remaining line into ipa_endpoint_data_valid().
One final note: the aggregation time limit value for IPA v4.5 needs
to be computed differently. That is handled in an upcoming patch.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-30 23:37:09 +00:00
|
|
|
/* Encoded values for AGGR endpoint register fields */
|
|
|
|
static u32 aggr_byte_limit_encoded(enum ipa_version version, u32 limit)
|
|
|
|
{
|
|
|
|
if (version < IPA_VERSION_4_5)
|
|
|
|
return u32_encode_bits(limit, aggr_byte_limit_fmask(true));
|
|
|
|
|
|
|
|
return u32_encode_bits(limit, aggr_byte_limit_fmask(false));
|
|
|
|
}
|
|
|
|
|
2020-11-30 23:37:11 +00:00
|
|
|
/* Encode the aggregation timer limit (microseconds) based on IPA version */
|
net: ipa: update IPA aggregation registers for IPA v4.5
IPA v4.5 significantly changes the format of the configuration
register used for endpoint aggregation. The AGGR_BYTE_LIMIT field
is now larger, and the positions of other fields are shifted. This
complicates the way we have to access this register because functions
like u32_encode_bits() require their field mask argument to be constant.
A further complication is that we want to know the maximum value
representable by at least one of these fields, and that too requires
a constant field mask.
This patch adds support for IPA v4.5 endpoint aggregation registers
in a way that continues to support "legacy" IPA hardware. It does
so in a way that keeps field masks constant.
First, for each variable field mask, we define an inline function
whose return value is either the legacy value or the IPA v4.5 value.
Second, we define functions for these fields that encode a value
to use in each field based on the IPA version (this approach is
already used elsewhere). The field mask provided is supplied by
the function mentioned above.
Finally, for the aggregation byte limit fields where we want to
know the maximum representable value, we define a function that
returns that maximum, computed from the appropriate field mask.
We can no longer verify at build time that our buffer size is
in the range that can be represented by the aggregation byte
limit field. So remove the test done by a BUILD_BUG_ON() call
in ipa_endpoint_validate_build(), and implement a comparable check
at the top of ipa_endpoint_data_valid().
Doing that makes ipa_endpoint_validate_build() contain a single
line BUILD_BUG_ON() call, so just remove that function and move
the remaining line into ipa_endpoint_data_valid().
One final note: the aggregation time limit value for IPA v4.5 needs
to be computed differently. That is handled in an upcoming patch.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-30 23:37:09 +00:00
|
|
|
static u32 aggr_time_limit_encoded(enum ipa_version version, u32 limit)
|
|
|
|
{
|
2020-11-30 23:37:11 +00:00
|
|
|
u32 gran_sel;
|
|
|
|
u32 fmask;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
if (version < IPA_VERSION_4_5) {
|
|
|
|
/* We set aggregation granularity in ipa_hardware_config() */
|
|
|
|
limit = DIV_ROUND_CLOSEST(limit, IPA_AGGR_GRANULARITY);
|
|
|
|
|
net: ipa: update IPA aggregation registers for IPA v4.5
IPA v4.5 significantly changes the format of the configuration
register used for endpoint aggregation. The AGGR_BYTE_LIMIT field
is now larger, and the positions of other fields are shifted. This
complicates the way we have to access this register because functions
like u32_encode_bits() require their field mask argument to be constant.
A further complication is that we want to know the maximum value
representable by at least one of these fields, and that too requires
a constant field mask.
This patch adds support for IPA v4.5 endpoint aggregation registers
in a way that continues to support "legacy" IPA hardware. It does
so in a way that keeps field masks constant.
First, for each variable field mask, we define an inline function
whose return value is either the legacy value or the IPA v4.5 value.
Second, we define functions for these fields that encode a value
to use in each field based on the IPA version (this approach is
already used elsewhere). The field mask provided is supplied by
the function mentioned above.
Finally, for the aggregation byte limit fields where we want to
know the maximum representable value, we define a function that
returns that maximum, computed from the appropriate field mask.
We can no longer verify at build time that our buffer size is
in the range that can be represented by the aggregation byte
limit field. So remove the test done by a BUILD_BUG_ON() call
in ipa_endpoint_validate_build(), and implement a comparable check
at the top of ipa_endpoint_data_valid().
Doing that makes ipa_endpoint_validate_build() contain a single
line BUILD_BUG_ON() call, so just remove that function and move
the remaining line into ipa_endpoint_data_valid().
One final note: the aggregation time limit value for IPA v4.5 needs
to be computed differently. That is handled in an upcoming patch.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-30 23:37:09 +00:00
|
|
|
return u32_encode_bits(limit, aggr_time_limit_fmask(true));
|
2020-11-30 23:37:11 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* IPA v4.5 expresses the time limit using Qtime. The AP has
|
|
|
|
* pulse generators 0 and 1 available, which were configured
|
|
|
|
* in ipa_qtime_config() to have granularity 100 usec and
|
|
|
|
* 1 msec, respectively. Use pulse generator 0 if possible,
|
|
|
|
* otherwise fall back to pulse generator 1.
|
|
|
|
*/
|
|
|
|
fmask = aggr_time_limit_fmask(false);
|
|
|
|
val = DIV_ROUND_CLOSEST(limit, 100);
|
|
|
|
if (val > field_max(fmask)) {
|
|
|
|
/* Have to use pulse generator 1 (millisecond granularity) */
|
|
|
|
gran_sel = AGGR_GRAN_SEL_FMASK;
|
|
|
|
val = DIV_ROUND_CLOSEST(limit, 1000);
|
|
|
|
} else {
|
|
|
|
/* We can use pulse generator 0 (100 usec granularity) */
|
|
|
|
gran_sel = 0;
|
|
|
|
}
|
net: ipa: update IPA aggregation registers for IPA v4.5
IPA v4.5 significantly changes the format of the configuration
register used for endpoint aggregation. The AGGR_BYTE_LIMIT field
is now larger, and the positions of other fields are shifted. This
complicates the way we have to access this register because functions
like u32_encode_bits() require their field mask argument to be constant.
A further complication is that we want to know the maximum value
representable by at least one of these fields, and that too requires
a constant field mask.
This patch adds support for IPA v4.5 endpoint aggregation registers
in a way that continues to support "legacy" IPA hardware. It does
so in a way that keeps field masks constant.
First, for each variable field mask, we define an inline function
whose return value is either the legacy value or the IPA v4.5 value.
Second, we define functions for these fields that encode a value
to use in each field based on the IPA version (this approach is
already used elsewhere). The field mask provided is supplied by
the function mentioned above.
Finally, for the aggregation byte limit fields where we want to
know the maximum representable value, we define a function that
returns that maximum, computed from the appropriate field mask.
We can no longer verify at build time that our buffer size is
in the range that can be represented by the aggregation byte
limit field. So remove the test done by a BUILD_BUG_ON() call
in ipa_endpoint_validate_build(), and implement a comparable check
at the top of ipa_endpoint_data_valid().
Doing that makes ipa_endpoint_validate_build() contain a single
line BUILD_BUG_ON() call, so just remove that function and move
the remaining line into ipa_endpoint_data_valid().
One final note: the aggregation time limit value for IPA v4.5 needs
to be computed differently. That is handled in an upcoming patch.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-30 23:37:09 +00:00
|
|
|
|
2020-11-30 23:37:11 +00:00
|
|
|
return gran_sel | u32_encode_bits(val, fmask);
|
net: ipa: update IPA aggregation registers for IPA v4.5
IPA v4.5 significantly changes the format of the configuration
register used for endpoint aggregation. The AGGR_BYTE_LIMIT field
is now larger, and the positions of other fields are shifted. This
complicates the way we have to access this register because functions
like u32_encode_bits() require their field mask argument to be constant.
A further complication is that we want to know the maximum value
representable by at least one of these fields, and that too requires
a constant field mask.
This patch adds support for IPA v4.5 endpoint aggregation registers
in a way that continues to support "legacy" IPA hardware. It does
so in a way that keeps field masks constant.
First, for each variable field mask, we define an inline function
whose return value is either the legacy value or the IPA v4.5 value.
Second, we define functions for these fields that encode a value
to use in each field based on the IPA version (this approach is
already used elsewhere). The field mask provided is supplied by
the function mentioned above.
Finally, for the aggregation byte limit fields where we want to
know the maximum representable value, we define a function that
returns that maximum, computed from the appropriate field mask.
We can no longer verify at build time that our buffer size is
in the range that can be represented by the aggregation byte
limit field. So remove the test done by a BUILD_BUG_ON() call
in ipa_endpoint_validate_build(), and implement a comparable check
at the top of ipa_endpoint_data_valid().
Doing that makes ipa_endpoint_validate_build() contain a single
line BUILD_BUG_ON() call, so just remove that function and move
the remaining line into ipa_endpoint_data_valid().
One final note: the aggregation time limit value for IPA v4.5 needs
to be computed differently. That is handled in an upcoming patch.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-30 23:37:09 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static u32 aggr_sw_eof_active_encoded(enum ipa_version version, bool enabled)
|
|
|
|
{
|
|
|
|
u32 val = enabled ? 1 : 0;
|
|
|
|
|
|
|
|
if (version < IPA_VERSION_4_5)
|
|
|
|
return u32_encode_bits(val, aggr_sw_eof_active_fmask(true));
|
|
|
|
|
|
|
|
return u32_encode_bits(val, aggr_sw_eof_active_fmask(false));
|
|
|
|
}
|
|
|
|
|
2020-03-06 04:28:24 +00:00
|
|
|
static void ipa_endpoint_init_aggr(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
u32 offset = IPA_REG_ENDP_INIT_AGGR_N_OFFSET(endpoint->endpoint_id);
|
net: ipa: update IPA aggregation registers for IPA v4.5
IPA v4.5 significantly changes the format of the configuration
register used for endpoint aggregation. The AGGR_BYTE_LIMIT field
is now larger, and the positions of other fields are shifted. This
complicates the way we have to access this register because functions
like u32_encode_bits() require their field mask argument to be constant.
A further complication is that we want to know the maximum value
representable by at least one of these fields, and that too requires
a constant field mask.
This patch adds support for IPA v4.5 endpoint aggregation registers
in a way that continues to support "legacy" IPA hardware. It does
so in a way that keeps field masks constant.
First, for each variable field mask, we define an inline function
whose return value is either the legacy value or the IPA v4.5 value.
Second, we define functions for these fields that encode a value
to use in each field based on the IPA version (this approach is
already used elsewhere). The field mask provided is supplied by
the function mentioned above.
Finally, for the aggregation byte limit fields where we want to
know the maximum representable value, we define a function that
returns that maximum, computed from the appropriate field mask.
We can no longer verify at build time that our buffer size is
in the range that can be represented by the aggregation byte
limit field. So remove the test done by a BUILD_BUG_ON() call
in ipa_endpoint_validate_build(), and implement a comparable check
at the top of ipa_endpoint_data_valid().
Doing that makes ipa_endpoint_validate_build() contain a single
line BUILD_BUG_ON() call, so just remove that function and move
the remaining line into ipa_endpoint_data_valid().
One final note: the aggregation time limit value for IPA v4.5 needs
to be computed differently. That is handled in an upcoming patch.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-30 23:37:09 +00:00
|
|
|
enum ipa_version version = endpoint->ipa->version;
|
2020-03-06 04:28:24 +00:00
|
|
|
u32 val = 0;
|
|
|
|
|
|
|
|
if (endpoint->data->aggregation) {
|
|
|
|
if (!endpoint->toward_ipa) {
|
net: ipa: update IPA aggregation registers for IPA v4.5
IPA v4.5 significantly changes the format of the configuration
register used for endpoint aggregation. The AGGR_BYTE_LIMIT field
is now larger, and the positions of other fields are shifted. This
complicates the way we have to access this register because functions
like u32_encode_bits() require their field mask argument to be constant.
A further complication is that we want to know the maximum value
representable by at least one of these fields, and that too requires
a constant field mask.
This patch adds support for IPA v4.5 endpoint aggregation registers
in a way that continues to support "legacy" IPA hardware. It does
so in a way that keeps field masks constant.
First, for each variable field mask, we define an inline function
whose return value is either the legacy value or the IPA v4.5 value.
Second, we define functions for these fields that encode a value
to use in each field based on the IPA version (this approach is
already used elsewhere). The field mask provided is supplied by
the function mentioned above.
Finally, for the aggregation byte limit fields where we want to
know the maximum representable value, we define a function that
returns that maximum, computed from the appropriate field mask.
We can no longer verify at build time that our buffer size is
in the range that can be represented by the aggregation byte
limit field. So remove the test done by a BUILD_BUG_ON() call
in ipa_endpoint_validate_build(), and implement a comparable check
at the top of ipa_endpoint_data_valid().
Doing that makes ipa_endpoint_validate_build() contain a single
line BUILD_BUG_ON() call, so just remove that function and move
the remaining line into ipa_endpoint_data_valid().
One final note: the aggregation time limit value for IPA v4.5 needs
to be computed differently. That is handled in an upcoming patch.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-30 23:37:09 +00:00
|
|
|
bool close_eof;
|
2020-03-06 04:28:24 +00:00
|
|
|
u32 limit;
|
|
|
|
|
|
|
|
val |= u32_encode_bits(IPA_ENABLE_AGGR, AGGR_EN_FMASK);
|
|
|
|
val |= u32_encode_bits(IPA_GENERIC, AGGR_TYPE_FMASK);
|
2020-06-29 21:55:23 +00:00
|
|
|
|
|
|
|
limit = ipa_aggr_size_kb(IPA_RX_BUFFER_SIZE);
|
net: ipa: update IPA aggregation registers for IPA v4.5
IPA v4.5 significantly changes the format of the configuration
register used for endpoint aggregation. The AGGR_BYTE_LIMIT field
is now larger, and the positions of other fields are shifted. This
complicates the way we have to access this register because functions
like u32_encode_bits() require their field mask argument to be constant.
A further complication is that we want to know the maximum value
representable by at least one of these fields, and that too requires
a constant field mask.
This patch adds support for IPA v4.5 endpoint aggregation registers
in a way that continues to support "legacy" IPA hardware. It does
so in a way that keeps field masks constant.
First, for each variable field mask, we define an inline function
whose return value is either the legacy value or the IPA v4.5 value.
Second, we define functions for these fields that encode a value
to use in each field based on the IPA version (this approach is
already used elsewhere). The field mask provided is supplied by
the function mentioned above.
Finally, for the aggregation byte limit fields where we want to
know the maximum representable value, we define a function that
returns that maximum, computed from the appropriate field mask.
We can no longer verify at build time that our buffer size is
in the range that can be represented by the aggregation byte
limit field. So remove the test done by a BUILD_BUG_ON() call
in ipa_endpoint_validate_build(), and implement a comparable check
at the top of ipa_endpoint_data_valid().
Doing that makes ipa_endpoint_validate_build() contain a single
line BUILD_BUG_ON() call, so just remove that function and move
the remaining line into ipa_endpoint_data_valid().
One final note: the aggregation time limit value for IPA v4.5 needs
to be computed differently. That is handled in an upcoming patch.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-30 23:37:09 +00:00
|
|
|
val |= aggr_byte_limit_encoded(version, limit);
|
2020-06-29 21:55:22 +00:00
|
|
|
|
net: ipa: update IPA aggregation registers for IPA v4.5
IPA v4.5 significantly changes the format of the configuration
register used for endpoint aggregation. The AGGR_BYTE_LIMIT field
is now larger, and the positions of other fields are shifted. This
complicates the way we have to access this register because functions
like u32_encode_bits() require their field mask argument to be constant.
A further complication is that we want to know the maximum value
representable by at least one of these fields, and that too requires
a constant field mask.
This patch adds support for IPA v4.5 endpoint aggregation registers
in a way that continues to support "legacy" IPA hardware. It does
so in a way that keeps field masks constant.
First, for each variable field mask, we define an inline function
whose return value is either the legacy value or the IPA v4.5 value.
Second, we define functions for these fields that encode a value
to use in each field based on the IPA version (this approach is
already used elsewhere). The field mask provided is supplied by
the function mentioned above.
Finally, for the aggregation byte limit fields where we want to
know the maximum representable value, we define a function that
returns that maximum, computed from the appropriate field mask.
We can no longer verify at build time that our buffer size is
in the range that can be represented by the aggregation byte
limit field. So remove the test done by a BUILD_BUG_ON() call
in ipa_endpoint_validate_build(), and implement a comparable check
at the top of ipa_endpoint_data_valid().
Doing that makes ipa_endpoint_validate_build() contain a single
line BUILD_BUG_ON() call, so just remove that function and move
the remaining line into ipa_endpoint_data_valid().
One final note: the aggregation time limit value for IPA v4.5 needs
to be computed differently. That is handled in an upcoming patch.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-30 23:37:09 +00:00
|
|
|
limit = IPA_AGGR_TIME_LIMIT;
|
|
|
|
val |= aggr_time_limit_encoded(version, limit);
|
2020-06-29 21:55:22 +00:00
|
|
|
|
2020-06-29 21:55:23 +00:00
|
|
|
/* AGGR_PKT_LIMIT is 0 (unlimited) */
|
|
|
|
|
net: ipa: update IPA aggregation registers for IPA v4.5
IPA v4.5 significantly changes the format of the configuration
register used for endpoint aggregation. The AGGR_BYTE_LIMIT field
is now larger, and the positions of other fields are shifted. This
complicates the way we have to access this register because functions
like u32_encode_bits() require their field mask argument to be constant.
A further complication is that we want to know the maximum value
representable by at least one of these fields, and that too requires
a constant field mask.
This patch adds support for IPA v4.5 endpoint aggregation registers
in a way that continues to support "legacy" IPA hardware. It does
so in a way that keeps field masks constant.
First, for each variable field mask, we define an inline function
whose return value is either the legacy value or the IPA v4.5 value.
Second, we define functions for these fields that encode a value
to use in each field based on the IPA version (this approach is
already used elsewhere). The field mask provided is supplied by
the function mentioned above.
Finally, for the aggregation byte limit fields where we want to
know the maximum representable value, we define a function that
returns that maximum, computed from the appropriate field mask.
We can no longer verify at build time that our buffer size is
in the range that can be represented by the aggregation byte
limit field. So remove the test done by a BUILD_BUG_ON() call
in ipa_endpoint_validate_build(), and implement a comparable check
at the top of ipa_endpoint_data_valid().
Doing that makes ipa_endpoint_validate_build() contain a single
line BUILD_BUG_ON() call, so just remove that function and move
the remaining line into ipa_endpoint_data_valid().
One final note: the aggregation time limit value for IPA v4.5 needs
to be computed differently. That is handled in an upcoming patch.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-30 23:37:09 +00:00
|
|
|
close_eof = endpoint->data->rx.aggr_close_eof;
|
|
|
|
val |= aggr_sw_eof_active_encoded(version, close_eof);
|
|
|
|
|
2020-03-06 04:28:24 +00:00
|
|
|
/* AGGR_HARD_BYTE_LIMIT_ENABLE is 0 */
|
|
|
|
} else {
|
|
|
|
val |= u32_encode_bits(IPA_ENABLE_DEAGGR,
|
|
|
|
AGGR_EN_FMASK);
|
|
|
|
val |= u32_encode_bits(IPA_QCMAP, AGGR_TYPE_FMASK);
|
|
|
|
/* other fields ignored */
|
|
|
|
}
|
|
|
|
/* AGGR_FORCE_CLOSE is 0 */
|
2020-11-25 20:45:20 +00:00
|
|
|
/* AGGR_GRAN_SEL is 0 for IPA v4.5 */
|
2020-03-06 04:28:24 +00:00
|
|
|
} else {
|
|
|
|
val |= u32_encode_bits(IPA_BYPASS_AGGR, AGGR_EN_FMASK);
|
|
|
|
/* other fields ignored */
|
|
|
|
}
|
|
|
|
|
|
|
|
iowrite32(val, endpoint->ipa->reg_virt + offset);
|
|
|
|
}
|
|
|
|
|
2020-11-30 23:37:12 +00:00
|
|
|
/* Return the Qtime-based head-of-line blocking timer value that
|
|
|
|
* represents the given number of microseconds. The result
|
|
|
|
* includes both the timer value and the selected timer granularity.
|
net: ipa: fix HOLB timer calculation
For IPA v4.2, the exact interpretation of the register that defines
the timeout for avoiding head-of-line blocking was a little unclear.
We're only assigning a 0 timeout to it right now, so that wasn't
very important. But now that I know how it's supposed to work, I'm
fixing it.
The register represents a tick counter, where each tick is equal to
128 IPA core clock cycles. For IPA v3.5.1, the register contains
a simple counter value. But for IPA v4.2, the register contains two
fields, base and scale, which approximate the tick counter as:
ticks = base << scale
The base and scale values to use for a given tick count are computed
using clever bit operations, and measures are taken to make the
resulting time period as close as possible to that requested.
There's no need for ipa_endpoint_init_hol_block_timer() to return
an error, so change its return type to void.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-03 21:23:35 +00:00
|
|
|
*/
|
2020-11-30 23:37:12 +00:00
|
|
|
static u32 hol_block_timer_qtime_val(struct ipa *ipa, u32 microseconds)
|
|
|
|
{
|
|
|
|
u32 gran_sel;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
/* IPA v4.5 expresses time limits using Qtime. The AP has
|
|
|
|
* pulse generators 0 and 1 available, which were configured
|
|
|
|
* in ipa_qtime_config() to have granularity 100 usec and
|
|
|
|
* 1 msec, respectively. Use pulse generator 0 if possible,
|
|
|
|
* otherwise fall back to pulse generator 1.
|
|
|
|
*/
|
|
|
|
val = DIV_ROUND_CLOSEST(microseconds, 100);
|
|
|
|
if (val > field_max(TIME_LIMIT_FMASK)) {
|
|
|
|
/* Have to use pulse generator 1 (millisecond granularity) */
|
|
|
|
gran_sel = GRAN_SEL_FMASK;
|
|
|
|
val = DIV_ROUND_CLOSEST(microseconds, 1000);
|
|
|
|
} else {
|
|
|
|
/* We can use pulse generator 0 (100 usec granularity) */
|
|
|
|
gran_sel = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return gran_sel | u32_encode_bits(val, TIME_LIMIT_FMASK);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* The head-of-line blocking timer is defined as a tick count. For
|
|
|
|
* IPA version 4.5 the tick count is based on the Qtimer, which is
|
|
|
|
* derived from the 19.2 MHz SoC XO clock. For older IPA versions
|
|
|
|
* each tick represents 128 cycles of the IPA core clock.
|
|
|
|
*
|
|
|
|
* Return the encoded value that should be written to that register
|
|
|
|
* that represents the timeout period provided. For IPA v4.2 this
|
|
|
|
* encodes a base and scale value, while for earlier versions the
|
|
|
|
* value is a simple tick count.
|
|
|
|
*/
|
|
|
|
static u32 hol_block_timer_val(struct ipa *ipa, u32 microseconds)
|
2020-03-06 04:28:24 +00:00
|
|
|
{
|
net: ipa: fix HOLB timer calculation
For IPA v4.2, the exact interpretation of the register that defines
the timeout for avoiding head-of-line blocking was a little unclear.
We're only assigning a 0 timeout to it right now, so that wasn't
very important. But now that I know how it's supposed to work, I'm
fixing it.
The register represents a tick counter, where each tick is equal to
128 IPA core clock cycles. For IPA v3.5.1, the register contains
a simple counter value. But for IPA v4.2, the register contains two
fields, base and scale, which approximate the tick counter as:
ticks = base << scale
The base and scale values to use for a given tick count are computed
using clever bit operations, and measures are taken to make the
resulting time period as close as possible to that requested.
There's no need for ipa_endpoint_init_hol_block_timer() to return
an error, so change its return type to void.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-03 21:23:35 +00:00
|
|
|
u32 width;
|
2020-03-06 04:28:24 +00:00
|
|
|
u32 scale;
|
net: ipa: fix HOLB timer calculation
For IPA v4.2, the exact interpretation of the register that defines
the timeout for avoiding head-of-line blocking was a little unclear.
We're only assigning a 0 timeout to it right now, so that wasn't
very important. But now that I know how it's supposed to work, I'm
fixing it.
The register represents a tick counter, where each tick is equal to
128 IPA core clock cycles. For IPA v3.5.1, the register contains
a simple counter value. But for IPA v4.2, the register contains two
fields, base and scale, which approximate the tick counter as:
ticks = base << scale
The base and scale values to use for a given tick count are computed
using clever bit operations, and measures are taken to make the
resulting time period as close as possible to that requested.
There's no need for ipa_endpoint_init_hol_block_timer() to return
an error, so change its return type to void.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-03 21:23:35 +00:00
|
|
|
u64 ticks;
|
|
|
|
u64 rate;
|
|
|
|
u32 high;
|
2020-03-06 04:28:24 +00:00
|
|
|
u32 val;
|
|
|
|
|
|
|
|
if (!microseconds)
|
net: ipa: fix HOLB timer calculation
For IPA v4.2, the exact interpretation of the register that defines
the timeout for avoiding head-of-line blocking was a little unclear.
We're only assigning a 0 timeout to it right now, so that wasn't
very important. But now that I know how it's supposed to work, I'm
fixing it.
The register represents a tick counter, where each tick is equal to
128 IPA core clock cycles. For IPA v3.5.1, the register contains
a simple counter value. But for IPA v4.2, the register contains two
fields, base and scale, which approximate the tick counter as:
ticks = base << scale
The base and scale values to use for a given tick count are computed
using clever bit operations, and measures are taken to make the
resulting time period as close as possible to that requested.
There's no need for ipa_endpoint_init_hol_block_timer() to return
an error, so change its return type to void.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-03 21:23:35 +00:00
|
|
|
return 0; /* Nothing to compute if timer period is 0 */
|
|
|
|
|
2021-03-24 13:15:23 +00:00
|
|
|
if (ipa->version >= IPA_VERSION_4_5)
|
2020-11-30 23:37:12 +00:00
|
|
|
return hol_block_timer_qtime_val(ipa, microseconds);
|
|
|
|
|
net: ipa: fix HOLB timer calculation
For IPA v4.2, the exact interpretation of the register that defines
the timeout for avoiding head-of-line blocking was a little unclear.
We're only assigning a 0 timeout to it right now, so that wasn't
very important. But now that I know how it's supposed to work, I'm
fixing it.
The register represents a tick counter, where each tick is equal to
128 IPA core clock cycles. For IPA v3.5.1, the register contains
a simple counter value. But for IPA v4.2, the register contains two
fields, base and scale, which approximate the tick counter as:
ticks = base << scale
The base and scale values to use for a given tick count are computed
using clever bit operations, and measures are taken to make the
resulting time period as close as possible to that requested.
There's no need for ipa_endpoint_init_hol_block_timer() to return
an error, so change its return type to void.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-03 21:23:35 +00:00
|
|
|
/* Use 64 bit arithmetic to avoid overflow... */
|
2021-08-20 16:01:28 +00:00
|
|
|
rate = ipa_core_clock_rate(ipa);
|
net: ipa: fix HOLB timer calculation
For IPA v4.2, the exact interpretation of the register that defines
the timeout for avoiding head-of-line blocking was a little unclear.
We're only assigning a 0 timeout to it right now, so that wasn't
very important. But now that I know how it's supposed to work, I'm
fixing it.
The register represents a tick counter, where each tick is equal to
128 IPA core clock cycles. For IPA v3.5.1, the register contains
a simple counter value. But for IPA v4.2, the register contains two
fields, base and scale, which approximate the tick counter as:
ticks = base << scale
The base and scale values to use for a given tick count are computed
using clever bit operations, and measures are taken to make the
resulting time period as close as possible to that requested.
There's no need for ipa_endpoint_init_hol_block_timer() to return
an error, so change its return type to void.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-03 21:23:35 +00:00
|
|
|
ticks = DIV_ROUND_CLOSEST(microseconds * rate, 128 * USEC_PER_SEC);
|
|
|
|
/* ...but we still need to fit into a 32-bit register */
|
|
|
|
WARN_ON(ticks > U32_MAX);
|
|
|
|
|
2020-11-16 23:37:57 +00:00
|
|
|
/* IPA v3.5.1 through v4.1 just record the tick count */
|
|
|
|
if (ipa->version < IPA_VERSION_4_2)
|
net: ipa: fix HOLB timer calculation
For IPA v4.2, the exact interpretation of the register that defines
the timeout for avoiding head-of-line blocking was a little unclear.
We're only assigning a 0 timeout to it right now, so that wasn't
very important. But now that I know how it's supposed to work, I'm
fixing it.
The register represents a tick counter, where each tick is equal to
128 IPA core clock cycles. For IPA v3.5.1, the register contains
a simple counter value. But for IPA v4.2, the register contains two
fields, base and scale, which approximate the tick counter as:
ticks = base << scale
The base and scale values to use for a given tick count are computed
using clever bit operations, and measures are taken to make the
resulting time period as close as possible to that requested.
There's no need for ipa_endpoint_init_hol_block_timer() to return
an error, so change its return type to void.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-03 21:23:35 +00:00
|
|
|
return (u32)ticks;
|
|
|
|
|
|
|
|
/* For IPA v4.2, the tick count is represented by base and
|
|
|
|
* scale fields within the 32-bit timer register, where:
|
|
|
|
* ticks = base << scale;
|
|
|
|
* The best precision is achieved when the base value is as
|
|
|
|
* large as possible. Find the highest set bit in the tick
|
|
|
|
* count, and extract the number of bits in the base field
|
2021-03-30 07:27:56 +00:00
|
|
|
* such that high bit is included.
|
net: ipa: fix HOLB timer calculation
For IPA v4.2, the exact interpretation of the register that defines
the timeout for avoiding head-of-line blocking was a little unclear.
We're only assigning a 0 timeout to it right now, so that wasn't
very important. But now that I know how it's supposed to work, I'm
fixing it.
The register represents a tick counter, where each tick is equal to
128 IPA core clock cycles. For IPA v3.5.1, the register contains
a simple counter value. But for IPA v4.2, the register contains two
fields, base and scale, which approximate the tick counter as:
ticks = base << scale
The base and scale values to use for a given tick count are computed
using clever bit operations, and measures are taken to make the
resulting time period as close as possible to that requested.
There's no need for ipa_endpoint_init_hol_block_timer() to return
an error, so change its return type to void.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-03 21:23:35 +00:00
|
|
|
*/
|
|
|
|
high = fls(ticks); /* 1..32 */
|
|
|
|
width = HWEIGHT32(BASE_VALUE_FMASK);
|
|
|
|
scale = high > width ? high - width : 0;
|
|
|
|
if (scale) {
|
|
|
|
/* If we're scaling, round up to get a closer result */
|
|
|
|
ticks += 1 << (scale - 1);
|
|
|
|
/* High bit was set, so rounding might have affected it */
|
|
|
|
if (fls(ticks) != high)
|
|
|
|
scale++;
|
|
|
|
}
|
2020-03-06 04:28:24 +00:00
|
|
|
|
|
|
|
val = u32_encode_bits(scale, SCALE_FMASK);
|
net: ipa: fix HOLB timer calculation
For IPA v4.2, the exact interpretation of the register that defines
the timeout for avoiding head-of-line blocking was a little unclear.
We're only assigning a 0 timeout to it right now, so that wasn't
very important. But now that I know how it's supposed to work, I'm
fixing it.
The register represents a tick counter, where each tick is equal to
128 IPA core clock cycles. For IPA v3.5.1, the register contains
a simple counter value. But for IPA v4.2, the register contains two
fields, base and scale, which approximate the tick counter as:
ticks = base << scale
The base and scale values to use for a given tick count are computed
using clever bit operations, and measures are taken to make the
resulting time period as close as possible to that requested.
There's no need for ipa_endpoint_init_hol_block_timer() to return
an error, so change its return type to void.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-03 21:23:35 +00:00
|
|
|
val |= u32_encode_bits(ticks >> scale, BASE_VALUE_FMASK);
|
2020-03-06 04:28:24 +00:00
|
|
|
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
net: ipa: fix HOLB timer calculation
For IPA v4.2, the exact interpretation of the register that defines
the timeout for avoiding head-of-line blocking was a little unclear.
We're only assigning a 0 timeout to it right now, so that wasn't
very important. But now that I know how it's supposed to work, I'm
fixing it.
The register represents a tick counter, where each tick is equal to
128 IPA core clock cycles. For IPA v3.5.1, the register contains
a simple counter value. But for IPA v4.2, the register contains two
fields, base and scale, which approximate the tick counter as:
ticks = base << scale
The base and scale values to use for a given tick count are computed
using clever bit operations, and measures are taken to make the
resulting time period as close as possible to that requested.
There's no need for ipa_endpoint_init_hol_block_timer() to return
an error, so change its return type to void.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-03 21:23:35 +00:00
|
|
|
/* If microseconds is 0, timeout is immediate */
|
|
|
|
static void ipa_endpoint_init_hol_block_timer(struct ipa_endpoint *endpoint,
|
|
|
|
u32 microseconds)
|
2020-03-06 04:28:24 +00:00
|
|
|
{
|
|
|
|
u32 endpoint_id = endpoint->endpoint_id;
|
|
|
|
struct ipa *ipa = endpoint->ipa;
|
|
|
|
u32 offset;
|
|
|
|
u32 val;
|
|
|
|
|
2021-11-12 22:22:10 +00:00
|
|
|
/* This should only be changed when HOL_BLOCK_EN is disabled */
|
2020-03-06 04:28:24 +00:00
|
|
|
offset = IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(endpoint_id);
|
2020-11-30 23:37:12 +00:00
|
|
|
val = hol_block_timer_val(ipa, microseconds);
|
2020-03-06 04:28:24 +00:00
|
|
|
iowrite32(val, ipa->reg_virt + offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
ipa_endpoint_init_hol_block_enable(struct ipa_endpoint *endpoint, bool enable)
|
|
|
|
{
|
|
|
|
u32 endpoint_id = endpoint->endpoint_id;
|
|
|
|
u32 offset;
|
|
|
|
u32 val;
|
|
|
|
|
2020-06-30 13:33:04 +00:00
|
|
|
val = enable ? HOL_BLOCK_EN_FMASK : 0;
|
2020-03-06 04:28:24 +00:00
|
|
|
offset = IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(endpoint_id);
|
|
|
|
iowrite32(val, endpoint->ipa->reg_virt + offset);
|
2021-11-12 22:22:09 +00:00
|
|
|
/* When enabling, the register must be written twice for IPA v4.5+ */
|
|
|
|
if (enable && endpoint->ipa->version >= IPA_VERSION_4_5)
|
|
|
|
iowrite32(val, endpoint->ipa->reg_virt + offset);
|
2020-03-06 04:28:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void ipa_endpoint_modem_hol_block_clear_all(struct ipa *ipa)
|
|
|
|
{
|
|
|
|
u32 i;
|
|
|
|
|
|
|
|
for (i = 0; i < IPA_ENDPOINT_MAX; i++) {
|
|
|
|
struct ipa_endpoint *endpoint = &ipa->endpoint[i];
|
|
|
|
|
2020-06-30 13:33:00 +00:00
|
|
|
if (endpoint->toward_ipa || endpoint->ee_id != GSI_EE_MODEM)
|
2020-03-06 04:28:24 +00:00
|
|
|
continue;
|
|
|
|
|
2021-11-12 22:22:10 +00:00
|
|
|
ipa_endpoint_init_hol_block_enable(endpoint, false);
|
net: ipa: fix HOLB timer calculation
For IPA v4.2, the exact interpretation of the register that defines
the timeout for avoiding head-of-line blocking was a little unclear.
We're only assigning a 0 timeout to it right now, so that wasn't
very important. But now that I know how it's supposed to work, I'm
fixing it.
The register represents a tick counter, where each tick is equal to
128 IPA core clock cycles. For IPA v3.5.1, the register contains
a simple counter value. But for IPA v4.2, the register contains two
fields, base and scale, which approximate the tick counter as:
ticks = base << scale
The base and scale values to use for a given tick count are computed
using clever bit operations, and measures are taken to make the
resulting time period as close as possible to that requested.
There's no need for ipa_endpoint_init_hol_block_timer() to return
an error, so change its return type to void.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-03 21:23:35 +00:00
|
|
|
ipa_endpoint_init_hol_block_timer(endpoint, 0);
|
2020-03-06 04:28:24 +00:00
|
|
|
ipa_endpoint_init_hol_block_enable(endpoint, true);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ipa_endpoint_init_deaggr(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
u32 offset = IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(endpoint->endpoint_id);
|
|
|
|
u32 val = 0;
|
|
|
|
|
2020-07-02 11:25:37 +00:00
|
|
|
if (!endpoint->toward_ipa)
|
|
|
|
return; /* Register not valid for RX endpoints */
|
|
|
|
|
2020-03-06 04:28:24 +00:00
|
|
|
/* DEAGGR_HDR_LEN is 0 */
|
|
|
|
/* PACKET_OFFSET_VALID is 0 */
|
|
|
|
/* PACKET_OFFSET_LOCATION is ignored (not valid) */
|
|
|
|
/* MAX_PACKET_LEN is 0 (not enforced) */
|
|
|
|
|
|
|
|
iowrite32(val, endpoint->ipa->reg_virt + offset);
|
|
|
|
}
|
|
|
|
|
2020-10-28 19:41:46 +00:00
|
|
|
static void ipa_endpoint_init_rsrc_grp(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
u32 offset = IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(endpoint->endpoint_id);
|
|
|
|
struct ipa *ipa = endpoint->ipa;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
val = rsrc_grp_encoded(ipa->version, endpoint->data->resource_group);
|
|
|
|
iowrite32(val, ipa->reg_virt + offset);
|
|
|
|
}
|
|
|
|
|
2020-03-06 04:28:24 +00:00
|
|
|
static void ipa_endpoint_init_seq(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
u32 offset = IPA_REG_ENDP_INIT_SEQ_N_OFFSET(endpoint->endpoint_id);
|
|
|
|
u32 val = 0;
|
|
|
|
|
2020-07-02 11:25:37 +00:00
|
|
|
if (!endpoint->toward_ipa)
|
|
|
|
return; /* Register not valid for RX endpoints */
|
|
|
|
|
2021-03-20 15:57:05 +00:00
|
|
|
/* Low-order byte configures primary packet processing */
|
2021-03-20 15:57:06 +00:00
|
|
|
val |= u32_encode_bits(endpoint->data->tx.seq_type, SEQ_TYPE_FMASK);
|
2021-03-20 15:57:05 +00:00
|
|
|
|
|
|
|
/* Second byte configures replicated packet processing */
|
2021-03-20 15:57:06 +00:00
|
|
|
val |= u32_encode_bits(endpoint->data->tx.seq_rep_type,
|
|
|
|
SEQ_REP_TYPE_FMASK);
|
2020-03-06 04:28:24 +00:00
|
|
|
|
|
|
|
iowrite32(val, endpoint->ipa->reg_virt + offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* ipa_endpoint_skb_tx() - Transmit a socket buffer
|
|
|
|
* @endpoint: Endpoint pointer
|
|
|
|
* @skb: Socket buffer to send
|
|
|
|
*
|
|
|
|
* Returns: 0 if successful, or a negative error code
|
|
|
|
*/
|
|
|
|
int ipa_endpoint_skb_tx(struct ipa_endpoint *endpoint, struct sk_buff *skb)
|
|
|
|
{
|
|
|
|
struct gsi_trans *trans;
|
|
|
|
u32 nr_frags;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Make sure source endpoint's TLV FIFO has enough entries to
|
|
|
|
* hold the linear portion of the skb and all its fragments.
|
|
|
|
* If not, see if we can linearize it before giving up.
|
|
|
|
*/
|
|
|
|
nr_frags = skb_shinfo(skb)->nr_frags;
|
|
|
|
if (1 + nr_frags > endpoint->trans_tre_max) {
|
|
|
|
if (skb_linearize(skb))
|
|
|
|
return -E2BIG;
|
|
|
|
nr_frags = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
trans = ipa_endpoint_trans_alloc(endpoint, 1 + nr_frags);
|
|
|
|
if (!trans)
|
|
|
|
return -EBUSY;
|
|
|
|
|
|
|
|
ret = gsi_trans_skb_add(trans, skb);
|
|
|
|
if (ret)
|
|
|
|
goto err_trans_free;
|
|
|
|
trans->data = skb; /* transaction owns skb now */
|
|
|
|
|
|
|
|
gsi_trans_commit(trans, !netdev_xmit_more());
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_trans_free:
|
|
|
|
gsi_trans_free(trans);
|
|
|
|
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ipa_endpoint_status(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
u32 endpoint_id = endpoint->endpoint_id;
|
|
|
|
struct ipa *ipa = endpoint->ipa;
|
|
|
|
u32 val = 0;
|
|
|
|
u32 offset;
|
|
|
|
|
|
|
|
offset = IPA_REG_ENDP_STATUS_N_OFFSET(endpoint_id);
|
|
|
|
|
|
|
|
if (endpoint->data->status_enable) {
|
|
|
|
val |= STATUS_EN_FMASK;
|
|
|
|
if (endpoint->toward_ipa) {
|
|
|
|
enum ipa_endpoint_name name;
|
|
|
|
u32 status_endpoint_id;
|
|
|
|
|
|
|
|
name = endpoint->data->tx.status_endpoint;
|
|
|
|
status_endpoint_id = ipa->name_map[name]->endpoint_id;
|
|
|
|
|
|
|
|
val |= u32_encode_bits(status_endpoint_id,
|
|
|
|
STATUS_ENDP_FMASK);
|
|
|
|
}
|
2020-11-25 20:45:20 +00:00
|
|
|
/* STATUS_LOCATION is 0, meaning status element precedes
|
|
|
|
* packet (not present for IPA v4.5)
|
|
|
|
*/
|
|
|
|
/* STATUS_PKT_SUPPRESS_FMASK is 0 (not present for v3.5.1) */
|
2020-03-06 04:28:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
iowrite32(val, ipa->reg_virt + offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ipa_endpoint_replenish_one(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
struct gsi_trans *trans;
|
|
|
|
bool doorbell = false;
|
|
|
|
struct page *page;
|
|
|
|
u32 offset;
|
|
|
|
u32 len;
|
|
|
|
int ret;
|
|
|
|
|
2020-03-20 16:02:20 +00:00
|
|
|
page = dev_alloc_pages(get_order(IPA_RX_BUFFER_SIZE));
|
2020-03-06 04:28:24 +00:00
|
|
|
if (!page)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
trans = ipa_endpoint_trans_alloc(endpoint, 1);
|
|
|
|
if (!trans)
|
|
|
|
goto err_free_pages;
|
|
|
|
|
|
|
|
/* Offset the buffer to make space for skb headroom */
|
|
|
|
offset = NET_SKB_PAD;
|
|
|
|
len = IPA_RX_BUFFER_SIZE - offset;
|
|
|
|
|
|
|
|
ret = gsi_trans_page_add(trans, page, len, offset);
|
|
|
|
if (ret)
|
|
|
|
goto err_trans_free;
|
|
|
|
trans->data = page; /* transaction owns page now */
|
|
|
|
|
|
|
|
if (++endpoint->replenish_ready == IPA_REPLENISH_BATCH) {
|
|
|
|
doorbell = true;
|
|
|
|
endpoint->replenish_ready = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
gsi_trans_commit(trans, doorbell);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_trans_free:
|
|
|
|
gsi_trans_free(trans);
|
|
|
|
err_free_pages:
|
2020-03-20 16:02:20 +00:00
|
|
|
__free_pages(page, get_order(IPA_RX_BUFFER_SIZE));
|
2020-03-06 04:28:24 +00:00
|
|
|
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2021-02-05 22:10:58 +00:00
|
|
|
* ipa_endpoint_replenish() - Replenish endpoint receive buffers
|
2020-07-13 12:24:18 +00:00
|
|
|
* @endpoint: Endpoint to be replenished
|
2021-02-05 22:10:58 +00:00
|
|
|
* @add_one: Whether this is replacing a just-consumed buffer
|
2020-03-06 04:28:24 +00:00
|
|
|
*
|
2021-02-05 22:10:58 +00:00
|
|
|
* The IPA hardware can hold a fixed number of receive buffers for an RX
|
|
|
|
* endpoint, based on the number of entries in the underlying channel ring
|
|
|
|
* buffer. If an endpoint's "backlog" is non-zero, it indicates how many
|
|
|
|
* more receive buffers can be supplied to the hardware. Replenishing for
|
|
|
|
* an endpoint can be disabled, in which case requests to replenish a
|
|
|
|
* buffer are "saved", and transferred to the backlog once it is re-enabled
|
|
|
|
* again.
|
2020-03-06 04:28:24 +00:00
|
|
|
*/
|
2021-02-05 22:10:58 +00:00
|
|
|
static void ipa_endpoint_replenish(struct ipa_endpoint *endpoint, bool add_one)
|
2020-03-06 04:28:24 +00:00
|
|
|
{
|
|
|
|
struct gsi *gsi;
|
|
|
|
u32 backlog;
|
|
|
|
|
|
|
|
if (!endpoint->replenish_enabled) {
|
2021-02-05 22:10:58 +00:00
|
|
|
if (add_one)
|
|
|
|
atomic_inc(&endpoint->replenish_saved);
|
2020-03-06 04:28:24 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (atomic_dec_not_zero(&endpoint->replenish_backlog))
|
|
|
|
if (ipa_endpoint_replenish_one(endpoint))
|
|
|
|
goto try_again_later;
|
2021-02-05 22:10:58 +00:00
|
|
|
if (add_one)
|
|
|
|
atomic_inc(&endpoint->replenish_backlog);
|
2020-03-06 04:28:24 +00:00
|
|
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
try_again_later:
|
|
|
|
/* The last one didn't succeed, so fix the backlog */
|
|
|
|
backlog = atomic_inc_return(&endpoint->replenish_backlog);
|
|
|
|
|
2021-02-05 22:10:58 +00:00
|
|
|
if (add_one)
|
|
|
|
atomic_inc(&endpoint->replenish_backlog);
|
2020-03-06 04:28:24 +00:00
|
|
|
|
|
|
|
/* Whenever a receive buffer transaction completes we'll try to
|
|
|
|
* replenish again. It's unlikely, but if we fail to supply even
|
|
|
|
* one buffer, nothing will trigger another replenish attempt.
|
|
|
|
* Receive buffer transactions use one TRE, so schedule work to
|
|
|
|
* try replenishing again if our backlog is *all* available TREs.
|
|
|
|
*/
|
|
|
|
gsi = &endpoint->ipa->gsi;
|
|
|
|
if (backlog == gsi_channel_tre_max(gsi, endpoint->channel_id))
|
|
|
|
schedule_delayed_work(&endpoint->replenish_work,
|
|
|
|
msecs_to_jiffies(1));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ipa_endpoint_replenish_enable(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
struct gsi *gsi = &endpoint->ipa->gsi;
|
|
|
|
u32 max_backlog;
|
|
|
|
u32 saved;
|
|
|
|
|
|
|
|
endpoint->replenish_enabled = true;
|
|
|
|
while ((saved = atomic_xchg(&endpoint->replenish_saved, 0)))
|
|
|
|
atomic_add(saved, &endpoint->replenish_backlog);
|
|
|
|
|
|
|
|
/* Start replenishing if hardware currently has no buffers */
|
|
|
|
max_backlog = gsi_channel_tre_max(gsi, endpoint->channel_id);
|
|
|
|
if (atomic_read(&endpoint->replenish_backlog) == max_backlog)
|
2021-02-05 22:10:58 +00:00
|
|
|
ipa_endpoint_replenish(endpoint, false);
|
2020-03-06 04:28:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void ipa_endpoint_replenish_disable(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
u32 backlog;
|
|
|
|
|
|
|
|
endpoint->replenish_enabled = false;
|
|
|
|
while ((backlog = atomic_xchg(&endpoint->replenish_backlog, 0)))
|
|
|
|
atomic_add(backlog, &endpoint->replenish_saved);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ipa_endpoint_replenish_work(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct delayed_work *dwork = to_delayed_work(work);
|
|
|
|
struct ipa_endpoint *endpoint;
|
|
|
|
|
|
|
|
endpoint = container_of(dwork, struct ipa_endpoint, replenish_work);
|
|
|
|
|
2021-02-05 22:10:58 +00:00
|
|
|
ipa_endpoint_replenish(endpoint, false);
|
2020-03-06 04:28:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void ipa_endpoint_skb_copy(struct ipa_endpoint *endpoint,
|
|
|
|
void *data, u32 len, u32 extra)
|
|
|
|
{
|
|
|
|
struct sk_buff *skb;
|
|
|
|
|
|
|
|
skb = __dev_alloc_skb(len, GFP_ATOMIC);
|
|
|
|
if (skb) {
|
|
|
|
skb_put(skb, len);
|
|
|
|
memcpy(skb->data, data, len);
|
|
|
|
skb->truesize += extra;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Now receive it, or drop it if there's no netdev */
|
|
|
|
if (endpoint->netdev)
|
|
|
|
ipa_modem_skb_rx(endpoint->netdev, skb);
|
|
|
|
else if (skb)
|
|
|
|
dev_kfree_skb_any(skb);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool ipa_endpoint_skb_build(struct ipa_endpoint *endpoint,
|
|
|
|
struct page *page, u32 len)
|
|
|
|
{
|
|
|
|
struct sk_buff *skb;
|
|
|
|
|
|
|
|
/* Nothing to do if there's no netdev */
|
|
|
|
if (!endpoint->netdev)
|
|
|
|
return false;
|
|
|
|
|
2021-07-26 17:40:10 +00:00
|
|
|
WARN_ON(len > SKB_WITH_OVERHEAD(IPA_RX_BUFFER_SIZE - NET_SKB_PAD));
|
|
|
|
|
2020-03-06 04:28:24 +00:00
|
|
|
skb = build_skb(page_address(page), IPA_RX_BUFFER_SIZE);
|
|
|
|
if (skb) {
|
|
|
|
/* Reserve the headroom and account for the data */
|
|
|
|
skb_reserve(skb, NET_SKB_PAD);
|
|
|
|
skb_put(skb, len);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Receive the buffer (or record drop if unable to build it) */
|
|
|
|
ipa_modem_skb_rx(endpoint->netdev, skb);
|
|
|
|
|
|
|
|
return skb != NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* The format of a packet status element is the same for several status
|
2020-09-28 23:04:38 +00:00
|
|
|
* types (opcodes). Other types aren't currently supported.
|
2020-03-06 04:28:24 +00:00
|
|
|
*/
|
|
|
|
static bool ipa_status_format_packet(enum ipa_status_opcode opcode)
|
|
|
|
{
|
|
|
|
switch (opcode) {
|
|
|
|
case IPA_STATUS_OPCODE_PACKET:
|
|
|
|
case IPA_STATUS_OPCODE_DROPPED_PACKET:
|
|
|
|
case IPA_STATUS_OPCODE_SUSPENDED_PACKET:
|
|
|
|
case IPA_STATUS_OPCODE_PACKET_2ND_PASS:
|
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool ipa_endpoint_status_skip(struct ipa_endpoint *endpoint,
|
|
|
|
const struct ipa_status *status)
|
|
|
|
{
|
|
|
|
u32 endpoint_id;
|
|
|
|
|
|
|
|
if (!ipa_status_format_packet(status->opcode))
|
|
|
|
return true;
|
|
|
|
if (!status->pkt_len)
|
|
|
|
return true;
|
2021-02-01 23:26:08 +00:00
|
|
|
endpoint_id = u8_get_bits(status->endp_dst_idx,
|
|
|
|
IPA_STATUS_DST_IDX_FMASK);
|
2020-03-06 04:28:24 +00:00
|
|
|
if (endpoint_id != endpoint->endpoint_id)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
return false; /* Don't skip this packet, process it */
|
|
|
|
}
|
|
|
|
|
2021-01-26 18:57:00 +00:00
|
|
|
static bool ipa_endpoint_status_tag(struct ipa_endpoint *endpoint,
|
|
|
|
const struct ipa_status *status)
|
|
|
|
{
|
2021-01-26 18:57:01 +00:00
|
|
|
struct ipa_endpoint *command_endpoint;
|
|
|
|
struct ipa *ipa = endpoint->ipa;
|
|
|
|
u32 endpoint_id;
|
|
|
|
|
|
|
|
if (!le16_get_bits(status->mask, IPA_STATUS_MASK_TAG_VALID_FMASK))
|
|
|
|
return false; /* No valid tag */
|
|
|
|
|
|
|
|
/* The status contains a valid tag. We know the packet was sent to
|
|
|
|
* this endpoint (already verified by ipa_endpoint_status_skip()).
|
|
|
|
* If the packet came from the AP->command TX endpoint we know
|
|
|
|
* this packet was sent as part of the pipeline clear process.
|
|
|
|
*/
|
|
|
|
endpoint_id = u8_get_bits(status->endp_src_idx,
|
|
|
|
IPA_STATUS_SRC_IDX_FMASK);
|
|
|
|
command_endpoint = ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX];
|
|
|
|
if (endpoint_id == command_endpoint->endpoint_id) {
|
|
|
|
complete(&ipa->completion);
|
|
|
|
} else {
|
|
|
|
dev_err(&ipa->pdev->dev,
|
|
|
|
"unexpected tagged packet from endpoint %u\n",
|
|
|
|
endpoint_id);
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
2021-01-26 18:57:00 +00:00
|
|
|
}
|
|
|
|
|
2020-03-06 04:28:24 +00:00
|
|
|
/* Return whether the status indicates the packet should be dropped */
|
2021-01-26 18:57:00 +00:00
|
|
|
static bool ipa_endpoint_status_drop(struct ipa_endpoint *endpoint,
|
|
|
|
const struct ipa_status *status)
|
2020-03-06 04:28:24 +00:00
|
|
|
{
|
|
|
|
u32 val;
|
|
|
|
|
2021-01-26 18:57:00 +00:00
|
|
|
/* If the status indicates a tagged transfer, we'll drop the packet */
|
|
|
|
if (ipa_endpoint_status_tag(endpoint, status))
|
|
|
|
return true;
|
|
|
|
|
2020-09-28 23:04:39 +00:00
|
|
|
/* Deaggregation exceptions we drop; all other types we consume */
|
2020-03-06 04:28:24 +00:00
|
|
|
if (status->exception)
|
|
|
|
return status->exception == IPA_STATUS_EXCEPTION_DEAGGR;
|
|
|
|
|
|
|
|
/* Drop the packet if it fails to match a routing rule; otherwise no */
|
|
|
|
val = le32_get_bits(status->flags1, IPA_STATUS_FLAGS1_RT_RULE_ID_FMASK);
|
|
|
|
|
|
|
|
return val == field_max(IPA_STATUS_FLAGS1_RT_RULE_ID_FMASK);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ipa_endpoint_status_parse(struct ipa_endpoint *endpoint,
|
|
|
|
struct page *page, u32 total_len)
|
|
|
|
{
|
|
|
|
void *data = page_address(page) + NET_SKB_PAD;
|
|
|
|
u32 unused = IPA_RX_BUFFER_SIZE - total_len;
|
|
|
|
u32 resid = total_len;
|
|
|
|
|
|
|
|
while (resid) {
|
|
|
|
const struct ipa_status *status = data;
|
|
|
|
u32 align;
|
|
|
|
u32 len;
|
|
|
|
|
|
|
|
if (resid < sizeof(*status)) {
|
|
|
|
dev_err(&endpoint->ipa->pdev->dev,
|
|
|
|
"short message (%u bytes < %zu byte status)\n",
|
|
|
|
resid, sizeof(*status));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Skip over status packets that lack packet data */
|
|
|
|
if (ipa_endpoint_status_skip(endpoint, status)) {
|
|
|
|
data += sizeof(*status);
|
|
|
|
resid -= sizeof(*status);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2021-01-26 18:56:59 +00:00
|
|
|
/* Compute the amount of buffer space consumed by the packet,
|
|
|
|
* including the status element. If the hardware is configured
|
|
|
|
* to pad packet data to an aligned boundary, account for that.
|
|
|
|
* And if checksum offload is enabled a trailer containing
|
|
|
|
* computed checksum information will be appended.
|
2020-03-06 04:28:24 +00:00
|
|
|
*/
|
|
|
|
align = endpoint->data->rx.pad_align ? : 1;
|
|
|
|
len = le16_to_cpu(status->pkt_len);
|
|
|
|
len = sizeof(*status) + ALIGN(len, align);
|
|
|
|
if (endpoint->data->checksum)
|
|
|
|
len += sizeof(struct rmnet_map_dl_csum_trailer);
|
|
|
|
|
2021-01-26 18:57:00 +00:00
|
|
|
if (!ipa_endpoint_status_drop(endpoint, status)) {
|
2021-01-26 18:56:59 +00:00
|
|
|
void *data2;
|
|
|
|
u32 extra;
|
|
|
|
u32 len2;
|
2020-03-06 04:28:24 +00:00
|
|
|
|
|
|
|
/* Client receives only packet data (no status) */
|
2021-01-26 18:56:59 +00:00
|
|
|
data2 = data + sizeof(*status);
|
|
|
|
len2 = le16_to_cpu(status->pkt_len);
|
|
|
|
|
|
|
|
/* Have the true size reflect the extra unused space in
|
|
|
|
* the original receive buffer. Distribute the "cost"
|
|
|
|
* proportionately across all aggregated packets in the
|
|
|
|
* buffer.
|
|
|
|
*/
|
|
|
|
extra = DIV_ROUND_CLOSEST(unused * len, total_len);
|
2020-03-06 04:28:24 +00:00
|
|
|
ipa_endpoint_skb_copy(endpoint, data2, len2, extra);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Consume status and the full packet it describes */
|
|
|
|
data += len;
|
|
|
|
resid -= len;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Complete a TX transaction, command or from ipa_endpoint_skb_tx() */
|
|
|
|
static void ipa_endpoint_tx_complete(struct ipa_endpoint *endpoint,
|
|
|
|
struct gsi_trans *trans)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Complete transaction initiated in ipa_endpoint_replenish_one() */
|
|
|
|
static void ipa_endpoint_rx_complete(struct ipa_endpoint *endpoint,
|
|
|
|
struct gsi_trans *trans)
|
|
|
|
{
|
|
|
|
struct page *page;
|
|
|
|
|
2021-02-05 22:10:58 +00:00
|
|
|
ipa_endpoint_replenish(endpoint, true);
|
2020-03-06 04:28:24 +00:00
|
|
|
|
|
|
|
if (trans->cancelled)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* Parse or build a socket buffer using the actual received length */
|
|
|
|
page = trans->data;
|
|
|
|
if (endpoint->data->status_enable)
|
|
|
|
ipa_endpoint_status_parse(endpoint, page, trans->len);
|
|
|
|
else if (ipa_endpoint_skb_build(endpoint, page, trans->len))
|
|
|
|
trans->data = NULL; /* Pages have been consumed */
|
|
|
|
}
|
|
|
|
|
|
|
|
void ipa_endpoint_trans_complete(struct ipa_endpoint *endpoint,
|
|
|
|
struct gsi_trans *trans)
|
|
|
|
{
|
|
|
|
if (endpoint->toward_ipa)
|
|
|
|
ipa_endpoint_tx_complete(endpoint, trans);
|
|
|
|
else
|
|
|
|
ipa_endpoint_rx_complete(endpoint, trans);
|
|
|
|
}
|
|
|
|
|
|
|
|
void ipa_endpoint_trans_release(struct ipa_endpoint *endpoint,
|
|
|
|
struct gsi_trans *trans)
|
|
|
|
{
|
|
|
|
if (endpoint->toward_ipa) {
|
|
|
|
struct ipa *ipa = endpoint->ipa;
|
|
|
|
|
|
|
|
/* Nothing to do for command transactions */
|
|
|
|
if (endpoint != ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX]) {
|
|
|
|
struct sk_buff *skb = trans->data;
|
|
|
|
|
|
|
|
if (skb)
|
|
|
|
dev_kfree_skb_any(skb);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
struct page *page = trans->data;
|
|
|
|
|
|
|
|
if (page)
|
2020-03-20 16:02:20 +00:00
|
|
|
__free_pages(page, get_order(IPA_RX_BUFFER_SIZE));
|
2020-03-06 04:28:24 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void ipa_endpoint_default_route_set(struct ipa *ipa, u32 endpoint_id)
|
|
|
|
{
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
/* ROUTE_DIS is 0 */
|
|
|
|
val = u32_encode_bits(endpoint_id, ROUTE_DEF_PIPE_FMASK);
|
|
|
|
val |= ROUTE_DEF_HDR_TABLE_FMASK;
|
|
|
|
val |= u32_encode_bits(0, ROUTE_DEF_HDR_OFST_FMASK);
|
|
|
|
val |= u32_encode_bits(endpoint_id, ROUTE_FRAG_DEF_PIPE_FMASK);
|
|
|
|
val |= ROUTE_DEF_RETAIN_HDR_FMASK;
|
|
|
|
|
|
|
|
iowrite32(val, ipa->reg_virt + IPA_REG_ROUTE_OFFSET);
|
|
|
|
}
|
|
|
|
|
|
|
|
void ipa_endpoint_default_route_clear(struct ipa *ipa)
|
|
|
|
{
|
|
|
|
ipa_endpoint_default_route_set(ipa, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* ipa_endpoint_reset_rx_aggr() - Reset RX endpoint with aggregation active
|
|
|
|
* @endpoint: Endpoint to be reset
|
|
|
|
*
|
|
|
|
* If aggregation is active on an RX endpoint when a reset is performed
|
|
|
|
* on its underlying GSI channel, a special sequence of actions must be
|
|
|
|
* taken to ensure the IPA pipeline is properly cleared.
|
|
|
|
*
|
2020-07-13 12:24:18 +00:00
|
|
|
* Return: 0 if successful, or a negative error code
|
2020-03-06 04:28:24 +00:00
|
|
|
*/
|
|
|
|
static int ipa_endpoint_reset_rx_aggr(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
struct device *dev = &endpoint->ipa->pdev->dev;
|
|
|
|
struct ipa *ipa = endpoint->ipa;
|
|
|
|
struct gsi *gsi = &ipa->gsi;
|
2020-05-04 23:37:12 +00:00
|
|
|
bool suspended = false;
|
2020-03-06 04:28:24 +00:00
|
|
|
dma_addr_t addr;
|
|
|
|
u32 retries;
|
|
|
|
u32 len = 1;
|
|
|
|
void *virt;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
virt = kzalloc(len, GFP_KERNEL);
|
|
|
|
if (!virt)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
addr = dma_map_single(dev, virt, len, DMA_FROM_DEVICE);
|
|
|
|
if (dma_mapping_error(dev, addr)) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto out_kfree;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Force close aggregation before issuing the reset */
|
|
|
|
ipa_endpoint_force_close(endpoint);
|
|
|
|
|
|
|
|
/* Reset and reconfigure the channel with the doorbell engine
|
|
|
|
* disabled. Then poll until we know aggregation is no longer
|
|
|
|
* active. We'll re-enable the doorbell (if appropriate) when
|
|
|
|
* we reset again below.
|
|
|
|
*/
|
|
|
|
gsi_channel_reset(gsi, endpoint->channel_id, false);
|
|
|
|
|
|
|
|
/* Make sure the channel isn't suspended */
|
2020-07-02 11:25:36 +00:00
|
|
|
suspended = ipa_endpoint_program_suspend(endpoint, false);
|
2020-03-06 04:28:24 +00:00
|
|
|
|
|
|
|
/* Start channel and do a 1 byte read */
|
|
|
|
ret = gsi_channel_start(gsi, endpoint->channel_id);
|
|
|
|
if (ret)
|
|
|
|
goto out_suspend_again;
|
|
|
|
|
|
|
|
ret = gsi_trans_read_byte(gsi, endpoint->channel_id, addr);
|
|
|
|
if (ret)
|
|
|
|
goto err_endpoint_stop;
|
|
|
|
|
|
|
|
/* Wait for aggregation to be closed on the channel */
|
|
|
|
retries = IPA_ENDPOINT_RESET_AGGR_RETRY_MAX;
|
|
|
|
do {
|
|
|
|
if (!ipa_endpoint_aggr_active(endpoint))
|
|
|
|
break;
|
2021-01-13 17:15:29 +00:00
|
|
|
usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
|
2020-03-06 04:28:24 +00:00
|
|
|
} while (retries--);
|
|
|
|
|
|
|
|
/* Check one last time */
|
|
|
|
if (ipa_endpoint_aggr_active(endpoint))
|
|
|
|
dev_err(dev, "endpoint %u still active during reset\n",
|
|
|
|
endpoint->endpoint_id);
|
|
|
|
|
|
|
|
gsi_trans_read_byte_done(gsi, endpoint->channel_id);
|
|
|
|
|
2020-05-04 23:53:44 +00:00
|
|
|
ret = gsi_channel_stop(gsi, endpoint->channel_id);
|
2020-03-06 04:28:24 +00:00
|
|
|
if (ret)
|
|
|
|
goto out_suspend_again;
|
|
|
|
|
2021-03-30 07:27:56 +00:00
|
|
|
/* Finally, reset and reconfigure the channel again (re-enabling
|
2020-03-06 04:28:24 +00:00
|
|
|
* the doorbell engine if appropriate). Sleep for 1 millisecond to
|
|
|
|
* complete the channel reset sequence. Finish by suspending the
|
|
|
|
* channel again (if necessary).
|
|
|
|
*/
|
2020-11-02 17:53:59 +00:00
|
|
|
gsi_channel_reset(gsi, endpoint->channel_id, true);
|
2020-03-06 04:28:24 +00:00
|
|
|
|
2021-01-13 17:15:29 +00:00
|
|
|
usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
|
2020-03-06 04:28:24 +00:00
|
|
|
|
|
|
|
goto out_suspend_again;
|
|
|
|
|
|
|
|
err_endpoint_stop:
|
2020-05-04 23:53:44 +00:00
|
|
|
(void)gsi_channel_stop(gsi, endpoint->channel_id);
|
2020-03-06 04:28:24 +00:00
|
|
|
out_suspend_again:
|
2020-05-04 23:37:12 +00:00
|
|
|
if (suspended)
|
|
|
|
(void)ipa_endpoint_program_suspend(endpoint, true);
|
2020-03-06 04:28:24 +00:00
|
|
|
dma_unmap_single(dev, addr, len, DMA_FROM_DEVICE);
|
|
|
|
out_kfree:
|
|
|
|
kfree(virt);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ipa_endpoint_reset(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
u32 channel_id = endpoint->channel_id;
|
|
|
|
struct ipa *ipa = endpoint->ipa;
|
|
|
|
bool special;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
/* On IPA v3.5.1, if an RX endpoint is reset while aggregation
|
|
|
|
* is active, we need to handle things specially to recover.
|
|
|
|
* All other cases just need to reset the underlying GSI channel.
|
|
|
|
*/
|
2021-03-24 13:15:23 +00:00
|
|
|
special = ipa->version < IPA_VERSION_4_0 && !endpoint->toward_ipa &&
|
2020-11-02 17:53:59 +00:00
|
|
|
endpoint->data->aggregation;
|
|
|
|
if (special && ipa_endpoint_aggr_active(endpoint))
|
2020-03-06 04:28:24 +00:00
|
|
|
ret = ipa_endpoint_reset_rx_aggr(endpoint);
|
|
|
|
else
|
2020-11-02 17:53:59 +00:00
|
|
|
gsi_channel_reset(&ipa->gsi, channel_id, true);
|
2020-03-06 04:28:24 +00:00
|
|
|
|
|
|
|
if (ret)
|
|
|
|
dev_err(&ipa->pdev->dev,
|
|
|
|
"error %d resetting channel %u for endpoint %u\n",
|
|
|
|
ret, endpoint->channel_id, endpoint->endpoint_id);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ipa_endpoint_program(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
2020-07-02 11:25:37 +00:00
|
|
|
if (endpoint->toward_ipa)
|
2020-07-02 11:25:34 +00:00
|
|
|
ipa_endpoint_program_delay(endpoint, false);
|
2020-07-02 11:25:37 +00:00
|
|
|
else
|
2020-07-02 11:25:36 +00:00
|
|
|
(void)ipa_endpoint_program_suspend(endpoint, false);
|
2020-03-06 04:28:24 +00:00
|
|
|
ipa_endpoint_init_cfg(endpoint);
|
2021-03-24 13:15:25 +00:00
|
|
|
ipa_endpoint_init_nat(endpoint);
|
2020-03-06 04:28:24 +00:00
|
|
|
ipa_endpoint_init_hdr(endpoint);
|
2020-07-02 11:25:37 +00:00
|
|
|
ipa_endpoint_init_hdr_ext(endpoint);
|
|
|
|
ipa_endpoint_init_hdr_metadata_mask(endpoint);
|
|
|
|
ipa_endpoint_init_mode(endpoint);
|
|
|
|
ipa_endpoint_init_aggr(endpoint);
|
|
|
|
ipa_endpoint_init_deaggr(endpoint);
|
2020-10-28 19:41:46 +00:00
|
|
|
ipa_endpoint_init_rsrc_grp(endpoint);
|
2020-07-02 11:25:37 +00:00
|
|
|
ipa_endpoint_init_seq(endpoint);
|
2020-03-06 04:28:24 +00:00
|
|
|
ipa_endpoint_status(endpoint);
|
|
|
|
}
|
|
|
|
|
|
|
|
int ipa_endpoint_enable_one(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
struct ipa *ipa = endpoint->ipa;
|
|
|
|
struct gsi *gsi = &ipa->gsi;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = gsi_channel_start(gsi, endpoint->channel_id);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&ipa->pdev->dev,
|
|
|
|
"error %d starting %cX channel %u for endpoint %u\n",
|
|
|
|
ret, endpoint->toward_ipa ? 'T' : 'R',
|
|
|
|
endpoint->channel_id, endpoint->endpoint_id);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!endpoint->toward_ipa) {
|
|
|
|
ipa_interrupt_suspend_enable(ipa->interrupt,
|
|
|
|
endpoint->endpoint_id);
|
|
|
|
ipa_endpoint_replenish_enable(endpoint);
|
|
|
|
}
|
|
|
|
|
|
|
|
ipa->enabled |= BIT(endpoint->endpoint_id);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void ipa_endpoint_disable_one(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
u32 mask = BIT(endpoint->endpoint_id);
|
|
|
|
struct ipa *ipa = endpoint->ipa;
|
2020-05-04 23:53:44 +00:00
|
|
|
struct gsi *gsi = &ipa->gsi;
|
2020-03-06 04:28:24 +00:00
|
|
|
int ret;
|
|
|
|
|
2020-05-04 23:53:44 +00:00
|
|
|
if (!(ipa->enabled & mask))
|
2020-03-06 04:28:24 +00:00
|
|
|
return;
|
|
|
|
|
2020-05-04 23:53:44 +00:00
|
|
|
ipa->enabled ^= mask;
|
2020-03-06 04:28:24 +00:00
|
|
|
|
|
|
|
if (!endpoint->toward_ipa) {
|
|
|
|
ipa_endpoint_replenish_disable(endpoint);
|
|
|
|
ipa_interrupt_suspend_disable(ipa->interrupt,
|
|
|
|
endpoint->endpoint_id);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Note that if stop fails, the channel's state is not well-defined */
|
2020-05-04 23:53:44 +00:00
|
|
|
ret = gsi_channel_stop(gsi, endpoint->channel_id);
|
2020-03-06 04:28:24 +00:00
|
|
|
if (ret)
|
|
|
|
dev_err(&ipa->pdev->dev,
|
|
|
|
"error %d attempting to stop endpoint %u\n", ret,
|
|
|
|
endpoint->endpoint_id);
|
|
|
|
}
|
|
|
|
|
|
|
|
void ipa_endpoint_suspend_one(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
struct device *dev = &endpoint->ipa->pdev->dev;
|
|
|
|
struct gsi *gsi = &endpoint->ipa->gsi;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!(endpoint->ipa->enabled & BIT(endpoint->endpoint_id)))
|
|
|
|
return;
|
|
|
|
|
2020-09-28 23:04:39 +00:00
|
|
|
if (!endpoint->toward_ipa) {
|
2020-03-06 04:28:24 +00:00
|
|
|
ipa_endpoint_replenish_disable(endpoint);
|
2020-05-04 23:37:12 +00:00
|
|
|
(void)ipa_endpoint_program_suspend(endpoint, true);
|
2020-09-28 23:04:39 +00:00
|
|
|
}
|
2020-03-06 04:28:24 +00:00
|
|
|
|
2021-08-03 14:00:58 +00:00
|
|
|
ret = gsi_channel_suspend(gsi, endpoint->channel_id);
|
2020-03-06 04:28:24 +00:00
|
|
|
if (ret)
|
|
|
|
dev_err(dev, "error %d suspending channel %u\n", ret,
|
|
|
|
endpoint->channel_id);
|
|
|
|
}
|
|
|
|
|
|
|
|
void ipa_endpoint_resume_one(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
struct device *dev = &endpoint->ipa->pdev->dev;
|
|
|
|
struct gsi *gsi = &endpoint->ipa->gsi;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!(endpoint->ipa->enabled & BIT(endpoint->endpoint_id)))
|
|
|
|
return;
|
|
|
|
|
2020-07-02 11:25:36 +00:00
|
|
|
if (!endpoint->toward_ipa)
|
2020-05-04 23:37:12 +00:00
|
|
|
(void)ipa_endpoint_program_suspend(endpoint, false);
|
2020-03-06 04:28:24 +00:00
|
|
|
|
2021-08-03 14:00:58 +00:00
|
|
|
ret = gsi_channel_resume(gsi, endpoint->channel_id);
|
2020-03-06 04:28:24 +00:00
|
|
|
if (ret)
|
|
|
|
dev_err(dev, "error %d resuming channel %u\n", ret,
|
|
|
|
endpoint->channel_id);
|
|
|
|
else if (!endpoint->toward_ipa)
|
|
|
|
ipa_endpoint_replenish_enable(endpoint);
|
|
|
|
}
|
|
|
|
|
|
|
|
void ipa_endpoint_suspend(struct ipa *ipa)
|
|
|
|
{
|
2020-10-09 20:28:48 +00:00
|
|
|
if (!ipa->setup_complete)
|
|
|
|
return;
|
|
|
|
|
2020-03-06 04:28:24 +00:00
|
|
|
if (ipa->modem_netdev)
|
|
|
|
ipa_modem_suspend(ipa->modem_netdev);
|
|
|
|
|
|
|
|
ipa_endpoint_suspend_one(ipa->name_map[IPA_ENDPOINT_AP_LAN_RX]);
|
|
|
|
ipa_endpoint_suspend_one(ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX]);
|
|
|
|
}
|
|
|
|
|
|
|
|
void ipa_endpoint_resume(struct ipa *ipa)
|
|
|
|
{
|
2020-10-09 20:28:48 +00:00
|
|
|
if (!ipa->setup_complete)
|
|
|
|
return;
|
|
|
|
|
2020-03-06 04:28:24 +00:00
|
|
|
ipa_endpoint_resume_one(ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX]);
|
|
|
|
ipa_endpoint_resume_one(ipa->name_map[IPA_ENDPOINT_AP_LAN_RX]);
|
|
|
|
|
|
|
|
if (ipa->modem_netdev)
|
|
|
|
ipa_modem_resume(ipa->modem_netdev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ipa_endpoint_setup_one(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
struct gsi *gsi = &endpoint->ipa->gsi;
|
|
|
|
u32 channel_id = endpoint->channel_id;
|
|
|
|
|
|
|
|
/* Only AP endpoints get set up */
|
|
|
|
if (endpoint->ee_id != GSI_EE_AP)
|
|
|
|
return;
|
|
|
|
|
|
|
|
endpoint->trans_tre_max = gsi_channel_trans_tre_max(gsi, channel_id);
|
|
|
|
if (!endpoint->toward_ipa) {
|
|
|
|
/* RX transactions require a single TRE, so the maximum
|
|
|
|
* backlog is the same as the maximum outstanding TREs.
|
|
|
|
*/
|
|
|
|
endpoint->replenish_enabled = false;
|
|
|
|
atomic_set(&endpoint->replenish_saved,
|
|
|
|
gsi_channel_tre_max(gsi, endpoint->channel_id));
|
|
|
|
atomic_set(&endpoint->replenish_backlog, 0);
|
|
|
|
INIT_DELAYED_WORK(&endpoint->replenish_work,
|
|
|
|
ipa_endpoint_replenish_work);
|
|
|
|
}
|
|
|
|
|
|
|
|
ipa_endpoint_program(endpoint);
|
|
|
|
|
|
|
|
endpoint->ipa->set_up |= BIT(endpoint->endpoint_id);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ipa_endpoint_teardown_one(struct ipa_endpoint *endpoint)
|
|
|
|
{
|
|
|
|
endpoint->ipa->set_up &= ~BIT(endpoint->endpoint_id);
|
|
|
|
|
|
|
|
if (!endpoint->toward_ipa)
|
|
|
|
cancel_delayed_work_sync(&endpoint->replenish_work);
|
|
|
|
|
|
|
|
ipa_endpoint_reset(endpoint);
|
|
|
|
}
|
|
|
|
|
|
|
|
void ipa_endpoint_setup(struct ipa *ipa)
|
|
|
|
{
|
|
|
|
u32 initialized = ipa->initialized;
|
|
|
|
|
|
|
|
ipa->set_up = 0;
|
|
|
|
while (initialized) {
|
|
|
|
u32 endpoint_id = __ffs(initialized);
|
|
|
|
|
|
|
|
initialized ^= BIT(endpoint_id);
|
|
|
|
|
|
|
|
ipa_endpoint_setup_one(&ipa->endpoint[endpoint_id]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void ipa_endpoint_teardown(struct ipa *ipa)
|
|
|
|
{
|
|
|
|
u32 set_up = ipa->set_up;
|
|
|
|
|
|
|
|
while (set_up) {
|
|
|
|
u32 endpoint_id = __fls(set_up);
|
|
|
|
|
|
|
|
set_up ^= BIT(endpoint_id);
|
|
|
|
|
|
|
|
ipa_endpoint_teardown_one(&ipa->endpoint[endpoint_id]);
|
|
|
|
}
|
|
|
|
ipa->set_up = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int ipa_endpoint_config(struct ipa *ipa)
|
|
|
|
{
|
|
|
|
struct device *dev = &ipa->pdev->dev;
|
|
|
|
u32 initialized;
|
|
|
|
u32 rx_base;
|
|
|
|
u32 rx_mask;
|
|
|
|
u32 tx_mask;
|
|
|
|
int ret = 0;
|
|
|
|
u32 max;
|
|
|
|
u32 val;
|
|
|
|
|
2021-06-21 17:56:25 +00:00
|
|
|
/* Prior to IPAv3.5, the FLAVOR_0 register was not supported.
|
|
|
|
* Furthermore, the endpoints were not grouped such that TX
|
|
|
|
* endpoint numbers started with 0 and RX endpoints had numbers
|
|
|
|
* higher than all TX endpoints, so we can't do the simple
|
|
|
|
* direction check used for newer hardware below.
|
|
|
|
*
|
|
|
|
* For hardware that doesn't support the FLAVOR_0 register,
|
|
|
|
* just set the available mask to support any endpoint, and
|
|
|
|
* assume the configuration is valid.
|
|
|
|
*/
|
|
|
|
if (ipa->version < IPA_VERSION_3_5) {
|
|
|
|
ipa->available = ~0;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-03-06 04:28:24 +00:00
|
|
|
/* Find out about the endpoints supplied by the hardware, and ensure
|
|
|
|
* the highest one doesn't exceed the number we support.
|
|
|
|
*/
|
|
|
|
val = ioread32(ipa->reg_virt + IPA_REG_FLAVOR_0_OFFSET);
|
|
|
|
|
|
|
|
/* Our RX is an IPA producer */
|
2020-11-16 23:38:05 +00:00
|
|
|
rx_base = u32_get_bits(val, IPA_PROD_LOWEST_FMASK);
|
|
|
|
max = rx_base + u32_get_bits(val, IPA_MAX_PROD_PIPES_FMASK);
|
2020-03-06 04:28:24 +00:00
|
|
|
if (max > IPA_ENDPOINT_MAX) {
|
|
|
|
dev_err(dev, "too many endpoints (%u > %u)\n",
|
|
|
|
max, IPA_ENDPOINT_MAX);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
rx_mask = GENMASK(max - 1, rx_base);
|
|
|
|
|
|
|
|
/* Our TX is an IPA consumer */
|
2020-11-16 23:38:05 +00:00
|
|
|
max = u32_get_bits(val, IPA_MAX_CONS_PIPES_FMASK);
|
2020-03-06 04:28:24 +00:00
|
|
|
tx_mask = GENMASK(max - 1, 0);
|
|
|
|
|
|
|
|
ipa->available = rx_mask | tx_mask;
|
|
|
|
|
|
|
|
/* Check for initialized endpoints not supported by the hardware */
|
|
|
|
if (ipa->initialized & ~ipa->available) {
|
|
|
|
dev_err(dev, "unavailable endpoint id(s) 0x%08x\n",
|
|
|
|
ipa->initialized & ~ipa->available);
|
|
|
|
ret = -EINVAL; /* Report other errors too */
|
|
|
|
}
|
|
|
|
|
|
|
|
initialized = ipa->initialized;
|
|
|
|
while (initialized) {
|
|
|
|
u32 endpoint_id = __ffs(initialized);
|
|
|
|
struct ipa_endpoint *endpoint;
|
|
|
|
|
|
|
|
initialized ^= BIT(endpoint_id);
|
|
|
|
|
|
|
|
/* Make sure it's pointing in the right direction */
|
|
|
|
endpoint = &ipa->endpoint[endpoint_id];
|
2021-04-09 18:07:22 +00:00
|
|
|
if ((endpoint_id < rx_base) != endpoint->toward_ipa) {
|
2020-03-06 04:28:24 +00:00
|
|
|
dev_err(dev, "endpoint id %u wrong direction\n",
|
|
|
|
endpoint_id);
|
|
|
|
ret = -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
void ipa_endpoint_deconfig(struct ipa *ipa)
|
|
|
|
{
|
|
|
|
ipa->available = 0; /* Nothing more to do */
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ipa_endpoint_init_one(struct ipa *ipa, enum ipa_endpoint_name name,
|
|
|
|
const struct ipa_gsi_endpoint_data *data)
|
|
|
|
{
|
|
|
|
struct ipa_endpoint *endpoint;
|
|
|
|
|
|
|
|
endpoint = &ipa->endpoint[data->endpoint_id];
|
|
|
|
|
|
|
|
if (data->ee_id == GSI_EE_AP)
|
|
|
|
ipa->channel_map[data->channel_id] = endpoint;
|
|
|
|
ipa->name_map[name] = endpoint;
|
|
|
|
|
|
|
|
endpoint->ipa = ipa;
|
|
|
|
endpoint->ee_id = data->ee_id;
|
|
|
|
endpoint->channel_id = data->channel_id;
|
|
|
|
endpoint->endpoint_id = data->endpoint_id;
|
|
|
|
endpoint->toward_ipa = data->toward_ipa;
|
|
|
|
endpoint->data = &data->endpoint.config;
|
|
|
|
|
|
|
|
ipa->initialized |= BIT(endpoint->endpoint_id);
|
|
|
|
}
|
|
|
|
|
2021-04-09 18:07:22 +00:00
|
|
|
static void ipa_endpoint_exit_one(struct ipa_endpoint *endpoint)
|
2020-03-06 04:28:24 +00:00
|
|
|
{
|
|
|
|
endpoint->ipa->initialized &= ~BIT(endpoint->endpoint_id);
|
|
|
|
|
|
|
|
memset(endpoint, 0, sizeof(*endpoint));
|
|
|
|
}
|
|
|
|
|
|
|
|
void ipa_endpoint_exit(struct ipa *ipa)
|
|
|
|
{
|
|
|
|
u32 initialized = ipa->initialized;
|
|
|
|
|
|
|
|
while (initialized) {
|
|
|
|
u32 endpoint_id = __fls(initialized);
|
|
|
|
|
|
|
|
initialized ^= BIT(endpoint_id);
|
|
|
|
|
|
|
|
ipa_endpoint_exit_one(&ipa->endpoint[endpoint_id]);
|
|
|
|
}
|
|
|
|
memset(ipa->name_map, 0, sizeof(ipa->name_map));
|
|
|
|
memset(ipa->channel_map, 0, sizeof(ipa->channel_map));
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Returns a bitmask of endpoints that support filtering, or 0 on error */
|
|
|
|
u32 ipa_endpoint_init(struct ipa *ipa, u32 count,
|
|
|
|
const struct ipa_gsi_endpoint_data *data)
|
|
|
|
{
|
|
|
|
enum ipa_endpoint_name name;
|
|
|
|
u32 filter_map;
|
|
|
|
|
|
|
|
if (!ipa_endpoint_data_valid(ipa, count, data))
|
|
|
|
return 0; /* Error */
|
|
|
|
|
|
|
|
ipa->initialized = 0;
|
|
|
|
|
|
|
|
filter_map = 0;
|
|
|
|
for (name = 0; name < count; name++, data++) {
|
|
|
|
if (ipa_gsi_endpoint_data_empty(data))
|
|
|
|
continue; /* Skip over empty slots */
|
|
|
|
|
|
|
|
ipa_endpoint_init_one(ipa, name, data);
|
|
|
|
|
|
|
|
if (data->endpoint.filter_support)
|
|
|
|
filter_map |= BIT(data->endpoint_id);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!ipa_filter_map_valid(ipa, filter_map))
|
|
|
|
goto err_endpoint_exit;
|
|
|
|
|
|
|
|
return filter_map; /* Non-zero bitmask */
|
|
|
|
|
|
|
|
err_endpoint_exit:
|
|
|
|
ipa_endpoint_exit(ipa);
|
|
|
|
|
|
|
|
return 0; /* Error */
|
|
|
|
}
|