2019-06-04 08:11:33 +00:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2005-04-16 22:20:36 +00:00
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/*
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* linux/arch/arm/kernel/iwmmxt.S
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*
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* XScale iWMMXt (Concan) context switching and handling
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*
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* Initial code:
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* Copyright (c) 2003, Intel Corporation
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*
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* Full lazy switching support, optimizations and more, by Nicolas Pitre
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* Copyright (c) 2003-2004, MontaVista Software, Inc.
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*/
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#include <linux/linkage.h>
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#include <asm/ptrace.h>
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#include <asm/thread_info.h>
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2005-09-09 19:08:59 +00:00
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#include <asm/asm-offsets.h>
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2014-04-22 15:14:27 +00:00
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#include <asm/assembler.h>
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2020-11-17 22:11:36 +00:00
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#include "iwmmxt.h"
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2005-04-16 22:20:36 +00:00
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2014-04-24 21:54:58 +00:00
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#if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
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2010-11-24 03:54:25 +00:00
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#define PJ4(code...) code
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#define XSC(code...)
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2014-04-24 21:54:58 +00:00
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#elif defined(CONFIG_CPU_MOHAWK) || \
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defined(CONFIG_CPU_XSC3) || \
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defined(CONFIG_CPU_XSCALE)
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2010-11-24 03:54:25 +00:00
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#define PJ4(code...)
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#define XSC(code...) code
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2014-04-24 21:54:58 +00:00
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#else
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#error "Unsupported iWMMXt architecture"
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2010-11-24 03:54:25 +00:00
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#endif
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2005-04-16 22:20:36 +00:00
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#define MMX_WR0 (0x00)
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#define MMX_WR1 (0x08)
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#define MMX_WR2 (0x10)
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#define MMX_WR3 (0x18)
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#define MMX_WR4 (0x20)
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#define MMX_WR5 (0x28)
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#define MMX_WR6 (0x30)
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#define MMX_WR7 (0x38)
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#define MMX_WR8 (0x40)
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#define MMX_WR9 (0x48)
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#define MMX_WR10 (0x50)
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#define MMX_WR11 (0x58)
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#define MMX_WR12 (0x60)
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#define MMX_WR13 (0x68)
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#define MMX_WR14 (0x70)
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#define MMX_WR15 (0x78)
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#define MMX_WCSSF (0x80)
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#define MMX_WCASF (0x84)
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#define MMX_WCGR0 (0x88)
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#define MMX_WCGR1 (0x8C)
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#define MMX_WCGR2 (0x90)
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#define MMX_WCGR3 (0x94)
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#define MMX_SIZE (0x98)
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.text
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2014-11-25 12:31:46 +00:00
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.arm
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2005-04-16 22:20:36 +00:00
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/*
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* Lazy switching of Concan coprocessor context
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*
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* r10 = struct thread_info pointer
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* r9 = ret_from_exception
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* lr = undefined instr exit
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*
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2014-04-22 15:14:29 +00:00
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* called from prefetch exception handler with interrupts enabled
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2005-04-16 22:20:36 +00:00
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*/
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ENTRY(iwmmxt_task_enable)
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2014-04-22 15:14:27 +00:00
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inc_preempt_count r10, r3
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2005-04-16 22:20:36 +00:00
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2010-11-24 03:54:25 +00:00
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XSC(mrc p15, 0, r2, c15, c1, 0)
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PJ4(mrc p15, 0, r2, c1, c0, 2)
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@ CP0 and CP1 accessible?
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XSC(tst r2, #0x3)
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PJ4(tst r2, #0xf)
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2014-04-22 15:14:27 +00:00
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bne 4f @ if so no business here
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2010-11-24 03:54:25 +00:00
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@ enable access to CP0 and CP1
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XSC(orr r2, r2, #0x3)
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XSC(mcr p15, 0, r2, c15, c1, 0)
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PJ4(orr r2, r2, #0xf)
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PJ4(mcr p15, 0, r2, c1, c0, 2)
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2005-04-16 22:20:36 +00:00
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ldr r3, =concan_owner
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add r0, r10, #TI_IWMMXT_STATE @ get task Concan save area
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ldr r2, [sp, #60] @ current task pc value
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ldr r1, [r3] @ get current Concan owner
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str r0, [r3] @ this task now owns Concan regs
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sub r2, r2, #4 @ adjust pc back
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str r2, [sp, #60]
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mrc p15, 0, r2, c2, c0, 0
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mov r2, r2 @ cpwait
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ARM: 8100/1: Fix preemption disable in iwmmxt_task_enable()
commit 431a84b1a4f7d1a0085d5b91330c5053cc8e8b12
("ARM: 8034/1: Disable preemption in iwmmxt_task_enable()")
introduced macros {inc,dec}_preempt_count to iwmmxt_task_enable
to make it run with preemption disabled.
Unfortunately, other functions in iwmmxt.S also use concan_{save,dump,load}
sections located in iwmmxt_task_enable() to deal with iWMMXt coprocessor.
This causes an unbalanced preempt_count due to excessive dec_preempt_count
and destroyed return addresses in callers of concan_ labels due to a register
collision:
Linux version 3.16.0-rc3-00062-gd92a333-dirty (jef@armhf) (gcc version 4.8.3 (Debian 4.8.3-4) ) #5 PREEMPT Thu Jul 3 19:46:39 CEST 2014
CPU: ARMv7 Processor [560f5815] revision 5 (ARMv7), cr=10c5387d
CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
Machine model: SolidRun CuBox
...
PJ4 iWMMXt v2 coprocessor enabled.
...
Unable to handle kernel paging request at virtual address fffffffe
pgd = bb25c000
[fffffffe] *pgd=3bfde821, *pte=00000000, *ppte=00000000
Internal error: Oops: 80000007 [#1] PREEMPT ARM
Modules linked in:
CPU: 0 PID: 62 Comm: startpar Not tainted 3.16.0-rc3-00062-gd92a333-dirty #5
task: bb230b80 ti: bb256000 task.ti: bb256000
PC is at 0xfffffffe
LR is at iwmmxt_task_copy+0x44/0x4c
pc : [<fffffffe>] lr : [<800130ac>] psr: 40000033
sp : bb257de8 ip : 00000013 fp : bb257ea4
r10: bb256000 r9 : fffffdfe r8 : 76e898e6
r7 : bb257ec8 r6 : bb256000 r5 : 7ea12760 r4 : 000000a0
r3 : ffffffff r2 : 00000003 r1 : bb257df8 r0 : 00000000
Flags: nZcv IRQs on FIQs on Mode SVC_32 ISA Thumb Segment user
Control: 10c5387d Table: 3b25c019 DAC: 00000015
Process startpar (pid: 62, stack limit = 0xbb256248)
This patch fixes the issue by moving concan_{save,dump,load} into separate
code sections and make iwmmxt_task_enable() call them in the same way the
other functions use concan_ symbols. The test for valid ownership is moved
to concan_save and is safe for the other user of it, iwmmxt_task_disable().
The register collision is also resolved by moving concan_ symbols as
{inc,dec}_preempt_count are now local to iwmmxt_task_enable().
Fixes: 431a84b1a4f7 ("ARM: 8034/1: Disable preemption in iwmmxt_task_enable()")
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Jean-Francois Moine <moinejf@free.fr>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-07-14 15:23:29 +00:00
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bl concan_save
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2005-04-16 22:20:36 +00:00
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ARM: 8100/1: Fix preemption disable in iwmmxt_task_enable()
commit 431a84b1a4f7d1a0085d5b91330c5053cc8e8b12
("ARM: 8034/1: Disable preemption in iwmmxt_task_enable()")
introduced macros {inc,dec}_preempt_count to iwmmxt_task_enable
to make it run with preemption disabled.
Unfortunately, other functions in iwmmxt.S also use concan_{save,dump,load}
sections located in iwmmxt_task_enable() to deal with iWMMXt coprocessor.
This causes an unbalanced preempt_count due to excessive dec_preempt_count
and destroyed return addresses in callers of concan_ labels due to a register
collision:
Linux version 3.16.0-rc3-00062-gd92a333-dirty (jef@armhf) (gcc version 4.8.3 (Debian 4.8.3-4) ) #5 PREEMPT Thu Jul 3 19:46:39 CEST 2014
CPU: ARMv7 Processor [560f5815] revision 5 (ARMv7), cr=10c5387d
CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
Machine model: SolidRun CuBox
...
PJ4 iWMMXt v2 coprocessor enabled.
...
Unable to handle kernel paging request at virtual address fffffffe
pgd = bb25c000
[fffffffe] *pgd=3bfde821, *pte=00000000, *ppte=00000000
Internal error: Oops: 80000007 [#1] PREEMPT ARM
Modules linked in:
CPU: 0 PID: 62 Comm: startpar Not tainted 3.16.0-rc3-00062-gd92a333-dirty #5
task: bb230b80 ti: bb256000 task.ti: bb256000
PC is at 0xfffffffe
LR is at iwmmxt_task_copy+0x44/0x4c
pc : [<fffffffe>] lr : [<800130ac>] psr: 40000033
sp : bb257de8 ip : 00000013 fp : bb257ea4
r10: bb256000 r9 : fffffdfe r8 : 76e898e6
r7 : bb257ec8 r6 : bb256000 r5 : 7ea12760 r4 : 000000a0
r3 : ffffffff r2 : 00000003 r1 : bb257df8 r0 : 00000000
Flags: nZcv IRQs on FIQs on Mode SVC_32 ISA Thumb Segment user
Control: 10c5387d Table: 3b25c019 DAC: 00000015
Process startpar (pid: 62, stack limit = 0xbb256248)
This patch fixes the issue by moving concan_{save,dump,load} into separate
code sections and make iwmmxt_task_enable() call them in the same way the
other functions use concan_ symbols. The test for valid ownership is moved
to concan_save and is safe for the other user of it, iwmmxt_task_disable().
The register collision is also resolved by moving concan_ symbols as
{inc,dec}_preempt_count are now local to iwmmxt_task_enable().
Fixes: 431a84b1a4f7 ("ARM: 8034/1: Disable preemption in iwmmxt_task_enable()")
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Jean-Francois Moine <moinejf@free.fr>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-07-14 15:23:29 +00:00
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#ifdef CONFIG_PREEMPT_COUNT
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get_thread_info r10
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#endif
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4: dec_preempt_count r10, r3
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2014-08-05 09:27:13 +00:00
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ret r9 @ normal exit from exception
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2005-04-16 22:20:36 +00:00
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concan_save:
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ARM: 8100/1: Fix preemption disable in iwmmxt_task_enable()
commit 431a84b1a4f7d1a0085d5b91330c5053cc8e8b12
("ARM: 8034/1: Disable preemption in iwmmxt_task_enable()")
introduced macros {inc,dec}_preempt_count to iwmmxt_task_enable
to make it run with preemption disabled.
Unfortunately, other functions in iwmmxt.S also use concan_{save,dump,load}
sections located in iwmmxt_task_enable() to deal with iWMMXt coprocessor.
This causes an unbalanced preempt_count due to excessive dec_preempt_count
and destroyed return addresses in callers of concan_ labels due to a register
collision:
Linux version 3.16.0-rc3-00062-gd92a333-dirty (jef@armhf) (gcc version 4.8.3 (Debian 4.8.3-4) ) #5 PREEMPT Thu Jul 3 19:46:39 CEST 2014
CPU: ARMv7 Processor [560f5815] revision 5 (ARMv7), cr=10c5387d
CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
Machine model: SolidRun CuBox
...
PJ4 iWMMXt v2 coprocessor enabled.
...
Unable to handle kernel paging request at virtual address fffffffe
pgd = bb25c000
[fffffffe] *pgd=3bfde821, *pte=00000000, *ppte=00000000
Internal error: Oops: 80000007 [#1] PREEMPT ARM
Modules linked in:
CPU: 0 PID: 62 Comm: startpar Not tainted 3.16.0-rc3-00062-gd92a333-dirty #5
task: bb230b80 ti: bb256000 task.ti: bb256000
PC is at 0xfffffffe
LR is at iwmmxt_task_copy+0x44/0x4c
pc : [<fffffffe>] lr : [<800130ac>] psr: 40000033
sp : bb257de8 ip : 00000013 fp : bb257ea4
r10: bb256000 r9 : fffffdfe r8 : 76e898e6
r7 : bb257ec8 r6 : bb256000 r5 : 7ea12760 r4 : 000000a0
r3 : ffffffff r2 : 00000003 r1 : bb257df8 r0 : 00000000
Flags: nZcv IRQs on FIQs on Mode SVC_32 ISA Thumb Segment user
Control: 10c5387d Table: 3b25c019 DAC: 00000015
Process startpar (pid: 62, stack limit = 0xbb256248)
This patch fixes the issue by moving concan_{save,dump,load} into separate
code sections and make iwmmxt_task_enable() call them in the same way the
other functions use concan_ symbols. The test for valid ownership is moved
to concan_save and is safe for the other user of it, iwmmxt_task_disable().
The register collision is also resolved by moving concan_ symbols as
{inc,dec}_preempt_count are now local to iwmmxt_task_enable().
Fixes: 431a84b1a4f7 ("ARM: 8034/1: Disable preemption in iwmmxt_task_enable()")
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Jean-Francois Moine <moinejf@free.fr>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-07-14 15:23:29 +00:00
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teq r1, #0 @ test for last ownership
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beq concan_load @ no owner, skip save
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2005-04-16 22:20:36 +00:00
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tmrc r2, wCon
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@ CUP? wCx
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tst r2, #0x1
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beq 1f
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concan_dump:
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2020-11-17 22:11:36 +00:00
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wstrw wCSSF, r1, MMX_WCSSF
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wstrw wCASF, r1, MMX_WCASF
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wstrw wCGR0, r1, MMX_WCGR0
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wstrw wCGR1, r1, MMX_WCGR1
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wstrw wCGR2, r1, MMX_WCGR2
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wstrw wCGR3, r1, MMX_WCGR3
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2005-04-16 22:20:36 +00:00
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1: @ MUP? wRn
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tst r2, #0x2
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beq 2f
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2020-11-17 22:11:36 +00:00
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wstrd wR0, r1, MMX_WR0
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wstrd wR1, r1, MMX_WR1
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wstrd wR2, r1, MMX_WR2
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wstrd wR3, r1, MMX_WR3
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wstrd wR4, r1, MMX_WR4
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wstrd wR5, r1, MMX_WR5
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wstrd wR6, r1, MMX_WR6
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wstrd wR7, r1, MMX_WR7
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wstrd wR8, r1, MMX_WR8
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wstrd wR9, r1, MMX_WR9
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wstrd wR10, r1, MMX_WR10
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wstrd wR11, r1, MMX_WR11
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wstrd wR12, r1, MMX_WR12
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wstrd wR13, r1, MMX_WR13
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wstrd wR14, r1, MMX_WR14
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wstrd wR15, r1, MMX_WR15
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2005-04-16 22:20:36 +00:00
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2: teq r0, #0 @ anything to load?
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2014-08-05 09:27:13 +00:00
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reteq lr @ if not, return
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2005-04-16 22:20:36 +00:00
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concan_load:
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@ Load wRn
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2020-11-17 22:11:36 +00:00
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wldrd wR0, r0, MMX_WR0
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wldrd wR1, r0, MMX_WR1
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wldrd wR2, r0, MMX_WR2
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wldrd wR3, r0, MMX_WR3
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wldrd wR4, r0, MMX_WR4
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wldrd wR5, r0, MMX_WR5
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wldrd wR6, r0, MMX_WR6
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wldrd wR7, r0, MMX_WR7
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wldrd wR8, r0, MMX_WR8
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wldrd wR9, r0, MMX_WR9
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wldrd wR10, r0, MMX_WR10
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wldrd wR11, r0, MMX_WR11
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wldrd wR12, r0, MMX_WR12
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wldrd wR13, r0, MMX_WR13
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wldrd wR14, r0, MMX_WR14
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wldrd wR15, r0, MMX_WR15
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2005-04-16 22:20:36 +00:00
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@ Load wCx
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2020-11-17 22:11:36 +00:00
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wldrw wCSSF, r0, MMX_WCSSF
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wldrw wCASF, r0, MMX_WCASF
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wldrw wCGR0, r0, MMX_WCGR0
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wldrw wCGR1, r0, MMX_WCGR1
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wldrw wCGR2, r0, MMX_WCGR2
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wldrw wCGR3, r0, MMX_WCGR3
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2005-04-16 22:20:36 +00:00
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@ clear CUP/MUP (only if r1 != 0)
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teq r1, #0
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mov r2, #0
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2014-08-05 09:27:13 +00:00
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reteq lr
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2014-04-22 15:14:27 +00:00
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ARM: 8100/1: Fix preemption disable in iwmmxt_task_enable()
commit 431a84b1a4f7d1a0085d5b91330c5053cc8e8b12
("ARM: 8034/1: Disable preemption in iwmmxt_task_enable()")
introduced macros {inc,dec}_preempt_count to iwmmxt_task_enable
to make it run with preemption disabled.
Unfortunately, other functions in iwmmxt.S also use concan_{save,dump,load}
sections located in iwmmxt_task_enable() to deal with iWMMXt coprocessor.
This causes an unbalanced preempt_count due to excessive dec_preempt_count
and destroyed return addresses in callers of concan_ labels due to a register
collision:
Linux version 3.16.0-rc3-00062-gd92a333-dirty (jef@armhf) (gcc version 4.8.3 (Debian 4.8.3-4) ) #5 PREEMPT Thu Jul 3 19:46:39 CEST 2014
CPU: ARMv7 Processor [560f5815] revision 5 (ARMv7), cr=10c5387d
CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
Machine model: SolidRun CuBox
...
PJ4 iWMMXt v2 coprocessor enabled.
...
Unable to handle kernel paging request at virtual address fffffffe
pgd = bb25c000
[fffffffe] *pgd=3bfde821, *pte=00000000, *ppte=00000000
Internal error: Oops: 80000007 [#1] PREEMPT ARM
Modules linked in:
CPU: 0 PID: 62 Comm: startpar Not tainted 3.16.0-rc3-00062-gd92a333-dirty #5
task: bb230b80 ti: bb256000 task.ti: bb256000
PC is at 0xfffffffe
LR is at iwmmxt_task_copy+0x44/0x4c
pc : [<fffffffe>] lr : [<800130ac>] psr: 40000033
sp : bb257de8 ip : 00000013 fp : bb257ea4
r10: bb256000 r9 : fffffdfe r8 : 76e898e6
r7 : bb257ec8 r6 : bb256000 r5 : 7ea12760 r4 : 000000a0
r3 : ffffffff r2 : 00000003 r1 : bb257df8 r0 : 00000000
Flags: nZcv IRQs on FIQs on Mode SVC_32 ISA Thumb Segment user
Control: 10c5387d Table: 3b25c019 DAC: 00000015
Process startpar (pid: 62, stack limit = 0xbb256248)
This patch fixes the issue by moving concan_{save,dump,load} into separate
code sections and make iwmmxt_task_enable() call them in the same way the
other functions use concan_ symbols. The test for valid ownership is moved
to concan_save and is safe for the other user of it, iwmmxt_task_disable().
The register collision is also resolved by moving concan_ symbols as
{inc,dec}_preempt_count are now local to iwmmxt_task_enable().
Fixes: 431a84b1a4f7 ("ARM: 8034/1: Disable preemption in iwmmxt_task_enable()")
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Jean-Francois Moine <moinejf@free.fr>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-07-14 15:23:29 +00:00
|
|
|
tmcr wCon, r2
|
2014-06-30 15:29:12 +00:00
|
|
|
ret lr
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2014-11-25 12:31:46 +00:00
|
|
|
ENDPROC(iwmmxt_task_enable)
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/*
|
|
|
|
* Back up Concan regs to save area and disable access to them
|
|
|
|
* (mainly for gdb or sleep mode usage)
|
|
|
|
*
|
|
|
|
* r0 = struct thread_info pointer of target task or NULL for any
|
|
|
|
*/
|
|
|
|
|
|
|
|
ENTRY(iwmmxt_task_disable)
|
|
|
|
|
|
|
|
stmfd sp!, {r4, lr}
|
|
|
|
|
|
|
|
mrs ip, cpsr
|
|
|
|
orr r2, ip, #PSR_I_BIT @ disable interrupts
|
|
|
|
msr cpsr_c, r2
|
|
|
|
|
|
|
|
ldr r3, =concan_owner
|
|
|
|
add r2, r0, #TI_IWMMXT_STATE @ get task Concan save area
|
|
|
|
ldr r1, [r3] @ get current Concan owner
|
|
|
|
teq r1, #0 @ any current owner?
|
|
|
|
beq 1f @ no: quit
|
|
|
|
teq r0, #0 @ any owner?
|
|
|
|
teqne r1, r2 @ or specified one?
|
|
|
|
bne 1f @ no: quit
|
|
|
|
|
2010-11-24 03:54:25 +00:00
|
|
|
@ enable access to CP0 and CP1
|
|
|
|
XSC(mrc p15, 0, r4, c15, c1, 0)
|
ARM: pxa: fix logic error in PJ4 iWMMXt handling
This got added in:
commit ef6c84454f8567d4968c210d7d194fb711ed3739
Author: Haojian Zhuang <haojian.zhuang@marvell.com>
Date: Wed Nov 24 11:54:25 2010 +0800
ARM: pxa: add iwmmx support for PJ4
which does:
- mrc p15, 0, r2, c15, c1, 0
- orr r2, r2, #0x3 @ enable access to CP0 and CP1
- mcr p15, 0, r2, c15, c1, 0
+ @ enable access to CP0 and CP1
+ XSC(mrc p15, 0, r2, c15, c1, 0)
+ XSC(orr r2, r2, #0x3)
+ XSC(mcr p15, 0, r2, c15, c1, 0)
but then later does:
- mrc p15, 0, r4, c15, c1, 0
- orr r4, r4, #0x3 @ enable access to CP0 and CP1
- mcr p15, 0, r4, c15, c1, 0
+ @ enable access to CP0 and CP1
+ XSC(mrc p15, 0, r4, c15, c1, 0)
+ XSC(orr r4, r4, #0xf)
+ XSC(mcr p15, 0, r4, c15, c1, 0)
Signed-off-by: Lennert Buytenhek <buytenh@laptop.org>
Acked-by Haojian <haojian.zhuang@gmail.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2011-08-11 01:56:06 +00:00
|
|
|
XSC(orr r4, r4, #0x3)
|
2010-11-24 03:54:25 +00:00
|
|
|
XSC(mcr p15, 0, r4, c15, c1, 0)
|
|
|
|
PJ4(mrc p15, 0, r4, c1, c0, 2)
|
ARM: pxa: fix logic error in PJ4 iWMMXt handling
This got added in:
commit ef6c84454f8567d4968c210d7d194fb711ed3739
Author: Haojian Zhuang <haojian.zhuang@marvell.com>
Date: Wed Nov 24 11:54:25 2010 +0800
ARM: pxa: add iwmmx support for PJ4
which does:
- mrc p15, 0, r2, c15, c1, 0
- orr r2, r2, #0x3 @ enable access to CP0 and CP1
- mcr p15, 0, r2, c15, c1, 0
+ @ enable access to CP0 and CP1
+ XSC(mrc p15, 0, r2, c15, c1, 0)
+ XSC(orr r2, r2, #0x3)
+ XSC(mcr p15, 0, r2, c15, c1, 0)
but then later does:
- mrc p15, 0, r4, c15, c1, 0
- orr r4, r4, #0x3 @ enable access to CP0 and CP1
- mcr p15, 0, r4, c15, c1, 0
+ @ enable access to CP0 and CP1
+ XSC(mrc p15, 0, r4, c15, c1, 0)
+ XSC(orr r4, r4, #0xf)
+ XSC(mcr p15, 0, r4, c15, c1, 0)
Signed-off-by: Lennert Buytenhek <buytenh@laptop.org>
Acked-by Haojian <haojian.zhuang@gmail.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2011-08-11 01:56:06 +00:00
|
|
|
PJ4(orr r4, r4, #0xf)
|
2010-11-24 03:54:25 +00:00
|
|
|
PJ4(mcr p15, 0, r4, c1, c0, 2)
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
mov r0, #0 @ nothing to load
|
|
|
|
str r0, [r3] @ no more current owner
|
|
|
|
mrc p15, 0, r2, c2, c0, 0
|
|
|
|
mov r2, r2 @ cpwait
|
|
|
|
bl concan_save
|
|
|
|
|
2010-11-24 03:54:25 +00:00
|
|
|
@ disable access to CP0 and CP1
|
|
|
|
XSC(bic r4, r4, #0x3)
|
|
|
|
XSC(mcr p15, 0, r4, c15, c1, 0)
|
|
|
|
PJ4(bic r4, r4, #0xf)
|
|
|
|
PJ4(mcr p15, 0, r4, c1, c0, 2)
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
mrc p15, 0, r2, c2, c0, 0
|
|
|
|
mov r2, r2 @ cpwait
|
|
|
|
|
|
|
|
1: msr cpsr_c, ip @ restore interrupt mode
|
|
|
|
ldmfd sp!, {r4, pc}
|
|
|
|
|
2014-11-25 12:31:46 +00:00
|
|
|
ENDPROC(iwmmxt_task_disable)
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/*
|
|
|
|
* Copy Concan state to given memory address
|
|
|
|
*
|
|
|
|
* r0 = struct thread_info pointer of target task
|
|
|
|
* r1 = memory address where to store Concan state
|
|
|
|
*
|
|
|
|
* this is called mainly in the creation of signal stack frames
|
|
|
|
*/
|
|
|
|
|
|
|
|
ENTRY(iwmmxt_task_copy)
|
|
|
|
|
|
|
|
mrs ip, cpsr
|
|
|
|
orr r2, ip, #PSR_I_BIT @ disable interrupts
|
|
|
|
msr cpsr_c, r2
|
|
|
|
|
|
|
|
ldr r3, =concan_owner
|
|
|
|
add r2, r0, #TI_IWMMXT_STATE @ get task Concan save area
|
|
|
|
ldr r3, [r3] @ get current Concan owner
|
|
|
|
teq r2, r3 @ does this task own it...
|
|
|
|
beq 1f
|
|
|
|
|
|
|
|
@ current Concan values are in the task save area
|
|
|
|
msr cpsr_c, ip @ restore interrupt mode
|
|
|
|
mov r0, r1
|
|
|
|
mov r1, r2
|
|
|
|
mov r2, #MMX_SIZE
|
|
|
|
b memcpy
|
|
|
|
|
|
|
|
1: @ this task owns Concan regs -- grab a copy from there
|
|
|
|
mov r0, #0 @ nothing to load
|
|
|
|
mov r2, #3 @ save all regs
|
|
|
|
mov r3, lr @ preserve return address
|
|
|
|
bl concan_dump
|
|
|
|
msr cpsr_c, ip @ restore interrupt mode
|
2014-06-30 15:29:12 +00:00
|
|
|
ret r3
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2014-11-25 12:31:46 +00:00
|
|
|
ENDPROC(iwmmxt_task_copy)
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/*
|
|
|
|
* Restore Concan state from given memory address
|
|
|
|
*
|
|
|
|
* r0 = struct thread_info pointer of target task
|
|
|
|
* r1 = memory address where to get Concan state from
|
|
|
|
*
|
|
|
|
* this is used to restore Concan state when unwinding a signal stack frame
|
|
|
|
*/
|
|
|
|
|
|
|
|
ENTRY(iwmmxt_task_restore)
|
|
|
|
|
|
|
|
mrs ip, cpsr
|
|
|
|
orr r2, ip, #PSR_I_BIT @ disable interrupts
|
|
|
|
msr cpsr_c, r2
|
|
|
|
|
|
|
|
ldr r3, =concan_owner
|
|
|
|
add r2, r0, #TI_IWMMXT_STATE @ get task Concan save area
|
|
|
|
ldr r3, [r3] @ get current Concan owner
|
|
|
|
bic r2, r2, #0x7 @ 64-bit alignment
|
|
|
|
teq r2, r3 @ does this task own it...
|
|
|
|
beq 1f
|
|
|
|
|
|
|
|
@ this task doesn't own Concan regs -- use its save area
|
|
|
|
msr cpsr_c, ip @ restore interrupt mode
|
|
|
|
mov r0, r2
|
|
|
|
mov r2, #MMX_SIZE
|
|
|
|
b memcpy
|
|
|
|
|
|
|
|
1: @ this task owns Concan regs -- load them directly
|
|
|
|
mov r0, r1
|
|
|
|
mov r1, #0 @ don't clear CUP/MUP
|
|
|
|
mov r3, lr @ preserve return address
|
|
|
|
bl concan_load
|
|
|
|
msr cpsr_c, ip @ restore interrupt mode
|
2014-06-30 15:29:12 +00:00
|
|
|
ret r3
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2014-11-25 12:31:46 +00:00
|
|
|
ENDPROC(iwmmxt_task_restore)
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/*
|
|
|
|
* Concan handling on task switch
|
|
|
|
*
|
2006-07-01 18:56:48 +00:00
|
|
|
* r0 = next thread_info pointer
|
2005-04-16 22:20:36 +00:00
|
|
|
*
|
2006-07-01 18:56:48 +00:00
|
|
|
* Called only from the iwmmxt notifier with task preemption disabled.
|
2005-04-16 22:20:36 +00:00
|
|
|
*/
|
|
|
|
ENTRY(iwmmxt_task_switch)
|
|
|
|
|
2010-11-24 03:54:25 +00:00
|
|
|
XSC(mrc p15, 0, r1, c15, c1, 0)
|
|
|
|
PJ4(mrc p15, 0, r1, c1, c0, 2)
|
|
|
|
@ CP0 and CP1 accessible?
|
|
|
|
XSC(tst r1, #0x3)
|
|
|
|
PJ4(tst r1, #0xf)
|
2005-04-16 22:20:36 +00:00
|
|
|
bne 1f @ yes: block them for next task
|
|
|
|
|
2006-07-01 18:56:48 +00:00
|
|
|
ldr r2, =concan_owner
|
|
|
|
add r3, r0, #TI_IWMMXT_STATE @ get next task Concan save area
|
|
|
|
ldr r2, [r2] @ get current Concan owner
|
|
|
|
teq r2, r3 @ next task owns it?
|
2014-06-30 15:29:12 +00:00
|
|
|
retne lr @ no: leave Concan disabled
|
2005-04-16 22:20:36 +00:00
|
|
|
|
ARM: pxa: fix logic error in PJ4 iWMMXt handling
This got added in:
commit ef6c84454f8567d4968c210d7d194fb711ed3739
Author: Haojian Zhuang <haojian.zhuang@marvell.com>
Date: Wed Nov 24 11:54:25 2010 +0800
ARM: pxa: add iwmmx support for PJ4
which does:
- mrc p15, 0, r2, c15, c1, 0
- orr r2, r2, #0x3 @ enable access to CP0 and CP1
- mcr p15, 0, r2, c15, c1, 0
+ @ enable access to CP0 and CP1
+ XSC(mrc p15, 0, r2, c15, c1, 0)
+ XSC(orr r2, r2, #0x3)
+ XSC(mcr p15, 0, r2, c15, c1, 0)
but then later does:
- mrc p15, 0, r4, c15, c1, 0
- orr r4, r4, #0x3 @ enable access to CP0 and CP1
- mcr p15, 0, r4, c15, c1, 0
+ @ enable access to CP0 and CP1
+ XSC(mrc p15, 0, r4, c15, c1, 0)
+ XSC(orr r4, r4, #0xf)
+ XSC(mcr p15, 0, r4, c15, c1, 0)
Signed-off-by: Lennert Buytenhek <buytenh@laptop.org>
Acked-by Haojian <haojian.zhuang@gmail.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2011-08-11 01:56:06 +00:00
|
|
|
1: @ flip Concan access
|
2010-11-24 03:54:25 +00:00
|
|
|
XSC(eor r1, r1, #0x3)
|
|
|
|
XSC(mcr p15, 0, r1, c15, c1, 0)
|
|
|
|
PJ4(eor r1, r1, #0xf)
|
|
|
|
PJ4(mcr p15, 0, r1, c1, c0, 2)
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2006-07-01 18:56:48 +00:00
|
|
|
mrc p15, 0, r1, c2, c0, 0
|
|
|
|
sub pc, lr, r1, lsr #32 @ cpwait and return
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2014-11-25 12:31:46 +00:00
|
|
|
ENDPROC(iwmmxt_task_switch)
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/*
|
|
|
|
* Remove Concan ownership of given task
|
|
|
|
*
|
|
|
|
* r0 = struct thread_info pointer
|
|
|
|
*/
|
|
|
|
ENTRY(iwmmxt_task_release)
|
|
|
|
|
|
|
|
mrs r2, cpsr
|
|
|
|
orr ip, r2, #PSR_I_BIT @ disable interrupts
|
|
|
|
msr cpsr_c, ip
|
|
|
|
ldr r3, =concan_owner
|
|
|
|
add r0, r0, #TI_IWMMXT_STATE @ get task Concan save area
|
|
|
|
ldr r1, [r3] @ get current Concan owner
|
|
|
|
eors r0, r0, r1 @ if equal...
|
|
|
|
streq r0, [r3] @ then clear ownership
|
|
|
|
msr cpsr_c, r2 @ restore interrupts
|
2014-06-30 15:29:12 +00:00
|
|
|
ret lr
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2014-11-25 12:31:46 +00:00
|
|
|
ENDPROC(iwmmxt_task_release)
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
.data
|
2017-07-26 11:49:31 +00:00
|
|
|
.align 2
|
2005-04-16 22:20:36 +00:00
|
|
|
concan_owner:
|
|
|
|
.word 0
|
|
|
|
|