2018-08-30 16:52:54 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2014-06-03 05:26:02 +00:00
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/*
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2018-08-30 16:52:54 +00:00
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* Intel SoC PMIC Driver
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2014-06-03 05:26:02 +00:00
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*
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* Copyright (C) 2012-2014 Intel Corporation. All rights reserved.
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*
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* Author: Yang, Bin <bin.yang@intel.com>
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* Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
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*/
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#ifndef __INTEL_SOC_PMIC_H__
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#define __INTEL_SOC_PMIC_H__
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#include <linux/regmap.h>
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2020-04-16 08:15:42 +00:00
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/**
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* struct intel_soc_pmic - Intel SoC PMIC data
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* @irq: Master interrupt number of the parent PMIC device
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* @regmap: Pointer to the parent PMIC device regmap structure
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* @irq_chip_data: IRQ chip data for the PMIC itself
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* @irq_chip_data_pwrbtn: Chained IRQ chip data for the Power Button
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* @irq_chip_data_tmu: Chained IRQ chip data for the Time Management Unit
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* @irq_chip_data_bcu: Chained IRQ chip data for the Burst Control Unit
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* @irq_chip_data_adc: Chained IRQ chip data for the General Purpose ADC
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* @irq_chip_data_chgr: Chained IRQ chip data for the External Charger
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* @irq_chip_data_crit: Chained IRQ chip data for the Critical Event Handler
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* @dev: Pointer to the parent PMIC device
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* @scu: Pointer to the SCU IPC device data structure
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*/
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2014-06-03 05:26:02 +00:00
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struct intel_soc_pmic {
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int irq;
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struct regmap *regmap;
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struct regmap_irq_chip_data *irq_chip_data;
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2018-08-30 16:52:52 +00:00
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struct regmap_irq_chip_data *irq_chip_data_pwrbtn;
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2016-11-07 20:11:47 +00:00
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struct regmap_irq_chip_data *irq_chip_data_tmu;
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mfd: intel_soc_pmic_bxtwc: Use chained IRQs for second level IRQ chips
Whishkey cove PMIC has support to mask/unmask interrupts at two levels.
At first level we can mask/unmask interrupt domains like TMU, GPIO, ADC,
CHGR, BCU THERMAL and PWRBTN and at second level, it provides facility
to mask/unmask individual interrupts belong each of this domain. For
example, in case of TMU, at first level we have TMU interrupt domain,
and at second level we have two interrupts, wake alarm, system alarm that
belong to the TMU interrupt domain.
Currently, in this driver all first level IRQs are registered as part of
IRQ chip(bxtwc_regmap_irq_chip). By default, after you register the IRQ
chip from your driver, all IRQs in that chip will masked and can only be
enabled if that IRQ is requested using request_irq() call. This is the
default Linux IRQ behavior model. And whenever a dependent device that
belongs to PMIC requests only the second level IRQ and not explicitly
unmask the first level IRQ, then in essence the second level IRQ will
still be disabled. For example, if TMU device driver request wake_alarm
IRQ and not explicitly unmask TMU level 1 IRQ then according to the default
Linux IRQ model, wake_alarm IRQ will still be disabled. So the proper
solution to fix this issue is to use the chained IRQ chip concept. We
should chain all the second level chip IRQs to the corresponding first
level IRQ. To do this, we need to create separate IRQ chips for every
group of second level IRQs.
In case of TMU, when adding second level IRQ chip, instead of using PMIC
IRQ we should use the corresponding first level IRQ. So the following
code will change from
ret = regmap_add_irq_chip(pmic->regmap, pmic->irq, ...)
to,
virq = regmap_irq_get_virq(&pmic->irq_chip_data, BXTWC_TMU_LVL1_IRQ);
ret = regmap_add_irq_chip(pmic->regmap, virq, ...)
In case of Whiskey Cove Type-C driver, Since USBC IRQ is moved under
charger level2 IRQ chip. We should use charger IRQ chip(irq_chip_data_chgr)
to get the USBC virtual IRQ number.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Revieved-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2017-06-05 19:08:05 +00:00
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struct regmap_irq_chip_data *irq_chip_data_bcu;
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struct regmap_irq_chip_data *irq_chip_data_adc;
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struct regmap_irq_chip_data *irq_chip_data_chgr;
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struct regmap_irq_chip_data *irq_chip_data_crit;
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2015-09-14 16:39:18 +00:00
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struct device *dev;
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2020-04-16 08:15:42 +00:00
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struct intel_scu_ipc_dev *scu;
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2014-06-03 05:26:02 +00:00
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};
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2019-01-07 11:15:53 +00:00
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int intel_soc_pmic_exec_mipi_pmic_seq_element(u16 i2c_address, u32 reg_address,
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u32 value, u32 mask);
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2014-06-03 05:26:02 +00:00
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#endif /* __INTEL_SOC_PMIC_H__ */
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