2018-01-09 18:29:54 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2013-04-11 00:04:48 +00:00
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/*
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* Internal header file for Samsung S3C2410 serial ports (UART0-2)
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*
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* Copyright (C) 2002 Shane Nay (shane@minirl.com)
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*
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* Additional defines, Copyright 2003 Simtec Electronics (linux@simtec.co.uk)
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*
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* Adapted from:
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*
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* Internal header file for MX1ADS serial ports (UART1 & 2)
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*
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* Copyright (C) 2002 Shane Nay (shane@minirl.com)
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2018-01-09 18:29:54 +00:00
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*/
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2013-04-11 00:04:48 +00:00
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#ifndef __ASM_ARM_REGS_SERIAL_H
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#define __ASM_ARM_REGS_SERIAL_H
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#define S3C2410_URXH (0x24)
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#define S3C2410_UTXH (0x20)
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#define S3C2410_ULCON (0x00)
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#define S3C2410_UCON (0x04)
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#define S3C2410_UFCON (0x08)
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#define S3C2410_UMCON (0x0C)
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#define S3C2410_UBRDIV (0x28)
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#define S3C2410_UTRSTAT (0x10)
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#define S3C2410_UERSTAT (0x14)
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#define S3C2410_UFSTAT (0x18)
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#define S3C2410_UMSTAT (0x1C)
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tty: serial: samsung: Init USI to keep clocks running
UART block is a part of USI (Universal Serial Interface) IP-core in
Samsung SoCs since Exynos9810 (e.g. in Exynos850). USI allows one to
enable one of three types of serial interface: UART, SPI or I2C. That's
possible because USI shares almost all internal circuits within each
protocol. USI also provides some additional registers so it's possible
to configure it.
One USI register called USI_OPTION has reset value of 0x0. Because of
this the clock gating behavior is controlled by hardware (HWACG =
Hardware Auto Clock Gating), which simply means the serial won't work
after reset as is. In order to make it work, USI_OPTION[2:1] bits must
be set to 0b01, so that HWACG is controlled manually (by software).
Bits meaning:
- CLKREQ_ON = 1: clock is continuously provided to IP
- CLKSTOP_ON = 0: drive IP_CLKREQ to High (needs to be set along with
CLKREQ_ON = 1)
USI is not present on older chips, like s3c2410, s3c2412, s3c2440,
s3c6400, s5pv210, exynos5433, exynos4210. So the new boolean field
'.has_usi' was added to struct s3c24xx_uart_info. USI registers will be
only actually accessed when '.has_usi' field is set to "1".
This feature is needed for further serial enablement on Exynos850, but
some other new Exynos chips (like Exynos9810) may benefit from this
feature as well.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20210811114827.27322-5-semen.protsenko@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-08-11 11:48:24 +00:00
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#define USI_CON (0xC4)
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#define USI_OPTION (0xC8)
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#define USI_CON_RESET (1<<0)
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#define USI_CON_RESET_MASK (1<<0)
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#define USI_OPTION_HWACG_CLKREQ_ON (1<<1)
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#define USI_OPTION_HWACG_CLKSTOP_ON (1<<2)
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#define USI_OPTION_HWACG_MASK (3<<1)
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2013-04-11 00:04:48 +00:00
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#define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3))
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#define S3C2410_LCON_CS5 (0x0)
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#define S3C2410_LCON_CS6 (0x1)
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#define S3C2410_LCON_CS7 (0x2)
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#define S3C2410_LCON_CS8 (0x3)
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#define S3C2410_LCON_CSMASK (0x3)
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#define S3C2410_LCON_PNONE (0x0)
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#define S3C2410_LCON_PEVEN (0x5 << 3)
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#define S3C2410_LCON_PODD (0x4 << 3)
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#define S3C2410_LCON_PMASK (0x7 << 3)
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#define S3C2410_LCON_STOPB (1<<2)
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#define S3C2410_LCON_IRM (1<<6)
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#define S3C2440_UCON_CLKMASK (3<<10)
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#define S3C2440_UCON_CLKSHIFT (10)
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#define S3C2440_UCON_PCLK (0<<10)
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#define S3C2440_UCON_UCLK (1<<10)
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#define S3C2440_UCON_PCLK2 (2<<10)
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#define S3C2440_UCON_FCLK (3<<10)
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#define S3C2443_UCON_EPLL (3<<10)
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#define S3C6400_UCON_CLKMASK (3<<10)
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#define S3C6400_UCON_CLKSHIFT (10)
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#define S3C6400_UCON_PCLK (0<<10)
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#define S3C6400_UCON_PCLK2 (2<<10)
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#define S3C6400_UCON_UCLK0 (1<<10)
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#define S3C6400_UCON_UCLK1 (3<<10)
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#define S3C2440_UCON2_FCLK_EN (1<<15)
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#define S3C2440_UCON0_DIVMASK (15 << 12)
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#define S3C2440_UCON1_DIVMASK (15 << 12)
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#define S3C2440_UCON2_DIVMASK (7 << 12)
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#define S3C2440_UCON_DIVSHIFT (12)
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#define S3C2412_UCON_CLKMASK (3<<10)
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#define S3C2412_UCON_CLKSHIFT (10)
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#define S3C2412_UCON_UCLK (1<<10)
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#define S3C2412_UCON_USYSCLK (3<<10)
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#define S3C2412_UCON_PCLK (0<<10)
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#define S3C2412_UCON_PCLK2 (2<<10)
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#define S3C2410_UCON_CLKMASK (1 << 10)
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#define S3C2410_UCON_CLKSHIFT (10)
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#define S3C2410_UCON_UCLK (1<<10)
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#define S3C2410_UCON_SBREAK (1<<4)
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#define S3C2410_UCON_TXILEVEL (1<<9)
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#define S3C2410_UCON_RXILEVEL (1<<8)
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#define S3C2410_UCON_TXIRQMODE (1<<2)
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#define S3C2410_UCON_RXIRQMODE (1<<0)
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#define S3C2410_UCON_RXFIFO_TOI (1<<7)
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#define S3C2443_UCON_RXERR_IRQEN (1<<6)
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#define S3C2443_UCON_LOOPBACK (1<<5)
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#define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
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S3C2410_UCON_RXILEVEL | \
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S3C2410_UCON_TXIRQMODE | \
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S3C2410_UCON_RXIRQMODE | \
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S3C2410_UCON_RXFIFO_TOI)
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2014-12-10 11:49:24 +00:00
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#define S3C64XX_UCON_TXBURST_1 (0<<20)
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#define S3C64XX_UCON_TXBURST_4 (1<<20)
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#define S3C64XX_UCON_TXBURST_8 (2<<20)
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#define S3C64XX_UCON_TXBURST_16 (3<<20)
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#define S3C64XX_UCON_TXBURST_MASK (0xf<<20)
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#define S3C64XX_UCON_RXBURST_1 (0<<16)
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#define S3C64XX_UCON_RXBURST_4 (1<<16)
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#define S3C64XX_UCON_RXBURST_8 (2<<16)
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#define S3C64XX_UCON_RXBURST_16 (3<<16)
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#define S3C64XX_UCON_RXBURST_MASK (0xf<<16)
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#define S3C64XX_UCON_TIMEOUT_SHIFT (12)
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#define S3C64XX_UCON_TIMEOUT_MASK (0xf<<12)
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#define S3C64XX_UCON_EMPTYINT_EN (1<<11)
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#define S3C64XX_UCON_DMASUS_EN (1<<10)
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#define S3C64XX_UCON_TXINT_LEVEL (1<<9)
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#define S3C64XX_UCON_RXINT_LEVEL (1<<8)
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#define S3C64XX_UCON_TIMEOUT_EN (1<<7)
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#define S3C64XX_UCON_ERRINT_EN (1<<6)
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#define S3C64XX_UCON_TXMODE_DMA (2<<2)
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#define S3C64XX_UCON_TXMODE_CPU (1<<2)
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#define S3C64XX_UCON_TXMODE_MASK (3<<2)
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#define S3C64XX_UCON_RXMODE_DMA (2<<0)
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#define S3C64XX_UCON_RXMODE_CPU (1<<0)
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#define S3C64XX_UCON_RXMODE_MASK (3<<0)
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2013-04-11 00:04:48 +00:00
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#define S3C2410_UFCON_FIFOMODE (1<<0)
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#define S3C2410_UFCON_TXTRIG0 (0<<6)
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#define S3C2410_UFCON_RXTRIG8 (1<<4)
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#define S3C2410_UFCON_RXTRIG12 (2<<4)
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/* S3C2440 FIFO trigger levels */
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#define S3C2440_UFCON_RXTRIG1 (0<<4)
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#define S3C2440_UFCON_RXTRIG8 (1<<4)
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#define S3C2440_UFCON_RXTRIG16 (2<<4)
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#define S3C2440_UFCON_RXTRIG32 (3<<4)
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#define S3C2440_UFCON_TXTRIG0 (0<<6)
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#define S3C2440_UFCON_TXTRIG16 (1<<6)
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#define S3C2440_UFCON_TXTRIG32 (2<<6)
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#define S3C2440_UFCON_TXTRIG48 (3<<6)
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#define S3C2410_UFCON_RESETBOTH (3<<1)
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#define S3C2410_UFCON_RESETTX (1<<2)
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#define S3C2410_UFCON_RESETRX (1<<1)
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#define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
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S3C2410_UFCON_TXTRIG0 | \
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S3C2410_UFCON_RXTRIG8 )
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#define S3C2410_UMCOM_AFC (1<<4)
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#define S3C2410_UMCOM_RTS_LOW (1<<0)
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#define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */
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#define S3C2412_UMCON_AFC_56 (1<<5)
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#define S3C2412_UMCON_AFC_48 (2<<5)
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#define S3C2412_UMCON_AFC_40 (3<<5)
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#define S3C2412_UMCON_AFC_32 (4<<5)
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#define S3C2412_UMCON_AFC_24 (5<<5)
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#define S3C2412_UMCON_AFC_16 (6<<5)
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#define S3C2412_UMCON_AFC_8 (7<<5)
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#define S3C2410_UFSTAT_TXFULL (1<<9)
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#define S3C2410_UFSTAT_RXFULL (1<<8)
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#define S3C2410_UFSTAT_TXMASK (15<<4)
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#define S3C2410_UFSTAT_TXSHIFT (4)
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#define S3C2410_UFSTAT_RXMASK (15<<0)
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#define S3C2410_UFSTAT_RXSHIFT (0)
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/* UFSTAT S3C2443 same as S3C2440 */
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#define S3C2440_UFSTAT_TXFULL (1<<14)
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#define S3C2440_UFSTAT_RXFULL (1<<6)
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#define S3C2440_UFSTAT_TXSHIFT (8)
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#define S3C2440_UFSTAT_RXSHIFT (0)
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#define S3C2440_UFSTAT_TXMASK (63<<8)
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#define S3C2440_UFSTAT_RXMASK (63)
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2014-12-10 11:49:24 +00:00
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#define S3C2410_UTRSTAT_TIMEOUT (1<<3)
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2013-04-11 00:04:48 +00:00
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#define S3C2410_UTRSTAT_TXE (1<<2)
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#define S3C2410_UTRSTAT_TXFE (1<<1)
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#define S3C2410_UTRSTAT_RXDR (1<<0)
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#define S3C2410_UERSTAT_OVERRUN (1<<0)
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#define S3C2410_UERSTAT_FRAME (1<<2)
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#define S3C2410_UERSTAT_BREAK (1<<3)
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#define S3C2443_UERSTAT_PARITY (1<<1)
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#define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \
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S3C2410_UERSTAT_FRAME | \
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S3C2410_UERSTAT_BREAK)
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#define S3C2410_UMSTAT_CTS (1<<0)
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#define S3C2410_UMSTAT_DeltaCTS (1<<2)
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#define S3C2443_DIVSLOT (0x2C)
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/* S3C64XX interrupt registers. */
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#define S3C64XX_UINTP 0x30
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#define S3C64XX_UINTSP 0x34
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#define S3C64XX_UINTM 0x38
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#define S3C64XX_UINTM_RXD (0)
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2014-12-10 11:49:24 +00:00
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#define S3C64XX_UINTM_ERROR (1)
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2013-04-11 00:04:48 +00:00
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#define S3C64XX_UINTM_TXD (2)
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#define S3C64XX_UINTM_RXD_MSK (1 << S3C64XX_UINTM_RXD)
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2014-12-10 11:49:24 +00:00
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#define S3C64XX_UINTM_ERR_MSK (1 << S3C64XX_UINTM_ERROR)
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2013-04-11 00:04:48 +00:00
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#define S3C64XX_UINTM_TXD_MSK (1 << S3C64XX_UINTM_TXD)
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/* Following are specific to S5PV210 */
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#define S5PV210_UCON_CLKMASK (1<<10)
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#define S5PV210_UCON_CLKSHIFT (10)
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#define S5PV210_UCON_PCLK (0<<10)
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#define S5PV210_UCON_UCLK (1<<10)
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#define S5PV210_UFCON_TXTRIG0 (0<<8)
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#define S5PV210_UFCON_TXTRIG4 (1<<8)
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#define S5PV210_UFCON_TXTRIG8 (2<<8)
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#define S5PV210_UFCON_TXTRIG16 (3<<8)
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#define S5PV210_UFCON_TXTRIG32 (4<<8)
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#define S5PV210_UFCON_TXTRIG64 (5<<8)
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#define S5PV210_UFCON_TXTRIG128 (6<<8)
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#define S5PV210_UFCON_TXTRIG256 (7<<8)
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#define S5PV210_UFCON_RXTRIG1 (0<<4)
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#define S5PV210_UFCON_RXTRIG4 (1<<4)
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#define S5PV210_UFCON_RXTRIG8 (2<<4)
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#define S5PV210_UFCON_RXTRIG16 (3<<4)
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#define S5PV210_UFCON_RXTRIG32 (4<<4)
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#define S5PV210_UFCON_RXTRIG64 (5<<4)
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#define S5PV210_UFCON_RXTRIG128 (6<<4)
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#define S5PV210_UFCON_RXTRIG256 (7<<4)
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#define S5PV210_UFSTAT_TXFULL (1<<24)
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#define S5PV210_UFSTAT_RXFULL (1<<8)
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#define S5PV210_UFSTAT_TXMASK (255<<16)
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#define S5PV210_UFSTAT_TXSHIFT (16)
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#define S5PV210_UFSTAT_RXMASK (255<<0)
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#define S5PV210_UFSTAT_RXSHIFT (0)
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#define S3C2410_UCON_CLKSEL0 (1 << 0)
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#define S3C2410_UCON_CLKSEL1 (1 << 1)
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#define S3C2410_UCON_CLKSEL2 (1 << 2)
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#define S3C2410_UCON_CLKSEL3 (1 << 3)
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/* Default values for s5pv210 UCON and UFCON uart registers */
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#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
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S3C2410_UCON_RXILEVEL | \
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S3C2410_UCON_TXIRQMODE | \
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S3C2410_UCON_RXIRQMODE | \
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S3C2410_UCON_RXFIFO_TOI | \
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S3C2443_UCON_RXERR_IRQEN)
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#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
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S5PV210_UFCON_TXTRIG4 | \
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S5PV210_UFCON_RXTRIG4)
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2021-03-04 21:38:59 +00:00
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#define APPLE_S5L_UCON_RXTO_ENA 9
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#define APPLE_S5L_UCON_RXTHRESH_ENA 12
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#define APPLE_S5L_UCON_TXTHRESH_ENA 13
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#define APPLE_S5L_UCON_RXTO_ENA_MSK (1 << APPLE_S5L_UCON_RXTO_ENA)
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#define APPLE_S5L_UCON_RXTHRESH_ENA_MSK (1 << APPLE_S5L_UCON_RXTHRESH_ENA)
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#define APPLE_S5L_UCON_TXTHRESH_ENA_MSK (1 << APPLE_S5L_UCON_TXTHRESH_ENA)
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#define APPLE_S5L_UCON_DEFAULT (S3C2410_UCON_TXIRQMODE | \
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S3C2410_UCON_RXIRQMODE | \
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S3C2410_UCON_RXFIFO_TOI)
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#define APPLE_S5L_UTRSTAT_RXTHRESH (1<<4)
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#define APPLE_S5L_UTRSTAT_TXTHRESH (1<<5)
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#define APPLE_S5L_UTRSTAT_RXTO (1<<9)
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#define APPLE_S5L_UTRSTAT_ALL_FLAGS (0x3f0)
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2013-04-11 00:04:48 +00:00
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#ifndef __ASSEMBLY__
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2014-03-20 17:55:11 +00:00
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#include <linux/serial_core.h>
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2013-04-11 00:04:48 +00:00
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/* configuration structure for per-machine configurations for the
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* serial port
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*
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* the pointer is setup by the machine specific initialisation from the
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2020-09-11 14:33:42 +00:00
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* arch/arm/mach-s3c/ directory.
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2013-04-11 00:04:48 +00:00
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*/
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struct s3c2410_uartcfg {
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unsigned char hwport; /* hardware port number */
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unsigned char unused;
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unsigned short flags;
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upf_t uart_flags; /* default uart flags */
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unsigned int clk_sel;
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unsigned int has_fracval;
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unsigned long ucon; /* value of ucon for port */
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unsigned long ulcon; /* value of ulcon for port */
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unsigned long ufcon; /* value of ufcon for port */
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARM_REGS_SERIAL_H */
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