2012-08-16 11:31:02 +00:00
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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2016-05-05 07:57:56 +00:00
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* Copyright (C) 2012 John Crispin <john@phrozen.org>
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2012-08-16 11:31:02 +00:00
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* Copyright (C) 2012 Lantiq GmbH
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*/
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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2017-01-29 02:05:57 +00:00
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#include <linux/init.h>
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2012-08-16 11:31:02 +00:00
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#include <linux/of_platform.h>
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#include <linux/of_irq.h>
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#include <lantiq_soc.h>
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#include "../clk.h"
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/* the magic ID byte of the core */
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#define GPTU_MAGIC 0x59
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/* clock control register */
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#define GPTU_CLC 0x00
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/* id register */
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#define GPTU_ID 0x08
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/* interrupt node enable */
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#define GPTU_IRNEN 0xf4
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/* interrupt control register */
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#define GPTU_IRCR 0xf8
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/* interrupt capture register */
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#define GPTU_IRNCR 0xfc
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/* there are 3 identical blocks of 2 timers. calculate register offsets */
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#define GPTU_SHIFT(x) (x % 2 ? 4 : 0)
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#define GPTU_BASE(x) (((x >> 1) * 0x20) + 0x10)
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/* timer control register */
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#define GPTU_CON(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x00)
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/* timer auto reload register */
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#define GPTU_RUN(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x08)
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/* timer manual reload register */
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#define GPTU_RLD(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x10)
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/* timer count register */
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#define GPTU_CNT(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x18)
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/* GPTU_CON(x) */
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#define CON_CNT BIT(2)
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#define CON_EDGE_ANY (BIT(7) | BIT(6))
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#define CON_SYNC BIT(8)
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#define CON_CLK_INT BIT(10)
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/* GPTU_RUN(x) */
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#define RUN_SEN BIT(0)
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#define RUN_RL BIT(2)
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/* set clock to runmode */
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#define CLC_RMC BIT(8)
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/* bring core out of suspend */
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#define CLC_SUSPEND BIT(4)
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/* the disable bit */
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#define CLC_DISABLE BIT(0)
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#define gptu_w32(x, y) ltq_w32((x), gptu_membase + (y))
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#define gptu_r32(x) ltq_r32(gptu_membase + (x))
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enum gptu_timer {
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TIMER1A = 0,
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TIMER1B,
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TIMER2A,
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TIMER2B,
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TIMER3A,
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TIMER3B
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};
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static void __iomem *gptu_membase;
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static struct resource irqres[6];
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static irqreturn_t timer_irq_handler(int irq, void *priv)
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{
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int timer = irq - irqres[0].start;
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gptu_w32(1 << timer, GPTU_IRNCR);
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return IRQ_HANDLED;
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}
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static void gptu_hwinit(void)
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{
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gptu_w32(0x00, GPTU_IRNEN);
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gptu_w32(0xff, GPTU_IRNCR);
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gptu_w32(CLC_RMC | CLC_SUSPEND, GPTU_CLC);
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}
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static void gptu_hwexit(void)
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{
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gptu_w32(0x00, GPTU_IRNEN);
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gptu_w32(0xff, GPTU_IRNCR);
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gptu_w32(CLC_DISABLE, GPTU_CLC);
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}
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static int gptu_enable(struct clk *clk)
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{
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int ret = request_irq(irqres[clk->bits].start, timer_irq_handler,
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IRQF_TIMER, "gtpu", NULL);
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if (ret) {
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pr_err("gptu: failed to request irq\n");
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return ret;
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}
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gptu_w32(CON_CNT | CON_EDGE_ANY | CON_SYNC | CON_CLK_INT,
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GPTU_CON(clk->bits));
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gptu_w32(1, GPTU_RLD(clk->bits));
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gptu_w32(gptu_r32(GPTU_IRNEN) | BIT(clk->bits), GPTU_IRNEN);
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gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits));
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return 0;
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}
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static void gptu_disable(struct clk *clk)
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{
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gptu_w32(0, GPTU_RUN(clk->bits));
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gptu_w32(0, GPTU_CON(clk->bits));
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gptu_w32(0, GPTU_RLD(clk->bits));
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gptu_w32(gptu_r32(GPTU_IRNEN) & ~BIT(clk->bits), GPTU_IRNEN);
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free_irq(irqres[clk->bits].start, NULL);
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}
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static inline void clkdev_add_gptu(struct device *dev, const char *con,
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unsigned int timer)
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{
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struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
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clk->cl.dev_id = dev_name(dev);
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clk->cl.con_id = con;
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clk->cl.clk = clk;
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clk->enable = gptu_enable;
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clk->disable = gptu_disable;
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clk->bits = timer;
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clkdev_add(&clk->cl);
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}
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2012-12-21 22:04:39 +00:00
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static int gptu_probe(struct platform_device *pdev)
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2012-08-16 11:31:02 +00:00
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{
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struct clk *clk;
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struct resource *res;
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if (of_irq_to_resource_table(pdev->dev.of_node, irqres, 6) != 6) {
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dev_err(&pdev->dev, "Failed to get IRQ list\n");
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return -EINVAL;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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/* remap gptu register range */
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2013-01-21 10:08:56 +00:00
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gptu_membase = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(gptu_membase))
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return PTR_ERR(gptu_membase);
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2012-08-16 11:31:02 +00:00
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/* enable our clock */
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clk = clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk)) {
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dev_err(&pdev->dev, "Failed to get clock\n");
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return -ENOENT;
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}
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clk_enable(clk);
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/* power up the core */
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gptu_hwinit();
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/* the gptu has a ID register */
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if (((gptu_r32(GPTU_ID) >> 8) & 0xff) != GPTU_MAGIC) {
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dev_err(&pdev->dev, "Failed to find magic\n");
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gptu_hwexit();
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2013-05-17 05:21:31 +00:00
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clk_disable(clk);
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clk_put(clk);
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2012-08-16 11:31:02 +00:00
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return -ENAVAIL;
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}
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/* register the clocks */
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clkdev_add_gptu(&pdev->dev, "timer1a", TIMER1A);
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clkdev_add_gptu(&pdev->dev, "timer1b", TIMER1B);
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clkdev_add_gptu(&pdev->dev, "timer2a", TIMER2A);
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clkdev_add_gptu(&pdev->dev, "timer2b", TIMER2B);
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clkdev_add_gptu(&pdev->dev, "timer3a", TIMER3A);
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clkdev_add_gptu(&pdev->dev, "timer3b", TIMER3B);
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dev_info(&pdev->dev, "gptu: 6 timers loaded\n");
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return 0;
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}
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static const struct of_device_id gptu_match[] = {
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{ .compatible = "lantiq,gptu-xway" },
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{},
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};
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static struct platform_driver dma_driver = {
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.probe = gptu_probe,
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.driver = {
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.name = "gptu-xway",
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.of_match_table = gptu_match,
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},
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};
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int __init gptu_init(void)
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{
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int ret = platform_driver_register(&dma_driver);
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if (ret)
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pr_info("gptu: Error registering platform driver\n");
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return ret;
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}
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arch_initcall(gptu_init);
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