2005-09-26 06:04:21 +00:00
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/*
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* PowerPC version
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Derived from "arch/i386/mm/fault.c"
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* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
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*
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* Modified by Cort Dougan and Paul Mackerras.
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*
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* Modified for PPC64 by Dave Engebretsen (engebret@ibm.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <linux/mman.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/highmem.h>
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#include <linux/module.h>
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#include <linux/kprobes.h>
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2007-05-08 07:27:03 +00:00
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#include <linux/kdebug.h>
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perf: Do the big rename: Performance Counters -> Performance Events
Bye-bye Performance Counters, welcome Performance Events!
In the past few months the perfcounters subsystem has grown out its
initial role of counting hardware events, and has become (and is
becoming) a much broader generic event enumeration, reporting, logging,
monitoring, analysis facility.
Naming its core object 'perf_counter' and naming the subsystem
'perfcounters' has become more and more of a misnomer. With pending
code like hw-breakpoints support the 'counter' name is less and
less appropriate.
All in one, we've decided to rename the subsystem to 'performance
events' and to propagate this rename through all fields, variables
and API names. (in an ABI compatible fashion)
The word 'event' is also a bit shorter than 'counter' - which makes
it slightly more convenient to write/handle as well.
Thanks goes to Stephane Eranian who first observed this misnomer and
suggested a rename.
User-space tooling and ABI compatibility is not affected - this patch
should be function-invariant. (Also, defconfigs were not touched to
keep the size down.)
This patch has been generated via the following script:
FILES=$(find * -type f | grep -vE 'oprofile|[^K]config')
sed -i \
-e 's/PERF_EVENT_/PERF_RECORD_/g' \
-e 's/PERF_COUNTER/PERF_EVENT/g' \
-e 's/perf_counter/perf_event/g' \
-e 's/nb_counters/nb_events/g' \
-e 's/swcounter/swevent/g' \
-e 's/tpcounter_event/tp_event/g' \
$FILES
for N in $(find . -name perf_counter.[ch]); do
M=$(echo $N | sed 's/perf_counter/perf_event/g')
mv $N $M
done
FILES=$(find . -name perf_event.*)
sed -i \
-e 's/COUNTER_MASK/REG_MASK/g' \
-e 's/COUNTER/EVENT/g' \
-e 's/\<event\>/event_id/g' \
-e 's/counter/event/g' \
-e 's/Counter/Event/g' \
$FILES
... to keep it as correct as possible. This script can also be
used by anyone who has pending perfcounters patches - it converts
a Linux kernel tree over to the new naming. We tried to time this
change to the point in time where the amount of pending patches
is the smallest: the end of the merge window.
Namespace clashes were fixed up in a preparatory patch - and some
stylistic fallout will be fixed up in a subsequent patch.
( NOTE: 'counters' are still the proper terminology when we deal
with hardware registers - and these sed scripts are a bit
over-eager in renaming them. I've undone some of that, but
in case there's something left where 'counter' would be
better than 'event' we can undo that on an individual basis
instead of touching an otherwise nicely automated patch. )
Suggested-by: Stephane Eranian <eranian@google.com>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: Paul Mackerras <paulus@samba.org>
Reviewed-by: Arjan van de Ven <arjan@linux.intel.com>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: David Howells <dhowells@redhat.com>
Cc: Kyle McMartin <kyle@mcmartin.ca>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: <linux-arch@vger.kernel.org>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-09-21 10:02:48 +00:00
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#include <linux/perf_event.h>
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2010-08-24 13:15:28 +00:00
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#include <linux/magic.h>
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2011-06-04 05:36:54 +00:00
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#include <linux/ratelimit.h>
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2005-09-26 06:04:21 +00:00
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2008-10-22 05:53:45 +00:00
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#include <asm/firmware.h>
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2005-09-26 06:04:21 +00:00
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/mmu.h>
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#include <asm/mmu_context.h>
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#include <asm/system.h>
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#include <asm/uaccess.h>
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#include <asm/tlbflush.h>
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#include <asm/siginfo.h>
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2009-11-20 00:21:02 +00:00
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#include <mm/mmu_decl.h>
|
2006-06-26 07:25:27 +00:00
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2011-09-29 10:55:14 +00:00
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#include "icswx.h"
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2007-04-30 10:56:46 +00:00
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#ifdef CONFIG_KPROBES
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static inline int notify_page_fault(struct pt_regs *regs)
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2006-06-26 07:25:27 +00:00
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{
|
2007-04-30 10:56:46 +00:00
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int ret = 0;
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/* kprobe_running() needs smp_processor_id() */
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if (!user_mode(regs)) {
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preempt_disable();
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if (kprobe_running() && kprobe_fault_handler(regs, 11))
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ret = 1;
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preempt_enable();
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}
|
2006-06-26 07:25:27 +00:00
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2007-04-30 10:56:46 +00:00
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return ret;
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2006-06-26 07:25:27 +00:00
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}
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#else
|
2007-04-30 10:56:46 +00:00
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static inline int notify_page_fault(struct pt_regs *regs)
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2006-06-26 07:25:27 +00:00
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{
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2007-04-30 10:56:46 +00:00
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return 0;
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2006-06-26 07:25:27 +00:00
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}
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#endif
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2005-09-26 06:04:21 +00:00
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/*
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* Check whether the instruction at regs->nip is a store using
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* an update addressing form which will update r1.
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*/
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static int store_updates_sp(struct pt_regs *regs)
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{
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unsigned int inst;
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if (get_user(inst, (unsigned int __user *)regs->nip))
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return 0;
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/* check for 1 in the rA field */
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if (((inst >> 16) & 0x1f) != 1)
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return 0;
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/* check major opcode */
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switch (inst >> 26) {
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case 37: /* stwu */
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case 39: /* stbu */
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case 45: /* sthu */
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case 53: /* stfsu */
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case 55: /* stfdu */
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return 1;
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case 62: /* std or stdu */
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return (inst & 3) == 1;
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case 31:
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/* check minor opcode */
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switch ((inst >> 1) & 0x3ff) {
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case 181: /* stdux */
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case 183: /* stwux */
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case 247: /* stbux */
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case 439: /* sthux */
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case 695: /* stfsux */
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case 759: /* stfdux */
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return 1;
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}
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}
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return 0;
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}
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|
/*
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|
|
* For 600- and 800-family processors, the error_code parameter is DSISR
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* for a data fault, SRR1 for an instruction fault. For 400-family processors
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* the error_code parameter is ESR for a data fault, 0 for an instruction
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* fault.
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* For 64-bit processors, the error_code parameter is
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* - DSISR for a non-SLB data access fault,
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* - SRR1 & 0x08000000 for a non-SLB instruction access fault
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* - 0 any SLB fault.
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*
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* The return value is 0 if the fault was handled, or the signal
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* number if this is a kernel fault that can't be handled here.
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*/
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int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
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unsigned long error_code)
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{
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struct vm_area_struct * vma;
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struct mm_struct *mm = current->mm;
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siginfo_t info;
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int code = SEGV_MAPERR;
|
2007-07-19 08:47:05 +00:00
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int is_write = 0, ret;
|
2005-09-26 06:04:21 +00:00
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int trap = TRAP(regs);
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int is_exec = trap == 0x400;
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#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
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|
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/*
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* Fortunately the bit assignments in SRR1 for an instruction
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* fault and DSISR for a data fault are mostly the same for the
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* bits we are interested in. But there are some bits which
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* indicate errors in DSISR but can validly be set in SRR1.
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*/
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if (trap == 0x400)
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error_code &= 0x48200000;
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else
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is_write = error_code & DSISR_ISSTORE;
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#else
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is_write = error_code & ESR_DST;
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#endif /* CONFIG_4xx || CONFIG_BOOKE */
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|
2011-09-29 10:55:14 +00:00
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|
#ifdef CONFIG_PPC_ICSWX
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|
|
/*
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|
|
* we need to do this early because this "data storage
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|
* interrupt" does not update the DAR/DEAR so we don't want to
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|
* look at it
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*/
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|
if (error_code & ICSWX_DSI_UCT) {
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|
|
int ret;
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|
|
|
|
|
|
ret = acop_handle_fault(regs, address, error_code);
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|
|
if (ret)
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|
return ret;
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|
|
}
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|
|
#endif
|
|
|
|
|
2007-04-30 10:56:46 +00:00
|
|
|
if (notify_page_fault(regs))
|
2005-09-26 06:04:21 +00:00
|
|
|
return 0;
|
|
|
|
|
2008-01-18 04:50:30 +00:00
|
|
|
if (unlikely(debugger_fault_handler(regs)))
|
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|
|
return 0;
|
2005-09-26 06:04:21 +00:00
|
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|
|
|
|
|
/* On a kernel SLB miss we can only check for a valid exception entry */
|
|
|
|
if (!user_mode(regs) && (address >= TASK_SIZE))
|
|
|
|
return SIGSEGV;
|
|
|
|
|
2010-03-29 23:59:25 +00:00
|
|
|
#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE) || \
|
|
|
|
defined(CONFIG_PPC_BOOK3S_64))
|
2005-09-26 06:04:21 +00:00
|
|
|
if (error_code & DSISR_DABRMATCH) {
|
|
|
|
/* DABR match */
|
2006-01-09 04:47:04 +00:00
|
|
|
do_dabr(regs, address, error_code);
|
2005-09-26 06:04:21 +00:00
|
|
|
return 0;
|
|
|
|
}
|
2010-03-29 23:59:25 +00:00
|
|
|
#endif
|
2005-09-26 06:04:21 +00:00
|
|
|
|
|
|
|
if (in_atomic() || mm == NULL) {
|
|
|
|
if (!user_mode(regs))
|
|
|
|
return SIGSEGV;
|
|
|
|
/* in_atomic() in user mode is really bad,
|
|
|
|
as is current->mm == NULL. */
|
2007-11-20 01:47:55 +00:00
|
|
|
printk(KERN_EMERG "Page fault in user mode with "
|
2005-09-26 06:04:21 +00:00
|
|
|
"in_atomic() = %d mm = %p\n", in_atomic(), mm);
|
|
|
|
printk(KERN_EMERG "NIP = %lx MSR = %lx\n",
|
|
|
|
regs->nip, regs->msr);
|
|
|
|
die("Weird page fault", regs, SIGSEGV);
|
|
|
|
}
|
|
|
|
|
2011-06-27 12:41:57 +00:00
|
|
|
perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address);
|
2009-03-13 11:21:33 +00:00
|
|
|
|
2005-09-26 06:04:21 +00:00
|
|
|
/* When running in the kernel we expect faults to occur only to
|
|
|
|
* addresses in user space. All other faults represent errors in the
|
2006-04-01 00:33:12 +00:00
|
|
|
* kernel and should generate an OOPS. Unfortunately, in the case of an
|
|
|
|
* erroneous fault occurring in a code path which already holds mmap_sem
|
2005-09-26 06:04:21 +00:00
|
|
|
* we will deadlock attempting to validate the fault against the
|
|
|
|
* address space. Luckily the kernel only validly references user
|
|
|
|
* space from well defined areas of code, which are listed in the
|
|
|
|
* exceptions table.
|
|
|
|
*
|
|
|
|
* As the vast majority of faults will be valid we will only perform
|
2006-04-01 00:33:12 +00:00
|
|
|
* the source reference check when there is a possibility of a deadlock.
|
2005-09-26 06:04:21 +00:00
|
|
|
* Attempt to lock the address space, if we cannot we then validate the
|
|
|
|
* source. If this is invalid we can skip the address space check,
|
|
|
|
* thus avoiding the deadlock.
|
|
|
|
*/
|
|
|
|
if (!down_read_trylock(&mm->mmap_sem)) {
|
|
|
|
if (!user_mode(regs) && !search_exception_tables(regs->nip))
|
|
|
|
goto bad_area_nosemaphore;
|
|
|
|
|
|
|
|
down_read(&mm->mmap_sem);
|
|
|
|
}
|
|
|
|
|
|
|
|
vma = find_vma(mm, address);
|
|
|
|
if (!vma)
|
|
|
|
goto bad_area;
|
|
|
|
if (vma->vm_start <= address)
|
|
|
|
goto good_area;
|
|
|
|
if (!(vma->vm_flags & VM_GROWSDOWN))
|
|
|
|
goto bad_area;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* N.B. The POWER/Open ABI allows programs to access up to
|
|
|
|
* 288 bytes below the stack pointer.
|
|
|
|
* The kernel signal delivery code writes up to about 1.5kB
|
|
|
|
* below the stack pointer (r1) before decrementing it.
|
|
|
|
* The exec code can write slightly over 640kB to the stack
|
|
|
|
* before setting the user r1. Thus we allow the stack to
|
|
|
|
* expand to 1MB without further checks.
|
|
|
|
*/
|
|
|
|
if (address + 0x100000 < vma->vm_end) {
|
|
|
|
/* get user regs even if this fault is in kernel mode */
|
|
|
|
struct pt_regs *uregs = current->thread.regs;
|
|
|
|
if (uregs == NULL)
|
|
|
|
goto bad_area;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* A user-mode access to an address a long way below
|
|
|
|
* the stack pointer is only valid if the instruction
|
|
|
|
* is one which would update the stack pointer to the
|
|
|
|
* address accessed if the instruction completed,
|
|
|
|
* i.e. either stwu rs,n(r1) or stwux rs,r1,rb
|
|
|
|
* (or the byte, halfword, float or double forms).
|
|
|
|
*
|
|
|
|
* If we don't check this then any write to the area
|
|
|
|
* between the last mapped region and the stack will
|
|
|
|
* expand the stack rather than segfaulting.
|
|
|
|
*/
|
|
|
|
if (address + 2048 < uregs->gpr[1]
|
|
|
|
&& (!user_mode(regs) || !store_updates_sp(regs)))
|
|
|
|
goto bad_area;
|
|
|
|
}
|
|
|
|
if (expand_stack(vma, address))
|
|
|
|
goto bad_area;
|
|
|
|
|
|
|
|
good_area:
|
|
|
|
code = SEGV_ACCERR;
|
|
|
|
#if defined(CONFIG_6xx)
|
|
|
|
if (error_code & 0x95700000)
|
|
|
|
/* an error such as lwarx to I/O controller space,
|
|
|
|
address matching DABR, eciwx, etc. */
|
|
|
|
goto bad_area;
|
|
|
|
#endif /* CONFIG_6xx */
|
|
|
|
#if defined(CONFIG_8xx)
|
2009-11-20 00:21:02 +00:00
|
|
|
/* 8xx sometimes need to load a invalid/non-present TLBs.
|
|
|
|
* These must be invalidated separately as linux mm don't.
|
|
|
|
*/
|
|
|
|
if (error_code & 0x40000000) /* no translation? */
|
|
|
|
_tlbil_va(address, 0, 0, 0);
|
|
|
|
|
2005-09-26 06:04:21 +00:00
|
|
|
/* The MPC8xx seems to always set 0x80000000, which is
|
|
|
|
* "undefined". Of those that can be set, this is the only
|
|
|
|
* one which seems bad.
|
|
|
|
*/
|
|
|
|
if (error_code & 0x10000000)
|
|
|
|
/* Guarded storage error. */
|
|
|
|
goto bad_area;
|
|
|
|
#endif /* CONFIG_8xx */
|
|
|
|
|
|
|
|
if (is_exec) {
|
powerpc/mm: Rework I$/D$ coherency (v3)
This patch reworks the way we do I and D cache coherency on PowerPC.
The "old" way was split in 3 different parts depending on the processor type:
- Hash with per-page exec support (64-bit and >= POWER4 only) does it
at hashing time, by preventing exec on unclean pages and cleaning pages
on exec faults.
- Everything without per-page exec support (32-bit hash, 8xx, and
64-bit < POWER4) does it for all page going to user space in update_mmu_cache().
- Embedded with per-page exec support does it from do_page_fault() on
exec faults, in a way similar to what the hash code does.
That leads to confusion, and bugs. For example, the method using update_mmu_cache()
is racy on SMP where another processor can see the new PTE and hash it in before
we have cleaned the cache, and then blow trying to execute. This is hard to hit but
I think it has bitten us in the past.
Also, it's inefficient for embedded where we always end up having to do at least
one more page fault.
This reworks the whole thing by moving the cache sync into two main call sites,
though we keep different behaviours depending on the HW capability. The call
sites are set_pte_at() which is now made out of line, and ptep_set_access_flags()
which joins the former in pgtable.c
The base idea for Embedded with per-page exec support, is that we now do the
flush at set_pte_at() time when coming from an exec fault, which allows us
to avoid the double fault problem completely (we can even improve the situation
more by implementing TLB preload in update_mmu_cache() but that's for later).
If for some reason we didn't do it there and we try to execute, we'll hit
the page fault, which will do a minor fault, which will hit ptep_set_access_flags()
to do things like update _PAGE_ACCESSED or _PAGE_DIRTY if needed, we just make
this guys also perform the I/D cache sync for exec faults now. This second path
is the catch all for things that weren't cleaned at set_pte_at() time.
For cpus without per-pag exec support, we always do the sync at set_pte_at(),
thus guaranteeing that when the PTE is visible to other processors, the cache
is clean.
For the 64-bit hash with per-page exec support case, we keep the old mechanism
for now. I'll look into changing it later, once I've reworked a bit how we
use _PAGE_EXEC.
This is also a first step for adding _PAGE_EXEC support for embedded platforms
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-02-10 16:02:37 +00:00
|
|
|
#ifdef CONFIG_PPC_STD_MMU
|
|
|
|
/* Protection fault on exec go straight to failure on
|
|
|
|
* Hash based MMUs as they either don't support per-page
|
|
|
|
* execute permission, or if they do, it's handled already
|
|
|
|
* at the hash level. This test would probably have to
|
|
|
|
* be removed if we change the way this works to make hash
|
|
|
|
* processors use the same I/D cache coherency mechanism
|
|
|
|
* as embedded.
|
|
|
|
*/
|
2005-09-26 06:04:21 +00:00
|
|
|
if (error_code & DSISR_PROTFAULT)
|
|
|
|
goto bad_area;
|
powerpc/mm: Rework I$/D$ coherency (v3)
This patch reworks the way we do I and D cache coherency on PowerPC.
The "old" way was split in 3 different parts depending on the processor type:
- Hash with per-page exec support (64-bit and >= POWER4 only) does it
at hashing time, by preventing exec on unclean pages and cleaning pages
on exec faults.
- Everything without per-page exec support (32-bit hash, 8xx, and
64-bit < POWER4) does it for all page going to user space in update_mmu_cache().
- Embedded with per-page exec support does it from do_page_fault() on
exec faults, in a way similar to what the hash code does.
That leads to confusion, and bugs. For example, the method using update_mmu_cache()
is racy on SMP where another processor can see the new PTE and hash it in before
we have cleaned the cache, and then blow trying to execute. This is hard to hit but
I think it has bitten us in the past.
Also, it's inefficient for embedded where we always end up having to do at least
one more page fault.
This reworks the whole thing by moving the cache sync into two main call sites,
though we keep different behaviours depending on the HW capability. The call
sites are set_pte_at() which is now made out of line, and ptep_set_access_flags()
which joins the former in pgtable.c
The base idea for Embedded with per-page exec support, is that we now do the
flush at set_pte_at() time when coming from an exec fault, which allows us
to avoid the double fault problem completely (we can even improve the situation
more by implementing TLB preload in update_mmu_cache() but that's for later).
If for some reason we didn't do it there and we try to execute, we'll hit
the page fault, which will do a minor fault, which will hit ptep_set_access_flags()
to do things like update _PAGE_ACCESSED or _PAGE_DIRTY if needed, we just make
this guys also perform the I/D cache sync for exec faults now. This second path
is the catch all for things that weren't cleaned at set_pte_at() time.
For cpus without per-pag exec support, we always do the sync at set_pte_at(),
thus guaranteeing that when the PTE is visible to other processors, the cache
is clean.
For the 64-bit hash with per-page exec support case, we keep the old mechanism
for now. I'll look into changing it later, once I've reworked a bit how we
use _PAGE_EXEC.
This is also a first step for adding _PAGE_EXEC support for embedded platforms
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-02-10 16:02:37 +00:00
|
|
|
#endif /* CONFIG_PPC_STD_MMU */
|
|
|
|
|
2007-07-19 00:00:20 +00:00
|
|
|
/*
|
|
|
|
* Allow execution from readable areas if the MMU does not
|
|
|
|
* provide separate controls over reading and executing.
|
powerpc/mm: Rework I$/D$ coherency (v3)
This patch reworks the way we do I and D cache coherency on PowerPC.
The "old" way was split in 3 different parts depending on the processor type:
- Hash with per-page exec support (64-bit and >= POWER4 only) does it
at hashing time, by preventing exec on unclean pages and cleaning pages
on exec faults.
- Everything without per-page exec support (32-bit hash, 8xx, and
64-bit < POWER4) does it for all page going to user space in update_mmu_cache().
- Embedded with per-page exec support does it from do_page_fault() on
exec faults, in a way similar to what the hash code does.
That leads to confusion, and bugs. For example, the method using update_mmu_cache()
is racy on SMP where another processor can see the new PTE and hash it in before
we have cleaned the cache, and then blow trying to execute. This is hard to hit but
I think it has bitten us in the past.
Also, it's inefficient for embedded where we always end up having to do at least
one more page fault.
This reworks the whole thing by moving the cache sync into two main call sites,
though we keep different behaviours depending on the HW capability. The call
sites are set_pte_at() which is now made out of line, and ptep_set_access_flags()
which joins the former in pgtable.c
The base idea for Embedded with per-page exec support, is that we now do the
flush at set_pte_at() time when coming from an exec fault, which allows us
to avoid the double fault problem completely (we can even improve the situation
more by implementing TLB preload in update_mmu_cache() but that's for later).
If for some reason we didn't do it there and we try to execute, we'll hit
the page fault, which will do a minor fault, which will hit ptep_set_access_flags()
to do things like update _PAGE_ACCESSED or _PAGE_DIRTY if needed, we just make
this guys also perform the I/D cache sync for exec faults now. This second path
is the catch all for things that weren't cleaned at set_pte_at() time.
For cpus without per-pag exec support, we always do the sync at set_pte_at(),
thus guaranteeing that when the PTE is visible to other processors, the cache
is clean.
For the 64-bit hash with per-page exec support case, we keep the old mechanism
for now. I'll look into changing it later, once I've reworked a bit how we
use _PAGE_EXEC.
This is also a first step for adding _PAGE_EXEC support for embedded platforms
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-02-10 16:02:37 +00:00
|
|
|
*
|
|
|
|
* Note: That code used to not be enabled for 4xx/BookE.
|
|
|
|
* It is now as I/D cache coherency for these is done at
|
|
|
|
* set_pte_at() time and I see no reason why the test
|
|
|
|
* below wouldn't be valid on those processors. This -may-
|
|
|
|
* break programs compiled with a really old ABI though.
|
2007-07-19 00:00:20 +00:00
|
|
|
*/
|
|
|
|
if (!(vma->vm_flags & VM_EXEC) &&
|
|
|
|
(cpu_has_feature(CPU_FTR_NOEXECUTE) ||
|
|
|
|
!(vma->vm_flags & (VM_READ | VM_WRITE))))
|
2005-09-26 06:04:21 +00:00
|
|
|
goto bad_area;
|
|
|
|
/* a write */
|
|
|
|
} else if (is_write) {
|
|
|
|
if (!(vma->vm_flags & VM_WRITE))
|
|
|
|
goto bad_area;
|
|
|
|
/* a read */
|
|
|
|
} else {
|
|
|
|
/* protection fault */
|
|
|
|
if (error_code & 0x08000000)
|
|
|
|
goto bad_area;
|
[PATCH] make PROT_WRITE imply PROT_READ
Make PROT_WRITE imply PROT_READ for a number of architectures which don't
support write only in hardware.
While looking at this, I noticed that some architectures which do not
support write only mappings already take the exact same approach. For
example, in arch/alpha/mm/fault.c:
"
if (cause < 0) {
if (!(vma->vm_flags & VM_EXEC))
goto bad_area;
} else if (!cause) {
/* Allow reads even for write-only mappings */
if (!(vma->vm_flags & (VM_READ | VM_WRITE)))
goto bad_area;
} else {
if (!(vma->vm_flags & VM_WRITE))
goto bad_area;
}
"
Thus, this patch brings other architectures which do not support write only
mappings in-line and consistent with the rest. I've verified the patch on
ia64, x86_64 and x86.
Additional discussion:
Several architectures, including x86, can not support write-only mappings.
The pte for x86 reserves a single bit for protection and its two states are
read only or read/write. Thus, write only is not supported in h/w.
Currently, if i 'mmap' a page write-only, the first read attempt on that page
creates a page fault and will SEGV. That check is enforced in
arch/blah/mm/fault.c. However, if i first write that page it will fault in
and the pte will be set to read/write. Thus, any subsequent reads to the page
will succeed. It is this inconsistency in behavior that this patch is
attempting to address. Furthermore, if the page is swapped out, and then
brought back the first read will also cause a SEGV. Thus, any arbitrary read
on a page can potentially result in a SEGV.
According to the SuSv3 spec, "if the application requests only PROT_WRITE, the
implementation may also allow read access." Also as mentioned, some
archtectures, such as alpha, shown above already take the approach that i am
suggesting.
The counter-argument to this raised by Arjan, is that the kernel is enforcing
the write only mapping the best it can given the h/w limitations. This is
true, however Alan Cox, and myself would argue that the inconsitency in
behavior, that is applications can sometimes work/sometimes fails is highly
undesireable. If you read through the thread, i think people, came to an
agreement on the last patch i posted, as nobody has objected to it...
Signed-off-by: Jason Baron <jbaron@redhat.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: "Luck, Tony" <tony.luck@intel.com>
Cc: Hugh Dickins <hugh@veritas.com>
Cc: Roman Zippel <zippel@linux-m68k.org>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Andi Kleen <ak@muc.de>
Acked-by: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: Arjan van de Ven <arjan@linux.intel.com>
Acked-by: Paul Mundt <lethal@linux-sh.org>
Cc: Kazumoto Kojima <kkojima@rr.iij4u.or.jp>
Cc: Ian Molton <spyro@f2s.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-09-29 08:58:58 +00:00
|
|
|
if (!(vma->vm_flags & (VM_READ | VM_EXEC | VM_WRITE)))
|
2005-09-26 06:04:21 +00:00
|
|
|
goto bad_area;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If for any reason at all we couldn't handle the fault,
|
|
|
|
* make sure we exit gracefully rather than endlessly redo
|
|
|
|
* the fault.
|
|
|
|
*/
|
2009-04-10 16:01:23 +00:00
|
|
|
ret = handle_mm_fault(mm, vma, address, is_write ? FAULT_FLAG_WRITE : 0);
|
2007-07-19 08:47:05 +00:00
|
|
|
if (unlikely(ret & VM_FAULT_ERROR)) {
|
|
|
|
if (ret & VM_FAULT_OOM)
|
|
|
|
goto out_of_memory;
|
|
|
|
else if (ret & VM_FAULT_SIGBUS)
|
|
|
|
goto do_sigbus;
|
2005-09-26 06:04:21 +00:00
|
|
|
BUG();
|
|
|
|
}
|
2008-10-22 05:53:45 +00:00
|
|
|
if (ret & VM_FAULT_MAJOR) {
|
2007-07-19 08:47:05 +00:00
|
|
|
current->maj_flt++;
|
2011-06-27 12:41:57 +00:00
|
|
|
perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1,
|
2009-04-08 13:01:33 +00:00
|
|
|
regs, address);
|
2008-10-22 05:53:45 +00:00
|
|
|
#ifdef CONFIG_PPC_SMLPAR
|
|
|
|
if (firmware_has_feature(FW_FEATURE_CMO)) {
|
|
|
|
preempt_disable();
|
2008-11-14 12:07:34 +00:00
|
|
|
get_lppaca()->page_ins += (1 << PAGE_FACTOR);
|
2008-10-22 05:53:45 +00:00
|
|
|
preempt_enable();
|
|
|
|
}
|
|
|
|
#endif
|
2009-03-13 11:21:34 +00:00
|
|
|
} else {
|
2007-07-19 08:47:05 +00:00
|
|
|
current->min_flt++;
|
2011-06-27 12:41:57 +00:00
|
|
|
perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1,
|
2009-04-08 13:01:33 +00:00
|
|
|
regs, address);
|
2009-03-13 11:21:34 +00:00
|
|
|
}
|
2005-09-26 06:04:21 +00:00
|
|
|
up_read(&mm->mmap_sem);
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
bad_area:
|
|
|
|
up_read(&mm->mmap_sem);
|
|
|
|
|
|
|
|
bad_area_nosemaphore:
|
|
|
|
/* User mode accesses cause a SIGSEGV */
|
|
|
|
if (user_mode(regs)) {
|
|
|
|
_exception(SIGSEGV, regs, code, address);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-06-04 05:36:54 +00:00
|
|
|
if (is_exec && (error_code & DSISR_PROTFAULT))
|
|
|
|
printk_ratelimited(KERN_CRIT "kernel tried to execute NX-protected"
|
|
|
|
" page (%lx) - exploit attempt? (uid: %d)\n",
|
|
|
|
address, current_uid());
|
2005-09-26 06:04:21 +00:00
|
|
|
|
|
|
|
return SIGSEGV;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We ran out of memory, or some other thing happened to us that made
|
|
|
|
* us unable to handle the page fault gracefully.
|
|
|
|
*/
|
|
|
|
out_of_memory:
|
|
|
|
up_read(&mm->mmap_sem);
|
2010-05-06 07:15:58 +00:00
|
|
|
if (!user_mode(regs))
|
|
|
|
return SIGKILL;
|
|
|
|
pagefault_out_of_memory();
|
|
|
|
return 0;
|
2005-09-26 06:04:21 +00:00
|
|
|
|
|
|
|
do_sigbus:
|
|
|
|
up_read(&mm->mmap_sem);
|
|
|
|
if (user_mode(regs)) {
|
|
|
|
info.si_signo = SIGBUS;
|
|
|
|
info.si_errno = 0;
|
|
|
|
info.si_code = BUS_ADRERR;
|
|
|
|
info.si_addr = (void __user *)address;
|
|
|
|
force_sig_info(SIGBUS, &info, current);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
return SIGBUS;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* bad_page_fault is called when we have a bad access from the kernel.
|
|
|
|
* It is called from the DSI and ISI handlers in head.S and from some
|
|
|
|
* of the procedures in traps.c.
|
|
|
|
*/
|
|
|
|
void bad_page_fault(struct pt_regs *regs, unsigned long address, int sig)
|
|
|
|
{
|
|
|
|
const struct exception_table_entry *entry;
|
2010-08-24 13:15:28 +00:00
|
|
|
unsigned long *stackend;
|
2005-09-26 06:04:21 +00:00
|
|
|
|
|
|
|
/* Are we prepared to handle this fault? */
|
|
|
|
if ((entry = search_exception_tables(regs->nip)) != NULL) {
|
|
|
|
regs->nip = entry->fixup;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* kernel has accessed a bad area */
|
2005-11-06 22:54:36 +00:00
|
|
|
|
|
|
|
switch (regs->trap) {
|
2006-11-07 23:22:59 +00:00
|
|
|
case 0x300:
|
|
|
|
case 0x380:
|
|
|
|
printk(KERN_ALERT "Unable to handle kernel paging request for "
|
|
|
|
"data at address 0x%08lx\n", regs->dar);
|
|
|
|
break;
|
|
|
|
case 0x400:
|
|
|
|
case 0x480:
|
|
|
|
printk(KERN_ALERT "Unable to handle kernel paging request for "
|
|
|
|
"instruction fetch\n");
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
printk(KERN_ALERT "Unable to handle kernel paging request for "
|
|
|
|
"unknown fault\n");
|
|
|
|
break;
|
2005-11-06 22:54:36 +00:00
|
|
|
}
|
|
|
|
printk(KERN_ALERT "Faulting instruction address: 0x%08lx\n",
|
|
|
|
regs->nip);
|
|
|
|
|
2010-08-24 13:15:28 +00:00
|
|
|
stackend = end_of_stack(current);
|
|
|
|
if (current != &init_task && *stackend != STACK_END_MAGIC)
|
|
|
|
printk(KERN_ALERT "Thread overran stack, or stack corrupted\n");
|
|
|
|
|
2005-09-26 06:04:21 +00:00
|
|
|
die("Kernel access of bad area", regs, sig);
|
|
|
|
}
|