License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 14:07:57 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2016-04-26 19:23:24 +00:00
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#ifndef _ASM_X86_TEXT_PATCHING_H
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#define _ASM_X86_TEXT_PATCHING_H
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#include <linux/types.h>
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#include <linux/stddef.h>
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#include <asm/ptrace.h>
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struct paravirt_patch_site;
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#ifdef CONFIG_PARAVIRT
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void apply_paravirt(struct paravirt_patch_site *start,
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struct paravirt_patch_site *end);
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#else
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static inline void apply_paravirt(struct paravirt_patch_site *start,
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struct paravirt_patch_site *end)
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{}
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#define __parainstructions NULL
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#define __parainstructions_end NULL
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#endif
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x86/alternative: Batch of patch operations
Currently, the patch of an address is done in three steps:
-- Pseudo-code #1 - Current implementation ---
1) add an int3 trap to the address that will be patched
sync cores (send IPI to all other CPUs)
2) update all but the first byte of the patched range
sync cores (send IPI to all other CPUs)
3) replace the first byte (int3) by the first byte of replacing opcode
sync cores (send IPI to all other CPUs)
-- Pseudo-code #1 ---
When a static key has more than one entry, these steps are called once for
each entry. The number of IPIs then is linear with regard to the number 'n' of
entries of a key: O(n*3), which is O(n).
This algorithm works fine for the update of a single key. But we think
it is possible to optimize the case in which a static key has more than
one entry. For instance, the sched_schedstats jump label has 56 entries
in my (updated) fedora kernel, resulting in 168 IPIs for each CPU in
which the thread that is enabling the key is _not_ running.
With this patch, rather than receiving a single patch to be processed, a vector
of patches is passed, enabling the rewrite of the pseudo-code #1 in this
way:
-- Pseudo-code #2 - This patch ---
1) for each patch in the vector:
add an int3 trap to the address that will be patched
sync cores (send IPI to all other CPUs)
2) for each patch in the vector:
update all but the first byte of the patched range
sync cores (send IPI to all other CPUs)
3) for each patch in the vector:
replace the first byte (int3) by the first byte of replacing opcode
sync cores (send IPI to all other CPUs)
-- Pseudo-code #2 - This patch ---
Doing the update in this way, the number of IPI becomes O(3) with regard
to the number of keys, which is O(1).
The batch mode is done with the function text_poke_bp_batch(), that receives
two arguments: a vector of "struct text_to_poke", and the number of entries
in the vector.
The vector must be sorted by the addr field of the text_to_poke structure,
enabling the binary search of a handler in the poke_int3_handler function
(a fast path).
Signed-off-by: Daniel Bristot de Oliveira <bristot@redhat.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Masami Hiramatsu <mhiramat@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Chris von Recklinghausen <crecklin@redhat.com>
Cc: Clark Williams <williams@redhat.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Jason Baron <jbaron@akamai.com>
Cc: Jiri Kosina <jkosina@suse.cz>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Scott Wood <swood@redhat.com>
Cc: Steven Rostedt (VMware) <rostedt@goodmis.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/ca506ed52584c80f64de23f6f55ca288e5d079de.1560325897.git.bristot@redhat.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-06-12 09:57:29 +00:00
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/*
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* Currently, the max observed size in the kernel code is
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* JUMP_LABEL_NOP_SIZE/RELATIVEJUMP_SIZE, which are 5.
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* Raise it if needed.
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*/
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#define POKE_MAX_OPCODE_SIZE 5
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2019-04-26 00:11:33 +00:00
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extern void text_poke_early(void *addr, const void *opcode, size_t len);
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2016-04-26 19:23:24 +00:00
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/*
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* Clear and restore the kernel write-protection flag on the local CPU.
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* Allows the kernel to edit read-only pages.
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* Side-effect: any interrupt handler running between save and restore will have
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* the ability to write to read-only pages.
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*
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* Warning:
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* Code patching in the UP case is safe if NMIs and MCE handlers are stopped and
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* no thread can be preempted in the instructions being modified (no iret to an
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* invalid instruction possible) or if the instructions are changed from a
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* consistent state to another consistent state atomically.
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2019-09-02 12:02:59 +00:00
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* On the local CPU you need to be protected against NMI or MCE handlers seeing
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* an inconsistent instruction while you patch.
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2016-04-26 19:23:24 +00:00
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*/
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extern void *text_poke(void *addr, const void *opcode, size_t len);
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x86/kprobes: Fix ordering while text-patching
Kprobes does something like:
register:
arch_arm_kprobe()
text_poke(INT3)
/* guarantees nothing, INT3 will become visible at some point, maybe */
kprobe_optimizer()
/* guarantees the bytes after INT3 are unused */
synchronize_rcu_tasks();
text_poke_bp(JMP32);
/* implies IPI-sync, kprobe really is enabled */
unregister:
__disarm_kprobe()
unoptimize_kprobe()
text_poke_bp(INT3 + tail);
/* implies IPI-sync, so tail is guaranteed visible */
arch_disarm_kprobe()
text_poke(old);
/* guarantees nothing, old will maybe become visible */
synchronize_rcu()
free-stuff
Now the problem is that on register, the synchronize_rcu_tasks() does
not imply sufficient to guarantee all CPUs have already observed INT3
(although in practice this is exceedingly unlikely not to have
happened) (similar to how MEMBARRIER_CMD_PRIVATE_EXPEDITED does not
imply MEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE).
Worse, even if it did, we'd have to do 2 synchronize calls to provide
the guarantee we're looking for, the first to ensure INT3 is visible,
the second to guarantee nobody is then still using the instruction
bytes after INT3.
Similar on unregister; the synchronize_rcu() between
__unregister_kprobe_top() and __unregister_kprobe_bottom() does not
guarantee all CPUs are free of the INT3 (and observe the old text).
Therefore, sprinkle some IPI-sync love around. This guarantees that
all CPUs agree on the text and RCU once again provides the required
guaranteed.
Tested-by: Alexei Starovoitov <ast@kernel.org>
Tested-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Acked-by: Masami Hiramatsu <mhiramat@kernel.org>
Acked-by: Alexei Starovoitov <ast@kernel.org>
Acked-by: Paul E. McKenney <paulmck@kernel.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20191111132458.162172862@infradead.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-10-09 19:15:28 +00:00
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extern void text_poke_sync(void);
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2019-04-26 00:11:21 +00:00
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extern void *text_poke_kgdb(void *addr, const void *opcode, size_t len);
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2016-04-26 19:23:24 +00:00
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extern int poke_int3_handler(struct pt_regs *regs);
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x86/alternatives: Teach text_poke_bp() to emulate instructions
In preparation for static_call and variable size jump_label support,
teach text_poke_bp() to emulate instructions, namely:
JMP32, JMP8, CALL, NOP2, NOP_ATOMIC5, INT3
The current text_poke_bp() takes a @handler argument which is used as
a jump target when the temporary INT3 is hit by a different CPU.
When patching CALL instructions, this doesn't work because we'd miss
the PUSH of the return address. Instead, teach poke_int3_handler() to
emulate an instruction, typically the instruction we're patching in.
This fits almost all text_poke_bp() users, except
arch_unoptimize_kprobe() which restores random text, and for that site
we have to build an explicit emulate instruction.
Tested-by: Alexei Starovoitov <ast@kernel.org>
Tested-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Masami Hiramatsu <mhiramat@kernel.org>
Reviewed-by: Daniel Bristot de Oliveira <bristot@redhat.com>
Acked-by: Alexei Starovoitov <ast@kernel.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20191111132457.529086974@infradead.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
(cherry picked from commit 8c7eebc10687af45ac8e40ad1bac0cf7893dba9f)
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
2019-06-05 08:48:37 +00:00
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extern void text_poke_bp(void *addr, const void *opcode, size_t len, const void *emulate);
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2019-08-26 11:38:58 +00:00
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extern void text_poke_queue(void *addr, const void *opcode, size_t len, const void *emulate);
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extern void text_poke_finish(void);
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x86/alternatives: Teach text_poke_bp() to emulate instructions
In preparation for static_call and variable size jump_label support,
teach text_poke_bp() to emulate instructions, namely:
JMP32, JMP8, CALL, NOP2, NOP_ATOMIC5, INT3
The current text_poke_bp() takes a @handler argument which is used as
a jump target when the temporary INT3 is hit by a different CPU.
When patching CALL instructions, this doesn't work because we'd miss
the PUSH of the return address. Instead, teach poke_int3_handler() to
emulate an instruction, typically the instruction we're patching in.
This fits almost all text_poke_bp() users, except
arch_unoptimize_kprobe() which restores random text, and for that site
we have to build an explicit emulate instruction.
Tested-by: Alexei Starovoitov <ast@kernel.org>
Tested-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Masami Hiramatsu <mhiramat@kernel.org>
Reviewed-by: Daniel Bristot de Oliveira <bristot@redhat.com>
Acked-by: Alexei Starovoitov <ast@kernel.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20191111132457.529086974@infradead.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
(cherry picked from commit 8c7eebc10687af45ac8e40ad1bac0cf7893dba9f)
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
2019-06-05 08:48:37 +00:00
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#define INT3_INSN_SIZE 1
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#define INT3_INSN_OPCODE 0xCC
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2020-08-18 13:57:47 +00:00
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#define RET_INSN_SIZE 1
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#define RET_INSN_OPCODE 0xC3
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x86/alternatives: Teach text_poke_bp() to emulate instructions
In preparation for static_call and variable size jump_label support,
teach text_poke_bp() to emulate instructions, namely:
JMP32, JMP8, CALL, NOP2, NOP_ATOMIC5, INT3
The current text_poke_bp() takes a @handler argument which is used as
a jump target when the temporary INT3 is hit by a different CPU.
When patching CALL instructions, this doesn't work because we'd miss
the PUSH of the return address. Instead, teach poke_int3_handler() to
emulate an instruction, typically the instruction we're patching in.
This fits almost all text_poke_bp() users, except
arch_unoptimize_kprobe() which restores random text, and for that site
we have to build an explicit emulate instruction.
Tested-by: Alexei Starovoitov <ast@kernel.org>
Tested-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Masami Hiramatsu <mhiramat@kernel.org>
Reviewed-by: Daniel Bristot de Oliveira <bristot@redhat.com>
Acked-by: Alexei Starovoitov <ast@kernel.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20191111132457.529086974@infradead.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
(cherry picked from commit 8c7eebc10687af45ac8e40ad1bac0cf7893dba9f)
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
2019-06-05 08:48:37 +00:00
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#define CALL_INSN_SIZE 5
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#define CALL_INSN_OPCODE 0xE8
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#define JMP32_INSN_SIZE 5
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#define JMP32_INSN_OPCODE 0xE9
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#define JMP8_INSN_SIZE 2
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#define JMP8_INSN_OPCODE 0xEB
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2019-05-01 13:11:17 +00:00
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2019-10-09 11:57:17 +00:00
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#define DISP32_SIZE 4
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2020-01-21 14:53:09 +00:00
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static __always_inline int text_opcode_size(u8 opcode)
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2019-10-09 10:44:17 +00:00
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{
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int size = 0;
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#define __CASE(insn) \
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case insn##_INSN_OPCODE: size = insn##_INSN_SIZE; break
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switch(opcode) {
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__CASE(INT3);
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2020-08-18 13:57:47 +00:00
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__CASE(RET);
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2019-10-09 10:44:17 +00:00
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__CASE(CALL);
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__CASE(JMP32);
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__CASE(JMP8);
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}
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#undef __CASE
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return size;
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}
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2019-10-09 10:44:14 +00:00
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union text_poke_insn {
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u8 text[POKE_MAX_OPCODE_SIZE];
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struct {
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u8 opcode;
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|
|
s32 disp;
|
|
|
|
|
} __attribute__((packed));
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static __always_inline
|
|
|
|
|
void *text_gen_insn(u8 opcode, const void *addr, const void *dest)
|
|
|
|
|
{
|
|
|
|
|
static union text_poke_insn insn; /* per instance */
|
|
|
|
|
int size = text_opcode_size(opcode);
|
|
|
|
|
|
|
|
|
|
insn.opcode = opcode;
|
|
|
|
|
|
|
|
|
|
if (size > 1) {
|
|
|
|
|
insn.disp = (long)dest - (long)(addr + size);
|
|
|
|
|
if (size == 2) {
|
|
|
|
|
/*
|
|
|
|
|
* Ensure that for JMP9 the displacement
|
|
|
|
|
* actually fits the signed byte.
|
|
|
|
|
*/
|
|
|
|
|
BUG_ON((insn.disp >> 31) != (insn.disp >> 7));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return &insn.text;
|
|
|
|
|
}
|
2019-10-09 10:44:17 +00:00
|
|
|
|
|
|
|
|
extern int after_bootmem;
|
|
|
|
|
extern __ro_after_init struct mm_struct *poking_mm;
|
|
|
|
|
extern __ro_after_init unsigned long poking_addr;
|
|
|
|
|
|
|
|
|
|
#ifndef CONFIG_UML_X86
|
2020-01-21 14:53:09 +00:00
|
|
|
static __always_inline
|
|
|
|
|
void int3_emulate_jmp(struct pt_regs *regs, unsigned long ip)
|
2019-10-09 10:44:17 +00:00
|
|
|
{
|
|
|
|
|
regs->ip = ip;
|
|
|
|
|
}
|
|
|
|
|
|
2020-01-21 14:53:09 +00:00
|
|
|
static __always_inline
|
|
|
|
|
void int3_emulate_push(struct pt_regs *regs, unsigned long val)
|
2019-05-01 13:11:17 +00:00
|
|
|
{
|
|
|
|
|
/*
|
|
|
|
|
* The int3 handler in entry_64.S adds a gap between the
|
|
|
|
|
* stack where the break point happened, and the saving of
|
|
|
|
|
* pt_regs. We can extend the original stack because of
|
|
|
|
|
* this gap. See the idtentry macro's create_gap option.
|
2019-09-03 11:43:24 +00:00
|
|
|
*
|
|
|
|
|
* Similarly entry_32.S will have a gap on the stack for (any) hardware
|
|
|
|
|
* exception and pt_regs; see FIXUP_FRAME.
|
2019-05-01 13:11:17 +00:00
|
|
|
*/
|
|
|
|
|
regs->sp -= sizeof(unsigned long);
|
|
|
|
|
*(unsigned long *)regs->sp = val;
|
|
|
|
|
}
|
|
|
|
|
|
2020-08-18 13:57:47 +00:00
|
|
|
static __always_inline
|
|
|
|
|
unsigned long int3_emulate_pop(struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
unsigned long val = *(unsigned long *)regs->sp;
|
|
|
|
|
regs->sp += sizeof(unsigned long);
|
|
|
|
|
return val;
|
|
|
|
|
}
|
|
|
|
|
|
2020-01-21 14:53:09 +00:00
|
|
|
static __always_inline
|
|
|
|
|
void int3_emulate_call(struct pt_regs *regs, unsigned long func)
|
2019-05-01 13:11:17 +00:00
|
|
|
{
|
|
|
|
|
int3_emulate_push(regs, regs->ip - INT3_INSN_SIZE + CALL_INSN_SIZE);
|
|
|
|
|
int3_emulate_jmp(regs, func);
|
|
|
|
|
}
|
2020-08-18 13:57:47 +00:00
|
|
|
|
|
|
|
|
static __always_inline
|
|
|
|
|
void int3_emulate_ret(struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
unsigned long ip = int3_emulate_pop(regs);
|
|
|
|
|
int3_emulate_jmp(regs, ip);
|
|
|
|
|
}
|
2019-05-11 12:32:40 +00:00
|
|
|
#endif /* !CONFIG_UML_X86 */
|
2019-05-01 13:11:17 +00:00
|
|
|
|
2016-04-26 19:23:24 +00:00
|
|
|
#endif /* _ASM_X86_TEXT_PATCHING_H */
|