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treewide: Add SPDX license identifier - Makefile/Kconfig Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-19 12:07:45 +00:00
# SPDX-License-Identifier: GPL-2.0-only
soc: Introduce drivers/soc place-holder for SOC specific drivers Based on earlier thread "https://lkml.org/lkml/2013/10/7/662" and discussion at Kernel Summit'2013, it was agreed to create 'driver/soc' for drivers which are quite SOC specific. Further discussion on the subject is in response to the earlier version of the patch is here: http://lwn.net/Articles/588942/ Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Paul Walmsley <paul@pwsan.com> Cc: Olof Johansson <olof@lixom.net> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Kumar Gala <galak@codeaurora.org>
2014-04-23 23:46:17 +00:00
menu "SOC (System On Chip) specific Drivers"
soc: actions: Add Owl SPS Implement S500 Smart Power System power-gating. For now flag PD_CPU2 and PD_CPU3 as always-on. Based on LeMaker linux-actions tree. Signed-off-by: Andreas Färber <afaerber@suse.de>
2017-02-26 03:09:57 +00:00
source "drivers/soc/actions/Kconfig"
soc: Add Amlogic SoC Information driver Amlogic SoCs have a SoC information register for SoC type, package type and revision information. This patchs adds support for this register decoding and exposing with the SoC bus infrastructure. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-23 08:28:18 +00:00
source "drivers/soc/amlogic/Kconfig"
soc: add aspeed folder and misc drivers Create a SoC folder for the ASPEED parts and place the misc drivers currently present into this folder. These drivers are not generic part drivers, but rather only apply to the ASPEED SoCs. Signed-off-by: Patrick Venture <venture@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Olof Johansson <olof@lixom.net>
2019-04-22 17:54:19 +00:00
source "drivers/soc/aspeed/Kconfig"
ARM: at91: move SoC detection to its own driver To simplify machine init and as the soc_device struct is not used as the parent for on-chip devices anymore, move SoC detection to its own driver. Change in dmesg: - before: DMA: preallocated 256 KiB pool for atomic coherent allocations AT91: Detected SoC family: sama5d2 AT91: Detected SoC: sama5d27, revision 0 No ATAGs? clocksource: tcb_clksrc: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 184217874325 ns at_xdmac f0010000.dma-controller: 16 channels, mapped at 0xe085b000 SCSI subsystem initialized - after: DMA: preallocated 256 KiB pool for atomic coherent allocations No ATAGs? clocksource: tcb_clksrc: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 184217874325 ns at_xdmac f0010000.dma-controller: 16 channels, mapped at 0xe0859000 AT91: Detected SoC family: sama5d2 AT91: Detected SoC: sama5d27, revision 0 SCSI subsystem initialized Suggested-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2017-02-16 10:31:06 +00:00
source "drivers/soc/atmel/Kconfig"
ARM: bcm2835: add rpi power domain driver This patch adds support for several power domains on Raspberry Pi, including USB (so it can be enabled even if the bootloader didn't do it), and graphics. This patch is the combined work of Eric Anholt (who wrote USB support inside of the Raspberry Pi firmware driver, and wrote the non-USB domain support) and Alexander Aring (who separated the original USB work out from the firmware driver). Signed-off-by: Alexander Aring <alex.aring@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Kevin Hilman <khilman@linaro.org>
2015-12-17 00:26:47 +00:00
source "drivers/soc/bcm/Kconfig"
riscv: Use vendor name for K210 SoC support Rename configuration options and directories related to the Kendryte K210 SoC to use the SoC vendor name (canaan) instead of the "kendryte" branding name. Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-12-13 13:50:38 +00:00
source "drivers/soc/canaan/Kconfig"
soc: fsl: add GUTS driver for QorIQ platforms The global utilities block controls power management, I/O device enabling, power-onreset(POR) configuration monitoring, alternate function selection for multiplexed signals,and clock control. This patch adds a driver to manage and access global utilities block. Initially only reading SVR and registering soc device are supported. Other guts accesses, such as reading RCW, should eventually be moved into this driver as well. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-11-09 03:14:08 +00:00
source "drivers/soc/fsl/Kconfig"
soc: imx: Add GPCv2 power gating driver Add code allowing for control of various power domains managed by GPCv2 IP block found in i.MX7 series of SoCs. Power domains covered by this patch are: - PCIE PHY - MIPI PHY - USB HSIC PHY - USB OTG1/2 PHY Support for any other power domain controlled by GPC is not present, and can be added at some later point. Testing of this code was done against a PCIe driver. Cc: yurovsky@gmail.com Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Dong Aisheng <dongas86@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-03-28 15:19:45 +00:00
source "drivers/soc/imx/Kconfig"
ARM: ixp4xx: Move NPE and QMGR to drivers/soc The Network Processing Engine and Queue Manager are versatile firmware components used by several IXP4xx drivers. Drivers are relying on getting access to these components using <mach/*> headers which does not work with multiplatform. We need to find a better place for the drivers to live. Let's first move them to drivers/soc and the start to refactor a bit by passing resources and moving headers. This patch introduce static IRQ assignments but that will be fixed by later patches in this series. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-02-10 13:45:47 +00:00
source "drivers/soc/ixp4xx/Kconfig"
drivers/soc/litex: add LiteX SoC Controller driver This commit adds driver for the FPGA-based LiteX SoC Controller from LiteX SoC builder. Co-developed-by: Mateusz Holenko <mholenko@antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com> Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com> Signed-off-by: Stafford Horne <shorne@gmail.com>
2020-10-13 14:45:52 +00:00
source "drivers/soc/litex/Kconfig"
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
source "drivers/soc/mediatek/Kconfig"
soc: qcom: Add GSBI driver The GSBI (General Serial Bus Interface) driver controls the overarching configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and earlier QCOM processors. The GSBI supports UART, I2C, SPI, and UIM functionality in various combinations. Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
2014-04-24 16:31:21 +00:00
source "drivers/soc/qcom/Kconfig"
soc: renesas: Rework Kconfig and Makefile logic The goals are to: - Allow precise control over and automatic selection of which (sub)drivers are used for which SoC, - Allow adding support for new SoCs easily, - Allow compile-testing of all (sub)drivers, - Keep driver selection logic in the subsystem-specific Kconfig, independent from the architecture-specific Kconfig (i.e. no "select" from arch/arm64/Kconfig.platforms), to avoid dependencies. This is implemented by: - Introducing Kconfig symbols for all drivers and sub-drivers, - Introducing the Kconfig symbol SOC_RENESAS, which is enabled automatically when building for a Renesas ARM platform, and which enables all required drivers without interaction of the user, based on SoC-specific ARCH_* symbols, - Allowing the user to enable any Kconfig symbol manually if COMPILE_TEST is enabled, - Using the new Kconfig symbols instead of the ARCH_* symbols to control compilation in the Makefile, - Always entering drivers/soc/renesas/ during the build. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-05-19 08:35:10 +00:00
source "drivers/soc/renesas/Kconfig"
soc: rockchip: power-domain: Add power domain driver This driver is found on RK3288 SoCs. In order to meet high performance and low power requirements, a power management unit is designed or saving power when RK3288 in low power mode. The RK3288 PMU is dedicated for managing the power of the whole chip. PMU can work in the Low Power Mode by setting bit[0] of PMU_PWRMODE_CON register. After setting the register, PMU would enter the Low Power mode. In the low power mode, pmu will auto power on/off the specified power domain, send idle req to specified power domain, shut down/up pll and so on. All of above are configurable by setting corresponding registers. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> [replace dsb() with dsb(sy) for arm64 buildability; sy is the default, so no functional change; adapt to per-user clocks in genpd] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-09-08 06:18:22 +00:00
source "drivers/soc/rockchip/Kconfig"
drivers: soc: Add support for Exynos PMU driver This patch moves Exynos PMU driver implementation from "arm/mach-exynos" to "drivers/soc/samsung". This driver is mainly used for setting misc bits of register from PMU IP of Exynos SoC which will be required to configure before Suspend/Resume. Currently all these settings are done in "arch/arm/mach-exynos/pmu.c" but moving ahead for ARM64 based SoC support, there is a need of this PMU driver in driver/* folder. This driver uses existing DT binding information and there should be no functionality change in the supported platforms. Signed-off-by: Amit Daniel Kachhap <amitdanielk@gmail.com> [tested on Peach-Pi (Exynos5880)] Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> [for testing on Trats2 (Exynos4412) and Odroid XU3 (Exynos5422)] Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> [k.kozlowski: Rebased, add necessary infrastructure for building and selecting drivers/soc because original patchset was on top of movement SROMc to drivers/soc] Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
2015-12-18 03:32:16 +00:00
source "drivers/soc/samsung/Kconfig"
riscv: move sifive_l2_cache.c to drivers/soc The sifive_l2_cache.c is in no way related to RISC-V architecture memory management. It is a little stub driver working around the fact that the EDAC maintainers prefer their drivers to be structured in a certain way that doesn't fit the SiFive SOCs. Move the file to drivers/soc and add a Kconfig option for it, as well as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE. Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Borislav Petkov <bp@suse.de> [paul.walmsley@sifive.com: keep the MAINTAINERS change specific to the L2$ controller code] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2019-11-07 09:20:39 +00:00
source "drivers/soc/sifive/Kconfig"
drivers: soc: sunxi: Introduce SoC driver to map SRAMs The Allwinner SoCs have a handful of SRAM that can be either mapped to be accessible by devices or the CPU. That mapping is controlled by an SRAM controller, and that mapping might not be set by the bootloader, for example if the device wasn't used at all, or if we're using solutions like the U-Boot's Falcon Boot. We could also imagine changing this at runtime for example to change the mapping of these SRAMs to use them for suspend/resume or runtime memory rate change, if that ever happens. These use cases require some API in the kernel to control that mapping, exported through a drivers/soc driver. This driver also implement a debugfs file that shows the SRAM found in the system, the current mapping and the SRAM that have been claimed by some drivers in the kernel. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-06-01 09:04:26 +00:00
source "drivers/soc/sunxi/Kconfig"
soc/tegra: Provide per-SoC Kconfig symbols Move per-SoC generation Kconfig symbols to drivers/soc/tegra/Kconfig to gather them all in a single place. This directory is a natural location for these options since it already contains the drivers that are shared across 32-bit and 64-bit ARM architectures. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-09-09 13:29:22 +00:00
source "drivers/soc/tegra/Kconfig"
soc: ti: add Keystone Navigator QMSS driver The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of the main hardware sub system which forms the backbone of the Keystone Multi-core Navigator. QMSS consist of queue managers, packed-data structure processors(PDSP), linking RAM, descriptor pools and infrastructure Packet DMA. The Queue Manager is a hardware module that is responsible for accelerating management of the packet queues. Packets are queued/de-queued by writing or reading descriptor address to a particular memory mapped location. The PDSPs perform QMSS related functions like accumulation, QoS, or event management. Linking RAM registers are used to link the descriptors which are stored in descriptor RAM. Descriptor RAM is configurable as internal or external memory. The QMSS driver manages the PDSP setups, linking RAM regions, queue pool management (allocation, push, pop and notify) and descriptor pool management. The specifics on the device tree bindings for QMSS can be found in: Documentation/devicetree/bindings/soc/keystone-navigator-qmss.txt Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Olof Johansson <olof@lixom.net> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2014-02-28 15:47:50 +00:00
source "drivers/soc/ti/Kconfig"
ARM: ux500: move soc_id driver to drivers/soc As the ux500 id code is basically a standalone driver, we can move it out of the arch code into drivers/soc/ux500. This is a user-visible change, as it moves all the devices in sysfs from /sys/devices/soc0/ to /sys/devices/ and leaves the soc0 node as a separate device. Originally the idea was to put all on-chip devices under the soc node, and ux500 was the first platform to have this device, but later platforms almost all didn't follow that pattern, so this makes the platform do the same thing as everyone else. Since the platform is really obsolete now, I am optimistic that nothing will break after moving the devices around. As the SoC driver no longer has access to the private header files, I'm changing the code to instead look up the address of the backupram from devicetree, which is a good idea anyway. Finally, having a separate Kconfig symbol means the driver is now optional and could even be a loadable module rather than always being built-in if we allowed that for soc_device. Signed-off-by: Arnd Bergmann <arnd@arndb.de> [Fixup mising Makefile, fixup BB_UID_BASE to fc0] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-06-22 14:32:36 +00:00
source "drivers/soc/ux500/Kconfig"
soc: add driver for the ARM RealView This adds a SoC driver to be used by the ARM RealView reference boards. We create the "versatile" directory to hold the different ARM reference designs as per the pattern of the clk directory layout. The driver utilze the syscon to get to the register needed. After this we can use sysfs to get at some SoC properties on RealView DT variants like this: > cd /sysbus/soc/devices/soc0 > ls board family machine power subsystem build fpga manufacturer soc_id uevent > cat family Versatile > cat fpga Multi-layer AXI > cat board HBI-0147 > cat build 03 Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Conflicts: drivers/soc/Kconfig drivers/soc/Makefile
2014-07-25 13:04:52 +00:00
source "drivers/soc/versatile/Kconfig"
soc: xilinx: Create folder structure for soc specific drivers Create directory structure with Makefile/Kconfig for adding xilinx soc specific drivers. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-12-19 13:15:25 +00:00
source "drivers/soc/xilinx/Kconfig"
soc: qcom: Add GSBI driver The GSBI (General Serial Bus Interface) driver controls the overarching configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and earlier QCOM processors. The GSBI supports UART, I2C, SPI, and UIM functionality in various combinations. Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
2014-04-24 16:31:21 +00:00
soc: Introduce drivers/soc place-holder for SOC specific drivers Based on earlier thread "https://lkml.org/lkml/2013/10/7/662" and discussion at Kernel Summit'2013, it was agreed to create 'driver/soc' for drivers which are quite SOC specific. Further discussion on the subject is in response to the earlier version of the patch is here: http://lwn.net/Articles/588942/ Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Paul Walmsley <paul@pwsan.com> Cc: Olof Johansson <olof@lixom.net> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Kumar Gala <galak@codeaurora.org>
2014-04-23 23:46:17 +00:00
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