2011-06-05 00:38:28 +00:00
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/*
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2014-01-17 15:30:01 +00:00
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* Intel MID GPIO driver
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2011-06-05 00:38:28 +00:00
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*
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2014-01-17 15:30:01 +00:00
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* Copyright (c) 2008-2014 Intel Corporation.
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2009-09-22 23:46:36 +00:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Supports:
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* Moorestown platform Langwell chip.
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2010-05-26 21:42:25 +00:00
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* Medfield platform Penwell chip.
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2013-10-04 20:01:42 +00:00
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* Clovertrail platform Cloverview chip.
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* Merrifield platform Tangier chip.
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2009-09-22 23:46:36 +00:00
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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2010-10-27 22:33:23 +00:00
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#include <linux/platform_device.h>
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2009-09-22 23:46:36 +00:00
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/stddef.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
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#include <linux/slab.h>
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2011-05-10 13:23:45 +00:00
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#include <linux/pm_runtime.h>
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2012-05-02 08:15:50 +00:00
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#include <linux/irqdomain.h>
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2009-09-22 23:46:36 +00:00
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2013-10-04 20:01:42 +00:00
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#define INTEL_MID_IRQ_TYPE_EDGE (1 << 0)
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#define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1)
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2013-10-04 20:01:40 +00:00
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2010-05-26 21:42:25 +00:00
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/*
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* Langwell chip has 64 pins and thus there are 2 32bit registers to control
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* each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
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* registers to control them, so we only define the order here instead of a
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* structure, to get a bit offset for a pin (use GPDR as an example):
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*
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* nreg = ngpio / 32;
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* reg = offset / 32;
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* bit = offset % 32;
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* reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
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*
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* so the bit of reg_addr is to control pin offset's GPDR feature
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*/
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enum GPIO_REG {
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GPLR = 0, /* pin level read-only */
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GPDR, /* pin direction */
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GPSR, /* pin set */
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GPCR, /* pin clear */
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GRER, /* rising edge detect */
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GFER, /* falling edge detect */
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GEDR, /* edge detect result */
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2011-10-03 11:36:07 +00:00
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GAFR, /* alt function */
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2009-09-22 23:46:36 +00:00
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};
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2013-10-04 20:01:42 +00:00
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/* intel_mid gpio driver data */
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struct intel_mid_gpio_ddata {
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2013-10-04 20:01:40 +00:00
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u16 ngpio; /* number of gpio pins */
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u32 gplr_offset; /* offset of first GPLR register from base */
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u32 flis_base; /* base address of FLIS registers */
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u32 flis_len; /* length of FLIS registers */
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u32 (*get_flis_offset)(int gpio);
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u32 chip_irq_type; /* chip interrupt type */
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};
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2013-10-04 20:01:42 +00:00
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struct intel_mid_gpio {
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2009-09-22 23:46:36 +00:00
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struct gpio_chip chip;
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2013-05-22 10:20:11 +00:00
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void __iomem *reg_base;
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2009-09-22 23:46:36 +00:00
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spinlock_t lock;
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2011-05-10 13:23:45 +00:00
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struct pci_dev *pdev;
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2012-05-02 08:15:50 +00:00
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struct irq_domain *domain;
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2009-09-22 23:46:36 +00:00
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};
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2013-10-04 20:01:42 +00:00
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#define to_intel_gpio_priv(chip) container_of(chip, struct intel_mid_gpio, chip)
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2012-12-20 22:45:51 +00:00
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2010-05-26 21:42:25 +00:00
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static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
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2013-05-22 10:20:14 +00:00
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enum GPIO_REG reg_type)
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2009-09-22 23:46:36 +00:00
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{
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2013-10-04 20:01:42 +00:00
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struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
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2010-05-26 21:42:25 +00:00
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unsigned nreg = chip->ngpio / 32;
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2009-09-22 23:46:36 +00:00
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u8 reg = offset / 32;
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2010-05-26 21:42:25 +00:00
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2013-10-04 20:01:42 +00:00
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return priv->reg_base + reg_type * nreg * 4 + reg * 4;
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2010-05-26 21:42:25 +00:00
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}
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2011-10-03 11:36:07 +00:00
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static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
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enum GPIO_REG reg_type)
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{
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2013-10-04 20:01:42 +00:00
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struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
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2011-10-03 11:36:07 +00:00
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unsigned nreg = chip->ngpio / 32;
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u8 reg = offset / 16;
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2013-10-04 20:01:42 +00:00
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return priv->reg_base + reg_type * nreg * 4 + reg * 4;
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2011-10-03 11:36:07 +00:00
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}
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2013-10-04 20:01:42 +00:00
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static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
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2011-10-03 11:36:07 +00:00
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{
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void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
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u32 value = readl(gafr);
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int shift = (offset % 16) << 1, af = (value >> shift) & 3;
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if (af) {
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value &= ~(3 << shift);
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writel(value, gafr);
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}
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return 0;
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}
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2013-10-04 20:01:42 +00:00
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static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
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2010-05-26 21:42:25 +00:00
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{
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void __iomem *gplr = gpio_reg(chip, offset, GPLR);
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2009-09-22 23:46:36 +00:00
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return readl(gplr) & BIT(offset % 32);
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}
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2013-10-04 20:01:42 +00:00
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static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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2009-09-22 23:46:36 +00:00
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{
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void __iomem *gpsr, *gpcr;
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if (value) {
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2010-05-26 21:42:25 +00:00
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gpsr = gpio_reg(chip, offset, GPSR);
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2009-09-22 23:46:36 +00:00
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writel(BIT(offset % 32), gpsr);
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} else {
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2010-05-26 21:42:25 +00:00
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gpcr = gpio_reg(chip, offset, GPCR);
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2009-09-22 23:46:36 +00:00
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writel(BIT(offset % 32), gpcr);
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}
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}
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2013-10-04 20:01:42 +00:00
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static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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2009-09-22 23:46:36 +00:00
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{
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2013-10-04 20:01:42 +00:00
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struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
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2010-05-26 21:42:25 +00:00
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void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
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2009-09-22 23:46:36 +00:00
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u32 value;
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unsigned long flags;
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2013-10-04 20:01:42 +00:00
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if (priv->pdev)
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pm_runtime_get(&priv->pdev->dev);
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2011-05-10 13:23:45 +00:00
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2013-10-04 20:01:42 +00:00
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spin_lock_irqsave(&priv->lock, flags);
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2009-09-22 23:46:36 +00:00
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value = readl(gpdr);
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value &= ~BIT(offset % 32);
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writel(value, gpdr);
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2013-10-04 20:01:42 +00:00
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spin_unlock_irqrestore(&priv->lock, flags);
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2011-05-10 13:23:45 +00:00
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2013-10-04 20:01:42 +00:00
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if (priv->pdev)
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pm_runtime_put(&priv->pdev->dev);
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2011-05-10 13:23:45 +00:00
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2009-09-22 23:46:36 +00:00
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return 0;
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}
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2013-10-04 20:01:42 +00:00
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static int intel_gpio_direction_output(struct gpio_chip *chip,
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2009-09-22 23:46:36 +00:00
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unsigned offset, int value)
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{
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2013-10-04 20:01:42 +00:00
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struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
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2010-05-26 21:42:25 +00:00
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void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
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2009-09-22 23:46:36 +00:00
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unsigned long flags;
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2013-10-04 20:01:42 +00:00
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intel_gpio_set(chip, offset, value);
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2011-05-10 13:23:45 +00:00
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2013-10-04 20:01:42 +00:00
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if (priv->pdev)
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pm_runtime_get(&priv->pdev->dev);
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2011-05-10 13:23:45 +00:00
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2013-10-04 20:01:42 +00:00
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spin_lock_irqsave(&priv->lock, flags);
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2009-09-22 23:46:36 +00:00
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value = readl(gpdr);
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2011-04-09 02:49:08 +00:00
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value |= BIT(offset % 32);
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2009-09-22 23:46:36 +00:00
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writel(value, gpdr);
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2013-10-04 20:01:42 +00:00
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spin_unlock_irqrestore(&priv->lock, flags);
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2011-05-10 13:23:45 +00:00
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2013-10-04 20:01:42 +00:00
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if (priv->pdev)
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pm_runtime_put(&priv->pdev->dev);
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2011-05-10 13:23:45 +00:00
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2009-09-22 23:46:36 +00:00
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return 0;
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}
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2013-10-04 20:01:42 +00:00
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static int intel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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2009-09-22 23:46:36 +00:00
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{
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2013-10-04 20:01:42 +00:00
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struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
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return irq_create_mapping(priv->domain, offset);
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2009-09-22 23:46:36 +00:00
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}
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2013-10-04 20:01:42 +00:00
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static int intel_mid_irq_type(struct irq_data *d, unsigned type)
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2009-09-22 23:46:36 +00:00
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{
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2013-10-04 20:01:42 +00:00
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struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
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2012-05-02 08:15:50 +00:00
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u32 gpio = irqd_to_hwirq(d);
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2009-09-22 23:46:36 +00:00
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unsigned long flags;
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u32 value;
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2013-10-04 20:01:42 +00:00
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void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
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void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
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2009-09-22 23:46:36 +00:00
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2013-10-04 20:01:42 +00:00
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if (gpio >= priv->chip.ngpio)
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2009-09-22 23:46:36 +00:00
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return -EINVAL;
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2011-05-10 13:23:45 +00:00
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2013-10-04 20:01:42 +00:00
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if (priv->pdev)
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pm_runtime_get(&priv->pdev->dev);
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2011-05-10 13:23:45 +00:00
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2013-10-04 20:01:42 +00:00
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spin_lock_irqsave(&priv->lock, flags);
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2009-09-22 23:46:36 +00:00
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if (type & IRQ_TYPE_EDGE_RISING)
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value = readl(grer) | BIT(gpio % 32);
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else
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value = readl(grer) & (~BIT(gpio % 32));
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writel(value, grer);
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if (type & IRQ_TYPE_EDGE_FALLING)
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value = readl(gfer) | BIT(gpio % 32);
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else
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value = readl(gfer) & (~BIT(gpio % 32));
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writel(value, gfer);
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2013-10-04 20:01:42 +00:00
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spin_unlock_irqrestore(&priv->lock, flags);
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2009-09-22 23:46:36 +00:00
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2013-10-04 20:01:42 +00:00
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if (priv->pdev)
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pm_runtime_put(&priv->pdev->dev);
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2011-05-10 13:23:45 +00:00
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2009-09-22 23:46:36 +00:00
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return 0;
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2010-10-27 22:33:22 +00:00
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}
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2009-09-22 23:46:36 +00:00
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2013-10-04 20:01:42 +00:00
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static void intel_mid_irq_unmask(struct irq_data *d)
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2009-09-22 23:46:36 +00:00
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{
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2010-10-27 22:33:22 +00:00
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}
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2009-09-22 23:46:36 +00:00
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2013-10-04 20:01:42 +00:00
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static void intel_mid_irq_mask(struct irq_data *d)
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2009-09-22 23:46:36 +00:00
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{
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2010-10-27 22:33:22 +00:00
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}
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2009-09-22 23:46:36 +00:00
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2013-11-20 14:24:32 +00:00
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static unsigned int intel_mid_irq_startup(struct irq_data *d)
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{
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struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
|
|
|
|
|
|
|
|
if (gpio_lock_as_irq(&priv->chip, irqd_to_hwirq(d)))
|
|
|
|
dev_err(priv->chip.dev,
|
|
|
|
"unable to lock HW IRQ %lu for IRQ\n",
|
|
|
|
irqd_to_hwirq(d));
|
|
|
|
intel_mid_irq_unmask(d);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_mid_irq_shutdown(struct irq_data *d)
|
|
|
|
{
|
|
|
|
struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
|
|
|
|
|
|
|
|
intel_mid_irq_mask(d);
|
|
|
|
gpio_unlock_as_irq(&priv->chip, irqd_to_hwirq(d));
|
|
|
|
}
|
|
|
|
|
2013-10-04 20:01:42 +00:00
|
|
|
static struct irq_chip intel_mid_irqchip = {
|
|
|
|
.name = "INTEL_MID-GPIO",
|
|
|
|
.irq_mask = intel_mid_irq_mask,
|
|
|
|
.irq_unmask = intel_mid_irq_unmask,
|
|
|
|
.irq_set_type = intel_mid_irq_type,
|
2013-11-20 14:24:32 +00:00
|
|
|
.irq_startup = intel_mid_irq_startup,
|
|
|
|
.irq_shutdown = intel_mid_irq_shutdown,
|
2009-09-22 23:46:36 +00:00
|
|
|
};
|
|
|
|
|
2013-10-04 20:01:42 +00:00
|
|
|
static const struct intel_mid_gpio_ddata gpio_lincroft = {
|
2013-10-04 20:01:40 +00:00
|
|
|
.ngpio = 64,
|
|
|
|
};
|
|
|
|
|
2013-10-04 20:01:42 +00:00
|
|
|
static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
|
2013-10-04 20:01:40 +00:00
|
|
|
.ngpio = 96,
|
2013-10-04 20:01:42 +00:00
|
|
|
.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
|
2013-10-04 20:01:40 +00:00
|
|
|
};
|
|
|
|
|
2013-10-04 20:01:42 +00:00
|
|
|
static const struct intel_mid_gpio_ddata gpio_penwell_core = {
|
2013-10-04 20:01:40 +00:00
|
|
|
.ngpio = 96,
|
2013-10-04 20:01:42 +00:00
|
|
|
.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
|
2013-10-04 20:01:40 +00:00
|
|
|
};
|
|
|
|
|
2013-10-04 20:01:42 +00:00
|
|
|
static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
|
2013-10-04 20:01:40 +00:00
|
|
|
.ngpio = 96,
|
2013-10-04 20:01:42 +00:00
|
|
|
.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL,
|
2013-10-04 20:01:40 +00:00
|
|
|
};
|
|
|
|
|
2013-10-04 20:01:42 +00:00
|
|
|
static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
|
2013-10-04 20:01:40 +00:00
|
|
|
.ngpio = 96,
|
2013-10-04 20:01:42 +00:00
|
|
|
.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
|
2013-10-04 20:01:40 +00:00
|
|
|
};
|
|
|
|
|
2013-10-04 20:01:42 +00:00
|
|
|
static const struct intel_mid_gpio_ddata gpio_tangier = {
|
2013-10-04 20:01:40 +00:00
|
|
|
.ngpio = 192,
|
|
|
|
.gplr_offset = 4,
|
|
|
|
.flis_base = 0xff0c0000,
|
|
|
|
.flis_len = 0x8000,
|
|
|
|
.get_flis_offset = NULL,
|
2013-10-04 20:01:42 +00:00
|
|
|
.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
|
2013-10-04 20:01:40 +00:00
|
|
|
};
|
|
|
|
|
2013-12-02 23:08:45 +00:00
|
|
|
static const struct pci_device_id intel_gpio_ids[] = {
|
2013-10-04 20:01:40 +00:00
|
|
|
{
|
|
|
|
/* Lincroft */
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
|
|
|
|
.driver_data = (kernel_ulong_t)&gpio_lincroft,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
/* Penwell AON */
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
|
|
|
|
.driver_data = (kernel_ulong_t)&gpio_penwell_aon,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
/* Penwell Core */
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
|
|
|
|
.driver_data = (kernel_ulong_t)&gpio_penwell_core,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
/* Cloverview Aon */
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
|
|
|
|
.driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
/* Cloverview Core */
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
|
|
|
|
.driver_data = (kernel_ulong_t)&gpio_cloverview_core,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
/* Tangier */
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1199),
|
|
|
|
.driver_data = (kernel_ulong_t)&gpio_tangier,
|
|
|
|
},
|
|
|
|
{ 0 }
|
2009-09-22 23:46:36 +00:00
|
|
|
};
|
2013-10-04 20:01:42 +00:00
|
|
|
MODULE_DEVICE_TABLE(pci, intel_gpio_ids);
|
2009-09-22 23:46:36 +00:00
|
|
|
|
2013-10-04 20:01:42 +00:00
|
|
|
static void intel_mid_irq_handler(unsigned irq, struct irq_desc *desc)
|
2009-09-22 23:46:36 +00:00
|
|
|
{
|
2011-03-17 19:32:49 +00:00
|
|
|
struct irq_data *data = irq_desc_get_irq_data(desc);
|
2013-10-04 20:01:42 +00:00
|
|
|
struct intel_mid_gpio *priv = irq_data_get_irq_handler_data(data);
|
2011-03-17 19:32:49 +00:00
|
|
|
struct irq_chip *chip = irq_data_get_irq_chip(data);
|
2011-03-17 19:32:58 +00:00
|
|
|
u32 base, gpio, mask;
|
2011-03-17 19:32:55 +00:00
|
|
|
unsigned long pending;
|
2009-09-22 23:46:36 +00:00
|
|
|
void __iomem *gedr;
|
|
|
|
|
|
|
|
/* check GPIO controller to check which pin triggered the interrupt */
|
2013-10-04 20:01:42 +00:00
|
|
|
for (base = 0; base < priv->chip.ngpio; base += 32) {
|
|
|
|
gedr = gpio_reg(&priv->chip, base, GEDR);
|
2012-05-10 10:01:22 +00:00
|
|
|
while ((pending = readl(gedr))) {
|
2011-07-08 09:02:18 +00:00
|
|
|
gpio = __ffs(pending);
|
2011-03-17 19:32:58 +00:00
|
|
|
mask = BIT(gpio);
|
|
|
|
/* Clear before handling so we can't lose an edge */
|
|
|
|
writel(mask, gedr);
|
2013-10-04 20:01:42 +00:00
|
|
|
generic_handle_irq(irq_find_mapping(priv->domain,
|
2012-05-02 08:15:50 +00:00
|
|
|
base + gpio));
|
2011-03-17 19:32:55 +00:00
|
|
|
}
|
2009-09-22 23:46:36 +00:00
|
|
|
}
|
2011-01-25 23:07:15 +00:00
|
|
|
|
2011-03-17 19:32:49 +00:00
|
|
|
chip->irq_eoi(data);
|
2009-09-22 23:46:36 +00:00
|
|
|
}
|
|
|
|
|
2013-10-04 20:01:42 +00:00
|
|
|
static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
|
2012-04-05 09:15:17 +00:00
|
|
|
{
|
|
|
|
void __iomem *reg;
|
|
|
|
unsigned base;
|
|
|
|
|
2013-10-04 20:01:42 +00:00
|
|
|
for (base = 0; base < priv->chip.ngpio; base += 32) {
|
2012-04-05 09:15:17 +00:00
|
|
|
/* Clear the rising-edge detect register */
|
2013-10-04 20:01:42 +00:00
|
|
|
reg = gpio_reg(&priv->chip, base, GRER);
|
2012-04-05 09:15:17 +00:00
|
|
|
writel(0, reg);
|
|
|
|
/* Clear the falling-edge detect register */
|
2013-10-04 20:01:42 +00:00
|
|
|
reg = gpio_reg(&priv->chip, base, GFER);
|
2012-04-05 09:15:17 +00:00
|
|
|
writel(0, reg);
|
|
|
|
/* Clear the edge detect status register */
|
2013-10-04 20:01:42 +00:00
|
|
|
reg = gpio_reg(&priv->chip, base, GEDR);
|
2012-04-05 09:15:17 +00:00
|
|
|
writel(~0, reg);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-10-11 17:27:02 +00:00
|
|
|
static int intel_gpio_irq_map(struct irq_domain *d, unsigned int irq,
|
|
|
|
irq_hw_number_t hwirq)
|
2012-05-02 08:15:50 +00:00
|
|
|
{
|
2013-10-04 20:01:42 +00:00
|
|
|
struct intel_mid_gpio *priv = d->host_data;
|
2012-05-02 08:15:50 +00:00
|
|
|
|
2013-11-26 13:28:32 +00:00
|
|
|
irq_set_chip_and_handler(irq, &intel_mid_irqchip, handle_simple_irq);
|
2013-10-11 17:27:02 +00:00
|
|
|
irq_set_chip_data(irq, priv);
|
|
|
|
irq_set_irq_type(irq, IRQ_TYPE_NONE);
|
2012-05-02 08:15:50 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-10-04 20:01:42 +00:00
|
|
|
static const struct irq_domain_ops intel_gpio_irq_ops = {
|
|
|
|
.map = intel_gpio_irq_map,
|
2012-05-02 08:15:50 +00:00
|
|
|
.xlate = irq_domain_xlate_twocell,
|
|
|
|
};
|
|
|
|
|
2013-10-04 20:01:42 +00:00
|
|
|
static int intel_gpio_runtime_idle(struct device *dev)
|
2011-05-10 13:23:45 +00:00
|
|
|
{
|
2014-01-31 21:08:01 +00:00
|
|
|
int err = pm_schedule_suspend(dev, 500);
|
|
|
|
return err ?: -EBUSY;
|
2011-05-10 13:23:45 +00:00
|
|
|
}
|
|
|
|
|
2013-10-04 20:01:42 +00:00
|
|
|
static const struct dev_pm_ops intel_gpio_pm_ops = {
|
|
|
|
SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
|
2011-05-10 13:23:45 +00:00
|
|
|
};
|
|
|
|
|
2013-10-04 20:01:42 +00:00
|
|
|
static int intel_gpio_probe(struct pci_dev *pdev,
|
2013-05-22 10:20:11 +00:00
|
|
|
const struct pci_device_id *id)
|
2009-09-22 23:46:36 +00:00
|
|
|
{
|
2013-05-22 10:20:11 +00:00
|
|
|
void __iomem *base;
|
2013-10-04 20:01:42 +00:00
|
|
|
struct intel_mid_gpio *priv;
|
2009-09-22 23:46:36 +00:00
|
|
|
u32 gpio_base;
|
2013-05-06 23:11:03 +00:00
|
|
|
u32 irq_base;
|
2012-08-05 09:52:34 +00:00
|
|
|
int retval;
|
2013-10-04 20:01:42 +00:00
|
|
|
struct intel_mid_gpio_ddata *ddata =
|
|
|
|
(struct intel_mid_gpio_ddata *)id->driver_data;
|
2009-09-22 23:46:36 +00:00
|
|
|
|
2013-05-22 10:20:12 +00:00
|
|
|
retval = pcim_enable_device(pdev);
|
2009-09-22 23:46:36 +00:00
|
|
|
if (retval)
|
2012-04-05 09:15:15 +00:00
|
|
|
return retval;
|
2009-09-22 23:46:36 +00:00
|
|
|
|
2013-05-22 10:20:12 +00:00
|
|
|
retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
|
2009-09-22 23:46:36 +00:00
|
|
|
if (retval) {
|
2013-05-22 10:20:12 +00:00
|
|
|
dev_err(&pdev->dev, "I/O memory mapping error\n");
|
|
|
|
return retval;
|
2009-09-22 23:46:36 +00:00
|
|
|
}
|
2013-05-22 10:20:11 +00:00
|
|
|
|
2013-05-22 10:20:12 +00:00
|
|
|
base = pcim_iomap_table(pdev)[1];
|
|
|
|
|
2013-05-22 10:20:11 +00:00
|
|
|
irq_base = readl(base);
|
|
|
|
gpio_base = readl(sizeof(u32) + base);
|
|
|
|
|
2009-09-22 23:46:36 +00:00
|
|
|
/* release the IO mapping, since we already get the info from bar1 */
|
2013-05-22 10:20:12 +00:00
|
|
|
pcim_iounmap_regions(pdev, 1 << 1);
|
2009-09-22 23:46:36 +00:00
|
|
|
|
2013-10-04 20:01:42 +00:00
|
|
|
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
|
|
|
|
if (!priv) {
|
2013-05-22 10:20:13 +00:00
|
|
|
dev_err(&pdev->dev, "can't allocate chip data\n");
|
2013-05-22 10:20:12 +00:00
|
|
|
return -ENOMEM;
|
2009-09-22 23:46:36 +00:00
|
|
|
}
|
2012-04-05 09:15:16 +00:00
|
|
|
|
2013-10-04 20:01:42 +00:00
|
|
|
priv->reg_base = pcim_iomap_table(pdev)[0];
|
|
|
|
priv->chip.label = dev_name(&pdev->dev);
|
2013-11-20 14:24:32 +00:00
|
|
|
priv->chip.dev = &pdev->dev;
|
2013-10-04 20:01:42 +00:00
|
|
|
priv->chip.request = intel_gpio_request;
|
|
|
|
priv->chip.direction_input = intel_gpio_direction_input;
|
|
|
|
priv->chip.direction_output = intel_gpio_direction_output;
|
|
|
|
priv->chip.get = intel_gpio_get;
|
|
|
|
priv->chip.set = intel_gpio_set;
|
|
|
|
priv->chip.to_irq = intel_gpio_to_irq;
|
|
|
|
priv->chip.base = gpio_base;
|
|
|
|
priv->chip.ngpio = ddata->ngpio;
|
2013-12-04 13:42:46 +00:00
|
|
|
priv->chip.can_sleep = false;
|
2013-10-04 20:01:42 +00:00
|
|
|
priv->pdev = pdev;
|
|
|
|
|
|
|
|
spin_lock_init(&priv->lock);
|
|
|
|
|
|
|
|
priv->domain = irq_domain_add_simple(pdev->dev.of_node, ddata->ngpio,
|
|
|
|
irq_base, &intel_gpio_irq_ops, priv);
|
|
|
|
if (!priv->domain)
|
2013-05-22 10:20:12 +00:00
|
|
|
return -ENOMEM;
|
2013-05-06 23:11:03 +00:00
|
|
|
|
2013-10-04 20:01:42 +00:00
|
|
|
pci_set_drvdata(pdev, priv);
|
|
|
|
retval = gpiochip_add(&priv->chip);
|
2009-09-22 23:46:36 +00:00
|
|
|
if (retval) {
|
2013-05-22 10:20:13 +00:00
|
|
|
dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
|
2013-05-22 10:20:12 +00:00
|
|
|
return retval;
|
2009-09-22 23:46:36 +00:00
|
|
|
}
|
2012-04-05 09:15:17 +00:00
|
|
|
|
2013-10-04 20:01:42 +00:00
|
|
|
intel_mid_irq_init_hw(priv);
|
2012-04-05 09:15:17 +00:00
|
|
|
|
2013-10-04 20:01:42 +00:00
|
|
|
irq_set_handler_data(pdev->irq, priv);
|
|
|
|
irq_set_chained_handler(pdev->irq, intel_mid_irq_handler);
|
2009-09-22 23:46:36 +00:00
|
|
|
|
2011-05-10 13:23:45 +00:00
|
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
|
|
pm_runtime_allow(&pdev->dev);
|
|
|
|
|
2012-04-05 09:15:15 +00:00
|
|
|
return 0;
|
2009-09-22 23:46:36 +00:00
|
|
|
}
|
|
|
|
|
2013-10-04 20:01:42 +00:00
|
|
|
static struct pci_driver intel_gpio_driver = {
|
|
|
|
.name = "intel_mid_gpio",
|
|
|
|
.id_table = intel_gpio_ids,
|
|
|
|
.probe = intel_gpio_probe,
|
2011-05-10 13:23:45 +00:00
|
|
|
.driver = {
|
2013-10-04 20:01:42 +00:00
|
|
|
.pm = &intel_gpio_pm_ops,
|
2011-05-10 13:23:45 +00:00
|
|
|
},
|
2009-09-22 23:46:36 +00:00
|
|
|
};
|
|
|
|
|
2013-10-04 20:01:42 +00:00
|
|
|
static int __init intel_gpio_init(void)
|
2009-09-22 23:46:36 +00:00
|
|
|
{
|
2013-10-04 20:01:42 +00:00
|
|
|
return pci_register_driver(&intel_gpio_driver);
|
2009-09-22 23:46:36 +00:00
|
|
|
}
|
|
|
|
|
2013-10-04 20:01:42 +00:00
|
|
|
device_initcall(intel_gpio_init);
|