um: add PCI over virtio emulation driver
To support testing of PCI/PCIe drivers in UML, add a PCI bus
support driver. This driver uses virtio, which in UML is really
just vhost-user, to talk to devices, and adds the devices to
the virtual PCI bus in the system.
Since virtio already allows DMA/bus mastering this really isn't
all that hard, of course we need the logic_iomem infrastructure
that was added by a previous patch.
The protocol to talk to the device is has a few fairly simple
messages for reading to/writing from config and IO spaces, and
messages for the device to send the various interrupts (INT#,
MSI/MSI-X and while suspended PME#).
Note that currently no offical virtio device ID is assigned for
this protocol, as a consequence this patch requires defining it
in the Kconfig, with a default that makes the driver refuse to
work at all.
Finally, in order to add support for MSI/MSI-X interrupts, some
small changes are needed in the UML IRQ code, it needs to have
more interrupts, changing NR_IRQS from 64 to 128 if this driver
is enabled, but not actually use them for anything so that the
generic IRQ domain/MSI infrastructure can allocate IRQ numbers.
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Richard Weinberger <richard@nod.at>
2021-03-05 12:19:58 +00:00
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/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
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/*
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* Copyright (C) 2021 Intel Corporation
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* Author: Johannes Berg <johannes@sipsolutions.net>
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*/
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#ifndef _UAPI_LINUX_VIRTIO_PCIDEV_H
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#define _UAPI_LINUX_VIRTIO_PCIDEV_H
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#include <linux/types.h>
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/**
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* enum virtio_pcidev_ops - virtual PCI device operations
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2021-08-17 15:53:29 +00:00
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* @VIRTIO_PCIDEV_OP_RESERVED: reserved to catch errors
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um: add PCI over virtio emulation driver
To support testing of PCI/PCIe drivers in UML, add a PCI bus
support driver. This driver uses virtio, which in UML is really
just vhost-user, to talk to devices, and adds the devices to
the virtual PCI bus in the system.
Since virtio already allows DMA/bus mastering this really isn't
all that hard, of course we need the logic_iomem infrastructure
that was added by a previous patch.
The protocol to talk to the device is has a few fairly simple
messages for reading to/writing from config and IO spaces, and
messages for the device to send the various interrupts (INT#,
MSI/MSI-X and while suspended PME#).
Note that currently no offical virtio device ID is assigned for
this protocol, as a consequence this patch requires defining it
in the Kconfig, with a default that makes the driver refuse to
work at all.
Finally, in order to add support for MSI/MSI-X interrupts, some
small changes are needed in the UML IRQ code, it needs to have
more interrupts, changing NR_IRQS from 64 to 128 if this driver
is enabled, but not actually use them for anything so that the
generic IRQ domain/MSI infrastructure can allocate IRQ numbers.
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Richard Weinberger <richard@nod.at>
2021-03-05 12:19:58 +00:00
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* @VIRTIO_PCIDEV_OP_CFG_READ: read config space, size is 1, 2, 4 or 8;
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* the @data field should be filled in by the device (in little endian).
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* @VIRTIO_PCIDEV_OP_CFG_WRITE: write config space, size is 1, 2, 4 or 8;
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* the @data field contains the data to write (in little endian).
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2021-08-17 15:53:29 +00:00
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* @VIRTIO_PCIDEV_OP_MMIO_READ: read BAR mem/pio, size can be variable;
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um: add PCI over virtio emulation driver
To support testing of PCI/PCIe drivers in UML, add a PCI bus
support driver. This driver uses virtio, which in UML is really
just vhost-user, to talk to devices, and adds the devices to
the virtual PCI bus in the system.
Since virtio already allows DMA/bus mastering this really isn't
all that hard, of course we need the logic_iomem infrastructure
that was added by a previous patch.
The protocol to talk to the device is has a few fairly simple
messages for reading to/writing from config and IO spaces, and
messages for the device to send the various interrupts (INT#,
MSI/MSI-X and while suspended PME#).
Note that currently no offical virtio device ID is assigned for
this protocol, as a consequence this patch requires defining it
in the Kconfig, with a default that makes the driver refuse to
work at all.
Finally, in order to add support for MSI/MSI-X interrupts, some
small changes are needed in the UML IRQ code, it needs to have
more interrupts, changing NR_IRQS from 64 to 128 if this driver
is enabled, but not actually use them for anything so that the
generic IRQ domain/MSI infrastructure can allocate IRQ numbers.
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Richard Weinberger <richard@nod.at>
2021-03-05 12:19:58 +00:00
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* the @data field should be filled in by the device (in little endian).
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2021-08-17 15:53:29 +00:00
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* @VIRTIO_PCIDEV_OP_MMIO_WRITE: write BAR mem/pio, size can be variable;
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um: add PCI over virtio emulation driver
To support testing of PCI/PCIe drivers in UML, add a PCI bus
support driver. This driver uses virtio, which in UML is really
just vhost-user, to talk to devices, and adds the devices to
the virtual PCI bus in the system.
Since virtio already allows DMA/bus mastering this really isn't
all that hard, of course we need the logic_iomem infrastructure
that was added by a previous patch.
The protocol to talk to the device is has a few fairly simple
messages for reading to/writing from config and IO spaces, and
messages for the device to send the various interrupts (INT#,
MSI/MSI-X and while suspended PME#).
Note that currently no offical virtio device ID is assigned for
this protocol, as a consequence this patch requires defining it
in the Kconfig, with a default that makes the driver refuse to
work at all.
Finally, in order to add support for MSI/MSI-X interrupts, some
small changes are needed in the UML IRQ code, it needs to have
more interrupts, changing NR_IRQS from 64 to 128 if this driver
is enabled, but not actually use them for anything so that the
generic IRQ domain/MSI infrastructure can allocate IRQ numbers.
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Richard Weinberger <richard@nod.at>
2021-03-05 12:19:58 +00:00
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* the @data field contains the data to write (in little endian).
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* @VIRTIO_PCIDEV_OP_MMIO_MEMSET: memset MMIO, size is variable but
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* the @data field only has one byte (unlike @VIRTIO_PCIDEV_OP_MMIO_WRITE)
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* @VIRTIO_PCIDEV_OP_INT: legacy INTx# pin interrupt, the addr field is 1-4 for
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* the number
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* @VIRTIO_PCIDEV_OP_MSI: MSI(-X) interrupt, this message basically transports
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* the 16- or 32-bit write that would otherwise be done into memory,
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* analogous to the write messages (@VIRTIO_PCIDEV_OP_MMIO_WRITE) above
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* @VIRTIO_PCIDEV_OP_PME: Dummy message whose content is ignored (and should be
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* all zeroes) to signal the PME# pin.
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*/
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enum virtio_pcidev_ops {
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VIRTIO_PCIDEV_OP_RESERVED = 0,
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VIRTIO_PCIDEV_OP_CFG_READ,
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VIRTIO_PCIDEV_OP_CFG_WRITE,
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VIRTIO_PCIDEV_OP_MMIO_READ,
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VIRTIO_PCIDEV_OP_MMIO_WRITE,
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VIRTIO_PCIDEV_OP_MMIO_MEMSET,
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VIRTIO_PCIDEV_OP_INT,
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VIRTIO_PCIDEV_OP_MSI,
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VIRTIO_PCIDEV_OP_PME,
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};
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/**
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* struct virtio_pcidev_msg - virtio PCI device operation
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* @op: the operation to do
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* @bar: the bar (only with BAR read/write messages)
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* @reserved: reserved
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* @size: the size of the read/write (in bytes)
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* @addr: the address to read/write
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* @data: the data, normally @size long, but just one byte for
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* %VIRTIO_PCIDEV_OP_MMIO_MEMSET
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*
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* Note: the fields are all in native (CPU) endian, however, the
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* @data values will often be in little endian (see the ops above.)
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*/
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struct virtio_pcidev_msg {
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__u8 op;
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__u8 bar;
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__u16 reserved;
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__u32 size;
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__u64 addr;
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__u8 data[];
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};
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#endif /* _UAPI_LINUX_VIRTIO_PCIDEV_H */
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