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linux-stable/drivers/soc/mediatek/mtk-pmic-wrap.c

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 655 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-27 06:55:21 +00:00
// SPDX-License-Identifier: GPL-2.0-only
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Flora Fu, MediaTek
*/
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#define PWRAP_MT8135_BRIDGE_IORD_ARB_EN 0x4
#define PWRAP_MT8135_BRIDGE_WACS3_EN 0x10
#define PWRAP_MT8135_BRIDGE_INIT_DONE3 0x14
#define PWRAP_MT8135_BRIDGE_WACS4_EN 0x24
#define PWRAP_MT8135_BRIDGE_INIT_DONE4 0x28
#define PWRAP_MT8135_BRIDGE_INT_EN 0x38
#define PWRAP_MT8135_BRIDGE_TIMER_EN 0x48
#define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x50
#define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54
/* macro for wrapper status */
#define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff)
soc: mediatek: pwrap: add arbiter capability Add arbiter capability for pwrap driver. The arbiter capability uses new design to judge the priority and latency for multi-channel. The design with arbiter support cannot change the watchdog timer. This patch is preparing for adding mt6873/8192 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-3-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:43 +00:00
#define PWRAP_GET_WACS_ARB_FSM(x) (((x) >> 1) & 0x00000007)
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
#define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007)
#define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001)
soc: mediatek: pwrap: use BIT() macro Use a better BIT() marco for the bit definition. No functional changes, cleanup only. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Link: https://lore.kernel.org/r/1615563286-22126-2-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:42 +00:00
#define PWRAP_STATE_SYNC_IDLE0 BIT(20)
#define PWRAP_STATE_INIT_DONE0 BIT(21)
soc: mediatek: pwrap: add pwrap driver for MT8186 SoC MT8186 are highly integrated SoC and use PMIC_MT6366 for power management. This patch adds pwrap master driver to access PMIC_MT6366. Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Link: https://lore.kernel.org/r/20220207083034.15327-2-johnson.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-07 08:30:33 +00:00
#define PWRAP_STATE_INIT_DONE0_MT8186 BIT(22)
soc: mediatek: pwrap: add arbiter capability Add arbiter capability for pwrap driver. The arbiter capability uses new design to judge the priority and latency for multi-channel. The design with arbiter support cannot change the watchdog timer. This patch is preparing for adding mt6873/8192 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-3-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:43 +00:00
#define PWRAP_STATE_INIT_DONE1 BIT(15)
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
/* macro for WACS FSM */
#define PWRAP_WACS_FSM_IDLE 0x00
#define PWRAP_WACS_FSM_REQ 0x02
#define PWRAP_WACS_FSM_WFDLE 0x04
#define PWRAP_WACS_FSM_WFVLDCLR 0x06
#define PWRAP_WACS_INIT_DONE 0x01
#define PWRAP_WACS_WACS_SYNC_IDLE 0x01
#define PWRAP_WACS_SYNC_BUSY 0x00
/* macro for device wrapper default value */
#define PWRAP_DEW_READ_TEST_VAL 0x5aa5
#define PWRAP_DEW_WRITE_TEST_VAL 0xa55a
/* macro for manual command */
soc: mediatek: PMIC wrap: add MT2701/7623 support Add the registers, callbacks and data structures required to make the wrapper work on MT2701 and MT7623. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:15 +00:00
#define PWRAP_MAN_CMD_SPI_WRITE_NEW (1 << 14)
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
#define PWRAP_MAN_CMD_SPI_WRITE (1 << 13)
#define PWRAP_MAN_CMD_OP_CSH (0x0 << 8)
#define PWRAP_MAN_CMD_OP_CSL (0x1 << 8)
#define PWRAP_MAN_CMD_OP_CK (0x2 << 8)
#define PWRAP_MAN_CMD_OP_OUTS (0x8 << 8)
#define PWRAP_MAN_CMD_OP_OUTD (0x9 << 8)
#define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8)
soc: mediatek: PMIC wrap: clear the STAUPD_TRIG bit of WDT_SRC_EN Since STAUPD interrupts aren't handled on mt8173, disable watchdog timeout monitor of STAUPD to avoid WDT_INT triggered by STAUPD. Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-01-21 11:04:00 +00:00
/* macro for Watch Dog Timer Source */
#define PWRAP_WDT_SRC_EN_STAUPD_TRIG (1 << 25)
#define PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE (1 << 20)
#define PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE (1 << 6)
#define PWRAP_WDT_SRC_MASK_ALL 0xffffffff
#define PWRAP_WDT_SRC_MASK_NO_STAUPD ~(PWRAP_WDT_SRC_EN_STAUPD_TRIG | \
PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \
PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)
soc: mediatek: pwrap: refactor pwrap_init for the various PMIC types pwrap initialization is highly associated with the base SoC and the target PMICs, so slight refactorization is made here for allowing pwrap_init to run on those PMICs with different capability from the previous MediaTek PMICs and the determination for the enablement of the pwrap capability depending on PMIC type. Apart from this, the patch makes the driver more extensible especially when more PMICs join into the pwrap driver. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:45 +00:00
/* Group of bits used for shown slave capability */
#define PWRAP_SLV_CAP_SPI BIT(0)
#define PWRAP_SLV_CAP_DUALIO BIT(1)
#define PWRAP_SLV_CAP_SECURITY BIT(2)
#define HAS_CAP(_c, _x) (((_c) & (_x)) == (_x))
soc: mediatek: pwrap: use group of bits for pwrap capability Use group of bits for pwrap capability instead of elements of structure. This patch is preparing for adding mt8183 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-25 13:48:39 +00:00
/* Group of bits used for shown pwrap capability */
#define PWRAP_CAP_BRIDGE BIT(0)
#define PWRAP_CAP_RESET BIT(1)
#define PWRAP_CAP_DCM BIT(2)
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
#define PWRAP_CAP_INT1_EN BIT(3)
#define PWRAP_CAP_WDT_SRC1 BIT(4)
soc: mediatek: pwrap: add arbiter capability Add arbiter capability for pwrap driver. The arbiter capability uses new design to judge the priority and latency for multi-channel. The design with arbiter support cannot change the watchdog timer. This patch is preparing for adding mt6873/8192 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-3-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:43 +00:00
#define PWRAP_CAP_ARB BIT(5)
soc: mediatek: pwrap: add pwrap driver for MT8186 SoC MT8186 are highly integrated SoC and use PMIC_MT6366 for power management. This patch adds pwrap master driver to access PMIC_MT6366. Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Link: https://lore.kernel.org/r/20220207083034.15327-2-johnson.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-07 08:30:33 +00:00
#define PWRAP_CAP_ARB_MT8186 BIT(8)
soc: mediatek: pwrap: use group of bits for pwrap capability Use group of bits for pwrap capability instead of elements of structure. This patch is preparing for adding mt8183 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-25 13:48:39 +00:00
soc: mediatek: PMIC wrap: add a slave specific struct This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:13 +00:00
/* defines for slave device wrapper registers */
enum dew_regs {
PWRAP_DEW_BASE,
PWRAP_DEW_DIO_EN,
PWRAP_DEW_READ_TEST,
PWRAP_DEW_WRITE_TEST,
PWRAP_DEW_CRC_EN,
PWRAP_DEW_CRC_VAL,
PWRAP_DEW_MON_GRP_SEL,
PWRAP_DEW_CIPHER_KEY_SEL,
PWRAP_DEW_CIPHER_IV_SEL,
PWRAP_DEW_CIPHER_RDY,
PWRAP_DEW_CIPHER_MODE,
PWRAP_DEW_CIPHER_SWRST,
soc: mediatek: pwrap: order SoCs and PMICs ascending Order SoC and PMIC numbers ascending to make the code more readable. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-25 13:46:59 +00:00
/* MT6323 only regs */
PWRAP_DEW_CIPHER_EN,
PWRAP_DEW_RDDMY_NO,
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
/* MT6358 only regs */
PWRAP_SMT_CON1,
PWRAP_DRV_CON1,
PWRAP_FILTER_CON0,
PWRAP_GPIO_PULLEN0_CLR,
PWRAP_RG_SPI_CON0,
PWRAP_RG_SPI_RECORD0,
PWRAP_RG_SPI_CON2,
PWRAP_RG_SPI_CON3,
PWRAP_RG_SPI_CON4,
PWRAP_RG_SPI_CON5,
PWRAP_RG_SPI_CON6,
PWRAP_RG_SPI_CON7,
PWRAP_RG_SPI_CON8,
PWRAP_RG_SPI_CON13,
PWRAP_SPISLV_KEY,
soc: mediatek: pwrap: add support for MT6359 PMIC MT6359 is a new power management IC and it is used for MT6779 SoCs. To define mt6359_regs for pmic register mapping and pmic_mt6359 for accessing register. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-02-16 06:17:23 +00:00
/* MT6359 only regs */
PWRAP_DEW_CRC_SWRST,
PWRAP_DEW_RG_EN_RECORD,
PWRAP_DEW_RECORD_CMD0,
PWRAP_DEW_RECORD_CMD1,
PWRAP_DEW_RECORD_CMD2,
PWRAP_DEW_RECORD_CMD3,
PWRAP_DEW_RECORD_CMD4,
PWRAP_DEW_RECORD_CMD5,
PWRAP_DEW_RECORD_WDATA0,
PWRAP_DEW_RECORD_WDATA1,
PWRAP_DEW_RECORD_WDATA2,
PWRAP_DEW_RECORD_WDATA3,
PWRAP_DEW_RECORD_WDATA4,
PWRAP_DEW_RECORD_WDATA5,
PWRAP_DEW_RG_ADDR_TARGET,
PWRAP_DEW_RG_ADDR_MASK,
PWRAP_DEW_RG_WDATA_TARGET,
PWRAP_DEW_RG_WDATA_MASK,
PWRAP_DEW_RG_SPI_RECORD_CLR,
PWRAP_DEW_RG_CMD_ALERT_CLR,
soc: mediatek: PMIC wrap: add a slave specific struct This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:13 +00:00
/* MT6397 only regs */
PWRAP_DEW_EVENT_OUT_EN,
PWRAP_DEW_EVENT_SRC_EN,
PWRAP_DEW_EVENT_SRC,
PWRAP_DEW_EVENT_FLAG,
PWRAP_DEW_MON_FLAG_SEL,
PWRAP_DEW_EVENT_TEST,
PWRAP_DEW_CIPHER_LOAD,
PWRAP_DEW_CIPHER_START,
soc: mediatek: PMIC wrap: add mt6323 slave support Add support for MT6323 slaves. This PMIC can be found on MT2701 and MT7623 EVB. The only function that we need to touch is pwrap_init_cipher(). Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:14 +00:00
};
static const u32 mt6323_regs[] = {
[PWRAP_DEW_BASE] = 0x0000,
[PWRAP_DEW_DIO_EN] = 0x018a,
[PWRAP_DEW_READ_TEST] = 0x018c,
[PWRAP_DEW_WRITE_TEST] = 0x018e,
[PWRAP_DEW_CRC_EN] = 0x0192,
[PWRAP_DEW_CRC_VAL] = 0x0194,
[PWRAP_DEW_MON_GRP_SEL] = 0x0196,
[PWRAP_DEW_CIPHER_KEY_SEL] = 0x0198,
[PWRAP_DEW_CIPHER_IV_SEL] = 0x019a,
[PWRAP_DEW_CIPHER_EN] = 0x019c,
[PWRAP_DEW_CIPHER_RDY] = 0x019e,
[PWRAP_DEW_CIPHER_MODE] = 0x01a0,
[PWRAP_DEW_CIPHER_SWRST] = 0x01a2,
[PWRAP_DEW_RDDMY_NO] = 0x01a4,
soc: mediatek: PMIC wrap: add a slave specific struct This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:13 +00:00
};
soc: mediatek: pwrap: order SoCs and PMICs ascending Order SoC and PMIC numbers ascending to make the code more readable. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-25 13:46:59 +00:00
static const u32 mt6351_regs[] = {
[PWRAP_DEW_DIO_EN] = 0x02F2,
[PWRAP_DEW_READ_TEST] = 0x02F4,
[PWRAP_DEW_WRITE_TEST] = 0x02F6,
[PWRAP_DEW_CRC_EN] = 0x02FA,
[PWRAP_DEW_CRC_VAL] = 0x02FC,
[PWRAP_DEW_CIPHER_KEY_SEL] = 0x0300,
[PWRAP_DEW_CIPHER_IV_SEL] = 0x0302,
[PWRAP_DEW_CIPHER_EN] = 0x0304,
[PWRAP_DEW_CIPHER_RDY] = 0x0306,
[PWRAP_DEW_CIPHER_MODE] = 0x0308,
[PWRAP_DEW_CIPHER_SWRST] = 0x030A,
[PWRAP_DEW_RDDMY_NO] = 0x030C,
};
soc: mediatek: pwrap: add mt6357 driver for mt6765 SoCs MT6357 is a new power management IC and it is used for mt6765 SoCs. To define mt6357_regs for pmic register mapping and pmic_mt6357 for accessing register. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-04 12:31:54 +00:00
static const u32 mt6357_regs[] = {
[PWRAP_DEW_DIO_EN] = 0x040A,
[PWRAP_DEW_READ_TEST] = 0x040C,
[PWRAP_DEW_WRITE_TEST] = 0x040E,
[PWRAP_DEW_CRC_EN] = 0x0412,
[PWRAP_DEW_CRC_VAL] = 0x0414,
[PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418,
[PWRAP_DEW_CIPHER_IV_SEL] = 0x041A,
[PWRAP_DEW_CIPHER_EN] = 0x041C,
[PWRAP_DEW_CIPHER_RDY] = 0x041E,
[PWRAP_DEW_CIPHER_MODE] = 0x0420,
[PWRAP_DEW_CIPHER_SWRST] = 0x0422,
[PWRAP_DEW_RDDMY_NO] = 0x0424,
};
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
static const u32 mt6358_regs[] = {
[PWRAP_SMT_CON1] = 0x0030,
[PWRAP_DRV_CON1] = 0x0038,
[PWRAP_FILTER_CON0] = 0x0040,
[PWRAP_GPIO_PULLEN0_CLR] = 0x0098,
[PWRAP_RG_SPI_CON0] = 0x0408,
[PWRAP_RG_SPI_RECORD0] = 0x040a,
[PWRAP_DEW_DIO_EN] = 0x040c,
[PWRAP_DEW_READ_TEST] = 0x040e,
[PWRAP_DEW_WRITE_TEST] = 0x0410,
[PWRAP_DEW_CRC_EN] = 0x0414,
[PWRAP_DEW_CIPHER_KEY_SEL] = 0x041a,
[PWRAP_DEW_CIPHER_IV_SEL] = 0x041c,
[PWRAP_DEW_CIPHER_EN] = 0x041e,
[PWRAP_DEW_CIPHER_RDY] = 0x0420,
[PWRAP_DEW_CIPHER_MODE] = 0x0422,
[PWRAP_DEW_CIPHER_SWRST] = 0x0424,
[PWRAP_RG_SPI_CON2] = 0x0432,
[PWRAP_RG_SPI_CON3] = 0x0434,
[PWRAP_RG_SPI_CON4] = 0x0436,
[PWRAP_RG_SPI_CON5] = 0x0438,
[PWRAP_RG_SPI_CON6] = 0x043a,
[PWRAP_RG_SPI_CON7] = 0x043c,
[PWRAP_RG_SPI_CON8] = 0x043e,
[PWRAP_RG_SPI_CON13] = 0x0448,
[PWRAP_SPISLV_KEY] = 0x044a,
};
soc: mediatek: pwrap: add support for MT6359 PMIC MT6359 is a new power management IC and it is used for MT6779 SoCs. To define mt6359_regs for pmic register mapping and pmic_mt6359 for accessing register. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-02-16 06:17:23 +00:00
static const u32 mt6359_regs[] = {
[PWRAP_DEW_RG_EN_RECORD] = 0x040a,
[PWRAP_DEW_DIO_EN] = 0x040c,
[PWRAP_DEW_READ_TEST] = 0x040e,
[PWRAP_DEW_WRITE_TEST] = 0x0410,
[PWRAP_DEW_CRC_SWRST] = 0x0412,
[PWRAP_DEW_CRC_EN] = 0x0414,
[PWRAP_DEW_CRC_VAL] = 0x0416,
[PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418,
[PWRAP_DEW_CIPHER_IV_SEL] = 0x041a,
[PWRAP_DEW_CIPHER_EN] = 0x041c,
[PWRAP_DEW_CIPHER_RDY] = 0x041e,
[PWRAP_DEW_CIPHER_MODE] = 0x0420,
[PWRAP_DEW_CIPHER_SWRST] = 0x0422,
[PWRAP_DEW_RDDMY_NO] = 0x0424,
[PWRAP_DEW_RECORD_CMD0] = 0x0428,
[PWRAP_DEW_RECORD_CMD1] = 0x042a,
[PWRAP_DEW_RECORD_CMD2] = 0x042c,
[PWRAP_DEW_RECORD_CMD3] = 0x042e,
[PWRAP_DEW_RECORD_CMD4] = 0x0430,
[PWRAP_DEW_RECORD_CMD5] = 0x0432,
[PWRAP_DEW_RECORD_WDATA0] = 0x0434,
[PWRAP_DEW_RECORD_WDATA1] = 0x0436,
[PWRAP_DEW_RECORD_WDATA2] = 0x0438,
[PWRAP_DEW_RECORD_WDATA3] = 0x043a,
[PWRAP_DEW_RECORD_WDATA4] = 0x043c,
[PWRAP_DEW_RECORD_WDATA5] = 0x043e,
[PWRAP_DEW_RG_ADDR_TARGET] = 0x0440,
[PWRAP_DEW_RG_ADDR_MASK] = 0x0442,
[PWRAP_DEW_RG_WDATA_TARGET] = 0x0444,
[PWRAP_DEW_RG_WDATA_MASK] = 0x0446,
[PWRAP_DEW_RG_SPI_RECORD_CLR] = 0x0448,
[PWRAP_DEW_RG_CMD_ALERT_CLR] = 0x0448,
[PWRAP_SPISLV_KEY] = 0x044a,
};
soc: mediatek: PMIC wrap: add a slave specific struct This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:13 +00:00
static const u32 mt6397_regs[] = {
[PWRAP_DEW_BASE] = 0xbc00,
[PWRAP_DEW_EVENT_OUT_EN] = 0xbc00,
[PWRAP_DEW_DIO_EN] = 0xbc02,
[PWRAP_DEW_EVENT_SRC_EN] = 0xbc04,
[PWRAP_DEW_EVENT_SRC] = 0xbc06,
[PWRAP_DEW_EVENT_FLAG] = 0xbc08,
[PWRAP_DEW_READ_TEST] = 0xbc0a,
[PWRAP_DEW_WRITE_TEST] = 0xbc0c,
[PWRAP_DEW_CRC_EN] = 0xbc0e,
[PWRAP_DEW_CRC_VAL] = 0xbc10,
[PWRAP_DEW_MON_GRP_SEL] = 0xbc12,
[PWRAP_DEW_MON_FLAG_SEL] = 0xbc14,
[PWRAP_DEW_EVENT_TEST] = 0xbc16,
[PWRAP_DEW_CIPHER_KEY_SEL] = 0xbc18,
[PWRAP_DEW_CIPHER_IV_SEL] = 0xbc1a,
[PWRAP_DEW_CIPHER_LOAD] = 0xbc1c,
[PWRAP_DEW_CIPHER_START] = 0xbc1e,
[PWRAP_DEW_CIPHER_RDY] = 0xbc20,
[PWRAP_DEW_CIPHER_MODE] = 0xbc22,
[PWRAP_DEW_CIPHER_SWRST] = 0xbc24,
};
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
enum pwrap_regs {
PWRAP_MUX_SEL,
PWRAP_WRAP_EN,
PWRAP_DIO_EN,
PWRAP_SIDLY,
PWRAP_CSHEXT_WRITE,
PWRAP_CSHEXT_READ,
PWRAP_CSLEXT_START,
PWRAP_CSLEXT_END,
PWRAP_STAUPD_PRD,
PWRAP_STAUPD_GRPEN,
PWRAP_STAUPD_MAN_TRIG,
PWRAP_STAUPD_STA,
PWRAP_WRAP_STA,
PWRAP_HARB_INIT,
PWRAP_HARB_HPRIO,
PWRAP_HIPRIO_ARB_EN,
PWRAP_HARB_STA0,
PWRAP_HARB_STA1,
PWRAP_MAN_EN,
PWRAP_MAN_CMD,
PWRAP_MAN_RDATA,
PWRAP_MAN_VLDCLR,
PWRAP_WACS0_EN,
PWRAP_INIT_DONE0,
PWRAP_WACS0_CMD,
PWRAP_WACS0_RDATA,
PWRAP_WACS0_VLDCLR,
PWRAP_WACS1_EN,
PWRAP_INIT_DONE1,
PWRAP_WACS1_CMD,
PWRAP_WACS1_RDATA,
PWRAP_WACS1_VLDCLR,
PWRAP_WACS2_EN,
PWRAP_INIT_DONE2,
PWRAP_WACS2_CMD,
PWRAP_WACS2_RDATA,
PWRAP_WACS2_VLDCLR,
PWRAP_INT_EN,
PWRAP_INT_FLG_RAW,
PWRAP_INT_FLG,
PWRAP_INT_CLR,
PWRAP_SIG_ADR,
PWRAP_SIG_MODE,
PWRAP_SIG_VALUE,
PWRAP_SIG_ERRVAL,
PWRAP_CRC_EN,
PWRAP_TIMER_EN,
PWRAP_TIMER_STA,
PWRAP_WDT_UNIT,
PWRAP_WDT_SRC_EN,
PWRAP_WDT_FLG,
PWRAP_DEBUG_INT_SEL,
PWRAP_CIPHER_KEY_SEL,
PWRAP_CIPHER_IV_SEL,
PWRAP_CIPHER_RDY,
PWRAP_CIPHER_MODE,
PWRAP_CIPHER_SWRST,
PWRAP_DCM_EN,
PWRAP_DCM_DBC_PRD,
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
PWRAP_EINT_STA0_ADR,
PWRAP_EINT_STA1_ADR,
soc: mediatek: pwrap: add arbiter capability Add arbiter capability for pwrap driver. The arbiter capability uses new design to judge the priority and latency for multi-channel. The design with arbiter support cannot change the watchdog timer. This patch is preparing for adding mt6873/8192 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-3-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:43 +00:00
PWRAP_SWINF_2_WDATA_31_0,
PWRAP_SWINF_2_RDATA_31_0,
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
soc: mediatek: PMIC wrap: add MT2701/7623 support Add the registers, callbacks and data structures required to make the wrapper work on MT2701 and MT7623. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:15 +00:00
/* MT2701 only regs */
PWRAP_ADC_CMD_ADDR,
PWRAP_PWRAP_ADC_CMD,
PWRAP_ADC_RDY_ADDR,
PWRAP_ADC_RDATA_ADDR1,
PWRAP_ADC_RDATA_ADDR2,
soc: mediatek: pwrap: add support for MT7622 SoC Add the registers, callbacks and data structures required to make the PMIC wrapper work on MT7622. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:48 +00:00
/* MT7622 only regs */
PWRAP_STA,
PWRAP_CLR,
PWRAP_DVFS_ADR8,
PWRAP_DVFS_WDATA8,
PWRAP_DVFS_ADR9,
PWRAP_DVFS_WDATA9,
PWRAP_DVFS_ADR10,
PWRAP_DVFS_WDATA10,
PWRAP_DVFS_ADR11,
PWRAP_DVFS_WDATA11,
PWRAP_DVFS_ADR12,
PWRAP_DVFS_WDATA12,
PWRAP_DVFS_ADR13,
PWRAP_DVFS_WDATA13,
PWRAP_DVFS_ADR14,
PWRAP_DVFS_WDATA14,
PWRAP_DVFS_ADR15,
PWRAP_DVFS_WDATA15,
PWRAP_EXT_CK,
PWRAP_ADC_RDATA_ADDR,
PWRAP_GPS_STA,
PWRAP_SW_RST,
PWRAP_DVFS_STEP_CTRL0,
PWRAP_DVFS_STEP_CTRL1,
PWRAP_DVFS_STEP_CTRL2,
PWRAP_SPI2_CTRL,
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
/* MT8135 only regs */
PWRAP_CSHEXT,
PWRAP_EVENT_IN_EN,
PWRAP_EVENT_DST_EN,
PWRAP_RRARB_INIT,
PWRAP_RRARB_EN,
PWRAP_RRARB_STA0,
PWRAP_RRARB_STA1,
PWRAP_EVENT_STA,
PWRAP_EVENT_STACLR,
PWRAP_CIPHER_LOAD,
PWRAP_CIPHER_START,
/* MT8173 only regs */
PWRAP_RDDMY,
PWRAP_SI_CK_CON,
PWRAP_DVFS_ADR0,
PWRAP_DVFS_WDATA0,
PWRAP_DVFS_ADR1,
PWRAP_DVFS_WDATA1,
PWRAP_DVFS_ADR2,
PWRAP_DVFS_WDATA2,
PWRAP_DVFS_ADR3,
PWRAP_DVFS_WDATA3,
PWRAP_DVFS_ADR4,
PWRAP_DVFS_WDATA4,
PWRAP_DVFS_ADR5,
PWRAP_DVFS_WDATA5,
PWRAP_DVFS_ADR6,
PWRAP_DVFS_WDATA6,
PWRAP_DVFS_ADR7,
PWRAP_DVFS_WDATA7,
PWRAP_SPMINF_STA,
PWRAP_CIPHER_EN,
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
/* MT8183 only regs */
PWRAP_SI_SAMPLE_CTRL,
PWRAP_CSLEXT_WRITE,
PWRAP_CSLEXT_READ,
PWRAP_EXT_CK_WRITE,
PWRAP_STAUPD_CTRL,
PWRAP_WACS_P2P_EN,
PWRAP_INIT_DONE_P2P,
PWRAP_WACS_MD32_EN,
PWRAP_INIT_DONE_MD32,
PWRAP_INT1_EN,
PWRAP_INT1_FLG,
PWRAP_INT1_CLR,
PWRAP_WDT_SRC_EN_1,
PWRAP_INT_GPS_AUXADC_CMD_ADDR,
PWRAP_INT_GPS_AUXADC_CMD,
PWRAP_INT_GPS_AUXADC_RDATA_ADDR,
PWRAP_EXT_GPS_AUXADC_RDATA_ADDR,
PWRAP_GPSINF_0_STA,
PWRAP_GPSINF_1_STA,
soc: mediatek: pwrap: add support for MT8516 pwrap Add the code to support the pwrap IP on the MediaTek MT8516 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-03-23 21:15:53 +00:00
/* MT8516 only regs */
PWRAP_OP_TYPE,
PWRAP_MSB_FIRST,
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
};
soc: mediatek: PMIC wrap: add MT2701/7623 support Add the registers, callbacks and data structures required to make the wrapper work on MT2701 and MT7623. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:15 +00:00
static int mt2701_regs[] = {
[PWRAP_MUX_SEL] = 0x0,
[PWRAP_WRAP_EN] = 0x4,
[PWRAP_DIO_EN] = 0x8,
[PWRAP_SIDLY] = 0xc,
[PWRAP_RDDMY] = 0x18,
[PWRAP_SI_CK_CON] = 0x1c,
[PWRAP_CSHEXT_WRITE] = 0x20,
[PWRAP_CSHEXT_READ] = 0x24,
[PWRAP_CSLEXT_START] = 0x28,
[PWRAP_CSLEXT_END] = 0x2c,
[PWRAP_STAUPD_PRD] = 0x30,
[PWRAP_STAUPD_GRPEN] = 0x34,
[PWRAP_STAUPD_MAN_TRIG] = 0x38,
[PWRAP_STAUPD_STA] = 0x3c,
[PWRAP_WRAP_STA] = 0x44,
[PWRAP_HARB_INIT] = 0x48,
[PWRAP_HARB_HPRIO] = 0x4c,
[PWRAP_HIPRIO_ARB_EN] = 0x50,
[PWRAP_HARB_STA0] = 0x54,
[PWRAP_HARB_STA1] = 0x58,
[PWRAP_MAN_EN] = 0x5c,
[PWRAP_MAN_CMD] = 0x60,
[PWRAP_MAN_RDATA] = 0x64,
[PWRAP_MAN_VLDCLR] = 0x68,
[PWRAP_WACS0_EN] = 0x6c,
[PWRAP_INIT_DONE0] = 0x70,
[PWRAP_WACS0_CMD] = 0x74,
[PWRAP_WACS0_RDATA] = 0x78,
[PWRAP_WACS0_VLDCLR] = 0x7c,
[PWRAP_WACS1_EN] = 0x80,
[PWRAP_INIT_DONE1] = 0x84,
[PWRAP_WACS1_CMD] = 0x88,
[PWRAP_WACS1_RDATA] = 0x8c,
[PWRAP_WACS1_VLDCLR] = 0x90,
[PWRAP_WACS2_EN] = 0x94,
[PWRAP_INIT_DONE2] = 0x98,
[PWRAP_WACS2_CMD] = 0x9c,
[PWRAP_WACS2_RDATA] = 0xa0,
[PWRAP_WACS2_VLDCLR] = 0xa4,
[PWRAP_INT_EN] = 0xa8,
[PWRAP_INT_FLG_RAW] = 0xac,
[PWRAP_INT_FLG] = 0xb0,
[PWRAP_INT_CLR] = 0xb4,
[PWRAP_SIG_ADR] = 0xb8,
[PWRAP_SIG_MODE] = 0xbc,
[PWRAP_SIG_VALUE] = 0xc0,
[PWRAP_SIG_ERRVAL] = 0xc4,
[PWRAP_CRC_EN] = 0xc8,
[PWRAP_TIMER_EN] = 0xcc,
[PWRAP_TIMER_STA] = 0xd0,
[PWRAP_WDT_UNIT] = 0xd4,
[PWRAP_WDT_SRC_EN] = 0xd8,
[PWRAP_WDT_FLG] = 0xdc,
[PWRAP_DEBUG_INT_SEL] = 0xe0,
[PWRAP_DVFS_ADR0] = 0xe4,
[PWRAP_DVFS_WDATA0] = 0xe8,
[PWRAP_DVFS_ADR1] = 0xec,
[PWRAP_DVFS_WDATA1] = 0xf0,
[PWRAP_DVFS_ADR2] = 0xf4,
[PWRAP_DVFS_WDATA2] = 0xf8,
[PWRAP_DVFS_ADR3] = 0xfc,
[PWRAP_DVFS_WDATA3] = 0x100,
[PWRAP_DVFS_ADR4] = 0x104,
[PWRAP_DVFS_WDATA4] = 0x108,
[PWRAP_DVFS_ADR5] = 0x10c,
[PWRAP_DVFS_WDATA5] = 0x110,
[PWRAP_DVFS_ADR6] = 0x114,
[PWRAP_DVFS_WDATA6] = 0x118,
[PWRAP_DVFS_ADR7] = 0x11c,
[PWRAP_DVFS_WDATA7] = 0x120,
[PWRAP_CIPHER_KEY_SEL] = 0x124,
[PWRAP_CIPHER_IV_SEL] = 0x128,
[PWRAP_CIPHER_EN] = 0x12c,
[PWRAP_CIPHER_RDY] = 0x130,
[PWRAP_CIPHER_MODE] = 0x134,
[PWRAP_CIPHER_SWRST] = 0x138,
[PWRAP_DCM_EN] = 0x13c,
[PWRAP_DCM_DBC_PRD] = 0x140,
[PWRAP_ADC_CMD_ADDR] = 0x144,
[PWRAP_PWRAP_ADC_CMD] = 0x148,
[PWRAP_ADC_RDY_ADDR] = 0x14c,
[PWRAP_ADC_RDATA_ADDR1] = 0x150,
[PWRAP_ADC_RDATA_ADDR2] = 0x154,
};
soc: mediatek: pwrap: add pwrap driver for mt6765 SoCs mt6765 is a highly integrated SoCs, it uses mt6357 for power management. This patch adds pwrap driver to access mt6357. Pwrap of mt6765 support dynamic priority meichanism, sequence monitor and starvation mechanism to make transaction more reliable. Signed-off-by: Argus Lin <argus.lin@mediatek.com> [mb: change has_bridge to capabilities] Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-04 12:31:53 +00:00
static int mt6765_regs[] = {
[PWRAP_MUX_SEL] = 0x0,
[PWRAP_WRAP_EN] = 0x4,
[PWRAP_DIO_EN] = 0x8,
[PWRAP_RDDMY] = 0x20,
[PWRAP_CSHEXT_WRITE] = 0x24,
[PWRAP_CSHEXT_READ] = 0x28,
[PWRAP_CSLEXT_START] = 0x2C,
[PWRAP_CSLEXT_END] = 0x30,
[PWRAP_STAUPD_PRD] = 0x3C,
[PWRAP_HARB_HPRIO] = 0x68,
[PWRAP_HIPRIO_ARB_EN] = 0x6C,
[PWRAP_MAN_EN] = 0x7C,
[PWRAP_MAN_CMD] = 0x80,
[PWRAP_WACS0_EN] = 0x8C,
[PWRAP_WACS1_EN] = 0x94,
[PWRAP_WACS2_EN] = 0x9C,
[PWRAP_INIT_DONE2] = 0xA0,
[PWRAP_WACS2_CMD] = 0xC20,
[PWRAP_WACS2_RDATA] = 0xC24,
[PWRAP_WACS2_VLDCLR] = 0xC28,
[PWRAP_INT_EN] = 0xB4,
[PWRAP_INT_FLG_RAW] = 0xB8,
[PWRAP_INT_FLG] = 0xBC,
[PWRAP_INT_CLR] = 0xC0,
[PWRAP_TIMER_EN] = 0xE8,
[PWRAP_WDT_UNIT] = 0xF0,
[PWRAP_WDT_SRC_EN] = 0xF4,
[PWRAP_DCM_EN] = 0x1DC,
[PWRAP_DCM_DBC_PRD] = 0x1E0,
};
soc: mediatek: pwrap: add pwrap driver for MT6779 SoCs MT6779 is a highly integrated SoCs, it uses PMIC_MT6359 for power management. This patch adds pwrap master driver to access PMIC_MT6359. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-02-16 06:17:22 +00:00
static int mt6779_regs[] = {
[PWRAP_MUX_SEL] = 0x0,
[PWRAP_WRAP_EN] = 0x4,
[PWRAP_DIO_EN] = 0x8,
[PWRAP_RDDMY] = 0x20,
[PWRAP_CSHEXT_WRITE] = 0x24,
[PWRAP_CSHEXT_READ] = 0x28,
[PWRAP_CSLEXT_WRITE] = 0x2C,
[PWRAP_CSLEXT_READ] = 0x30,
[PWRAP_EXT_CK_WRITE] = 0x34,
[PWRAP_STAUPD_CTRL] = 0x3C,
[PWRAP_STAUPD_GRPEN] = 0x40,
[PWRAP_EINT_STA0_ADR] = 0x44,
[PWRAP_HARB_HPRIO] = 0x68,
[PWRAP_HIPRIO_ARB_EN] = 0x6C,
[PWRAP_MAN_EN] = 0x7C,
[PWRAP_MAN_CMD] = 0x80,
[PWRAP_WACS0_EN] = 0x8C,
[PWRAP_INIT_DONE0] = 0x90,
[PWRAP_WACS1_EN] = 0x94,
[PWRAP_WACS2_EN] = 0x9C,
[PWRAP_INIT_DONE1] = 0x98,
[PWRAP_INIT_DONE2] = 0xA0,
[PWRAP_INT_EN] = 0xBC,
[PWRAP_INT_FLG_RAW] = 0xC0,
[PWRAP_INT_FLG] = 0xC4,
[PWRAP_INT_CLR] = 0xC8,
[PWRAP_INT1_EN] = 0xCC,
[PWRAP_INT1_FLG] = 0xD4,
[PWRAP_INT1_CLR] = 0xD8,
[PWRAP_TIMER_EN] = 0xF0,
[PWRAP_WDT_UNIT] = 0xF8,
[PWRAP_WDT_SRC_EN] = 0xFC,
[PWRAP_WDT_SRC_EN_1] = 0x100,
[PWRAP_WACS2_CMD] = 0xC20,
[PWRAP_WACS2_RDATA] = 0xC24,
[PWRAP_WACS2_VLDCLR] = 0xC28,
};
soc: mediatek: pwrap: add pwrap driver for mt6797 SoCs mt6797 is a highly integrated SoCs, it uses mt6351 for power management. This patch adds pwrap driver to access mt6351. Pwrap of mt6797 support dynamic priority meichanism, sequence monitor and starvation mechanism to make transaction more reliable. A big change from V4 to V5 is we remove INT1 interrupt declaration since it is only for debug purpose. The PWRAP_RDDMY, RESET and DCM can use legacy setting, it is backwards compatible. The new caps flag declaration is not needed, just remove it. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-06-11 10:49:59 +00:00
static int mt6797_regs[] = {
[PWRAP_MUX_SEL] = 0x0,
[PWRAP_WRAP_EN] = 0x4,
[PWRAP_DIO_EN] = 0x8,
[PWRAP_SIDLY] = 0xC,
[PWRAP_RDDMY] = 0x10,
[PWRAP_CSHEXT_WRITE] = 0x18,
[PWRAP_CSHEXT_READ] = 0x1C,
[PWRAP_CSLEXT_START] = 0x20,
[PWRAP_CSLEXT_END] = 0x24,
[PWRAP_STAUPD_PRD] = 0x28,
[PWRAP_HARB_HPRIO] = 0x50,
[PWRAP_HIPRIO_ARB_EN] = 0x54,
[PWRAP_MAN_EN] = 0x60,
[PWRAP_MAN_CMD] = 0x64,
[PWRAP_WACS0_EN] = 0x70,
[PWRAP_WACS1_EN] = 0x84,
[PWRAP_WACS2_EN] = 0x98,
[PWRAP_INIT_DONE2] = 0x9C,
[PWRAP_WACS2_CMD] = 0xA0,
[PWRAP_WACS2_RDATA] = 0xA4,
[PWRAP_WACS2_VLDCLR] = 0xA8,
[PWRAP_INT_EN] = 0xC0,
[PWRAP_INT_FLG_RAW] = 0xC4,
[PWRAP_INT_FLG] = 0xC8,
[PWRAP_INT_CLR] = 0xCC,
[PWRAP_TIMER_EN] = 0xF4,
[PWRAP_WDT_UNIT] = 0xFC,
[PWRAP_WDT_SRC_EN] = 0x100,
[PWRAP_DCM_EN] = 0x1CC,
[PWRAP_DCM_DBC_PRD] = 0x1D4,
};
soc: mediatek: pwrap: add pwrap driver for MT6873/8192 SoCs MT6873/8192 are highly integrated SoCs and use PMIC_MT6359 for power management. This patch adds pwrap master driver to access PMIC_MT6359. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-5-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:45 +00:00
static int mt6873_regs[] = {
[PWRAP_INIT_DONE2] = 0x0,
[PWRAP_TIMER_EN] = 0x3E0,
[PWRAP_INT_EN] = 0x448,
[PWRAP_WACS2_CMD] = 0xC80,
[PWRAP_SWINF_2_WDATA_31_0] = 0xC84,
[PWRAP_SWINF_2_RDATA_31_0] = 0xC94,
[PWRAP_WACS2_VLDCLR] = 0xCA4,
[PWRAP_WACS2_RDATA] = 0xCA8,
};
soc: mediatek: pwrap: add support for MT7622 SoC Add the registers, callbacks and data structures required to make the PMIC wrapper work on MT7622. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:48 +00:00
static int mt7622_regs[] = {
[PWRAP_MUX_SEL] = 0x0,
[PWRAP_WRAP_EN] = 0x4,
[PWRAP_DIO_EN] = 0x8,
[PWRAP_SIDLY] = 0xC,
[PWRAP_RDDMY] = 0x10,
[PWRAP_SI_CK_CON] = 0x14,
[PWRAP_CSHEXT_WRITE] = 0x18,
[PWRAP_CSHEXT_READ] = 0x1C,
[PWRAP_CSLEXT_START] = 0x20,
[PWRAP_CSLEXT_END] = 0x24,
[PWRAP_STAUPD_PRD] = 0x28,
[PWRAP_STAUPD_GRPEN] = 0x2C,
[PWRAP_EINT_STA0_ADR] = 0x30,
[PWRAP_EINT_STA1_ADR] = 0x34,
[PWRAP_STA] = 0x38,
[PWRAP_CLR] = 0x3C,
[PWRAP_STAUPD_MAN_TRIG] = 0x40,
[PWRAP_STAUPD_STA] = 0x44,
[PWRAP_WRAP_STA] = 0x48,
[PWRAP_HARB_INIT] = 0x4C,
[PWRAP_HARB_HPRIO] = 0x50,
[PWRAP_HIPRIO_ARB_EN] = 0x54,
[PWRAP_HARB_STA0] = 0x58,
[PWRAP_HARB_STA1] = 0x5C,
[PWRAP_MAN_EN] = 0x60,
[PWRAP_MAN_CMD] = 0x64,
[PWRAP_MAN_RDATA] = 0x68,
[PWRAP_MAN_VLDCLR] = 0x6C,
[PWRAP_WACS0_EN] = 0x70,
[PWRAP_INIT_DONE0] = 0x74,
[PWRAP_WACS0_CMD] = 0x78,
[PWRAP_WACS0_RDATA] = 0x7C,
[PWRAP_WACS0_VLDCLR] = 0x80,
[PWRAP_WACS1_EN] = 0x84,
[PWRAP_INIT_DONE1] = 0x88,
[PWRAP_WACS1_CMD] = 0x8C,
[PWRAP_WACS1_RDATA] = 0x90,
[PWRAP_WACS1_VLDCLR] = 0x94,
[PWRAP_WACS2_EN] = 0x98,
[PWRAP_INIT_DONE2] = 0x9C,
[PWRAP_WACS2_CMD] = 0xA0,
[PWRAP_WACS2_RDATA] = 0xA4,
[PWRAP_WACS2_VLDCLR] = 0xA8,
[PWRAP_INT_EN] = 0xAC,
[PWRAP_INT_FLG_RAW] = 0xB0,
[PWRAP_INT_FLG] = 0xB4,
[PWRAP_INT_CLR] = 0xB8,
[PWRAP_SIG_ADR] = 0xBC,
[PWRAP_SIG_MODE] = 0xC0,
[PWRAP_SIG_VALUE] = 0xC4,
[PWRAP_SIG_ERRVAL] = 0xC8,
[PWRAP_CRC_EN] = 0xCC,
[PWRAP_TIMER_EN] = 0xD0,
[PWRAP_TIMER_STA] = 0xD4,
[PWRAP_WDT_UNIT] = 0xD8,
[PWRAP_WDT_SRC_EN] = 0xDC,
[PWRAP_WDT_FLG] = 0xE0,
[PWRAP_DEBUG_INT_SEL] = 0xE4,
[PWRAP_DVFS_ADR0] = 0xE8,
[PWRAP_DVFS_WDATA0] = 0xEC,
[PWRAP_DVFS_ADR1] = 0xF0,
[PWRAP_DVFS_WDATA1] = 0xF4,
[PWRAP_DVFS_ADR2] = 0xF8,
[PWRAP_DVFS_WDATA2] = 0xFC,
[PWRAP_DVFS_ADR3] = 0x100,
[PWRAP_DVFS_WDATA3] = 0x104,
[PWRAP_DVFS_ADR4] = 0x108,
[PWRAP_DVFS_WDATA4] = 0x10C,
[PWRAP_DVFS_ADR5] = 0x110,
[PWRAP_DVFS_WDATA5] = 0x114,
[PWRAP_DVFS_ADR6] = 0x118,
[PWRAP_DVFS_WDATA6] = 0x11C,
[PWRAP_DVFS_ADR7] = 0x120,
[PWRAP_DVFS_WDATA7] = 0x124,
[PWRAP_DVFS_ADR8] = 0x128,
[PWRAP_DVFS_WDATA8] = 0x12C,
[PWRAP_DVFS_ADR9] = 0x130,
[PWRAP_DVFS_WDATA9] = 0x134,
[PWRAP_DVFS_ADR10] = 0x138,
[PWRAP_DVFS_WDATA10] = 0x13C,
[PWRAP_DVFS_ADR11] = 0x140,
[PWRAP_DVFS_WDATA11] = 0x144,
[PWRAP_DVFS_ADR12] = 0x148,
[PWRAP_DVFS_WDATA12] = 0x14C,
[PWRAP_DVFS_ADR13] = 0x150,
[PWRAP_DVFS_WDATA13] = 0x154,
[PWRAP_DVFS_ADR14] = 0x158,
[PWRAP_DVFS_WDATA14] = 0x15C,
[PWRAP_DVFS_ADR15] = 0x160,
[PWRAP_DVFS_WDATA15] = 0x164,
[PWRAP_SPMINF_STA] = 0x168,
[PWRAP_CIPHER_KEY_SEL] = 0x16C,
[PWRAP_CIPHER_IV_SEL] = 0x170,
[PWRAP_CIPHER_EN] = 0x174,
[PWRAP_CIPHER_RDY] = 0x178,
[PWRAP_CIPHER_MODE] = 0x17C,
[PWRAP_CIPHER_SWRST] = 0x180,
[PWRAP_DCM_EN] = 0x184,
[PWRAP_DCM_DBC_PRD] = 0x188,
[PWRAP_EXT_CK] = 0x18C,
[PWRAP_ADC_CMD_ADDR] = 0x190,
[PWRAP_PWRAP_ADC_CMD] = 0x194,
[PWRAP_ADC_RDATA_ADDR] = 0x198,
[PWRAP_GPS_STA] = 0x19C,
[PWRAP_SW_RST] = 0x1A0,
[PWRAP_DVFS_STEP_CTRL0] = 0x238,
[PWRAP_DVFS_STEP_CTRL1] = 0x23C,
[PWRAP_DVFS_STEP_CTRL2] = 0x240,
[PWRAP_SPI2_CTRL] = 0x244,
};
soc: mediatek: pwrap: order SoCs and PMICs ascending Order SoC and PMIC numbers ascending to make the code more readable. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-25 13:46:59 +00:00
static int mt8135_regs[] = {
[PWRAP_MUX_SEL] = 0x0,
[PWRAP_WRAP_EN] = 0x4,
[PWRAP_DIO_EN] = 0x8,
[PWRAP_SIDLY] = 0xc,
[PWRAP_CSHEXT] = 0x10,
[PWRAP_CSHEXT_WRITE] = 0x14,
[PWRAP_CSHEXT_READ] = 0x18,
[PWRAP_CSLEXT_START] = 0x1c,
[PWRAP_CSLEXT_END] = 0x20,
[PWRAP_STAUPD_PRD] = 0x24,
[PWRAP_STAUPD_GRPEN] = 0x28,
[PWRAP_STAUPD_MAN_TRIG] = 0x2c,
[PWRAP_STAUPD_STA] = 0x30,
[PWRAP_EVENT_IN_EN] = 0x34,
[PWRAP_EVENT_DST_EN] = 0x38,
[PWRAP_WRAP_STA] = 0x3c,
[PWRAP_RRARB_INIT] = 0x40,
[PWRAP_RRARB_EN] = 0x44,
[PWRAP_RRARB_STA0] = 0x48,
[PWRAP_RRARB_STA1] = 0x4c,
[PWRAP_HARB_INIT] = 0x50,
[PWRAP_HARB_HPRIO] = 0x54,
[PWRAP_HIPRIO_ARB_EN] = 0x58,
[PWRAP_HARB_STA0] = 0x5c,
[PWRAP_HARB_STA1] = 0x60,
[PWRAP_MAN_EN] = 0x64,
[PWRAP_MAN_CMD] = 0x68,
[PWRAP_MAN_RDATA] = 0x6c,
[PWRAP_MAN_VLDCLR] = 0x70,
[PWRAP_WACS0_EN] = 0x74,
[PWRAP_INIT_DONE0] = 0x78,
[PWRAP_WACS0_CMD] = 0x7c,
[PWRAP_WACS0_RDATA] = 0x80,
[PWRAP_WACS0_VLDCLR] = 0x84,
[PWRAP_WACS1_EN] = 0x88,
[PWRAP_INIT_DONE1] = 0x8c,
[PWRAP_WACS1_CMD] = 0x90,
[PWRAP_WACS1_RDATA] = 0x94,
[PWRAP_WACS1_VLDCLR] = 0x98,
[PWRAP_WACS2_EN] = 0x9c,
[PWRAP_INIT_DONE2] = 0xa0,
[PWRAP_WACS2_CMD] = 0xa4,
[PWRAP_WACS2_RDATA] = 0xa8,
[PWRAP_WACS2_VLDCLR] = 0xac,
[PWRAP_INT_EN] = 0xb0,
[PWRAP_INT_FLG_RAW] = 0xb4,
[PWRAP_INT_FLG] = 0xb8,
[PWRAP_INT_CLR] = 0xbc,
[PWRAP_SIG_ADR] = 0xc0,
[PWRAP_SIG_MODE] = 0xc4,
[PWRAP_SIG_VALUE] = 0xc8,
[PWRAP_SIG_ERRVAL] = 0xcc,
[PWRAP_CRC_EN] = 0xd0,
[PWRAP_EVENT_STA] = 0xd4,
[PWRAP_EVENT_STACLR] = 0xd8,
[PWRAP_TIMER_EN] = 0xdc,
[PWRAP_TIMER_STA] = 0xe0,
[PWRAP_WDT_UNIT] = 0xe4,
[PWRAP_WDT_SRC_EN] = 0xe8,
[PWRAP_WDT_FLG] = 0xec,
[PWRAP_DEBUG_INT_SEL] = 0xf0,
[PWRAP_CIPHER_KEY_SEL] = 0x134,
[PWRAP_CIPHER_IV_SEL] = 0x138,
[PWRAP_CIPHER_LOAD] = 0x13c,
[PWRAP_CIPHER_START] = 0x140,
[PWRAP_CIPHER_RDY] = 0x144,
[PWRAP_CIPHER_MODE] = 0x148,
[PWRAP_CIPHER_SWRST] = 0x14c,
[PWRAP_DCM_EN] = 0x15c,
[PWRAP_DCM_DBC_PRD] = 0x160,
};
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
static int mt8173_regs[] = {
[PWRAP_MUX_SEL] = 0x0,
[PWRAP_WRAP_EN] = 0x4,
[PWRAP_DIO_EN] = 0x8,
[PWRAP_SIDLY] = 0xc,
[PWRAP_RDDMY] = 0x10,
[PWRAP_SI_CK_CON] = 0x14,
[PWRAP_CSHEXT_WRITE] = 0x18,
[PWRAP_CSHEXT_READ] = 0x1c,
[PWRAP_CSLEXT_START] = 0x20,
[PWRAP_CSLEXT_END] = 0x24,
[PWRAP_STAUPD_PRD] = 0x28,
[PWRAP_STAUPD_GRPEN] = 0x2c,
[PWRAP_STAUPD_MAN_TRIG] = 0x40,
[PWRAP_STAUPD_STA] = 0x44,
[PWRAP_WRAP_STA] = 0x48,
[PWRAP_HARB_INIT] = 0x4c,
[PWRAP_HARB_HPRIO] = 0x50,
[PWRAP_HIPRIO_ARB_EN] = 0x54,
[PWRAP_HARB_STA0] = 0x58,
[PWRAP_HARB_STA1] = 0x5c,
[PWRAP_MAN_EN] = 0x60,
[PWRAP_MAN_CMD] = 0x64,
[PWRAP_MAN_RDATA] = 0x68,
[PWRAP_MAN_VLDCLR] = 0x6c,
[PWRAP_WACS0_EN] = 0x70,
[PWRAP_INIT_DONE0] = 0x74,
[PWRAP_WACS0_CMD] = 0x78,
[PWRAP_WACS0_RDATA] = 0x7c,
[PWRAP_WACS0_VLDCLR] = 0x80,
[PWRAP_WACS1_EN] = 0x84,
[PWRAP_INIT_DONE1] = 0x88,
[PWRAP_WACS1_CMD] = 0x8c,
[PWRAP_WACS1_RDATA] = 0x90,
[PWRAP_WACS1_VLDCLR] = 0x94,
[PWRAP_WACS2_EN] = 0x98,
[PWRAP_INIT_DONE2] = 0x9c,
[PWRAP_WACS2_CMD] = 0xa0,
[PWRAP_WACS2_RDATA] = 0xa4,
[PWRAP_WACS2_VLDCLR] = 0xa8,
[PWRAP_INT_EN] = 0xac,
[PWRAP_INT_FLG_RAW] = 0xb0,
[PWRAP_INT_FLG] = 0xb4,
[PWRAP_INT_CLR] = 0xb8,
[PWRAP_SIG_ADR] = 0xbc,
[PWRAP_SIG_MODE] = 0xc0,
[PWRAP_SIG_VALUE] = 0xc4,
[PWRAP_SIG_ERRVAL] = 0xc8,
[PWRAP_CRC_EN] = 0xcc,
[PWRAP_TIMER_EN] = 0xd0,
[PWRAP_TIMER_STA] = 0xd4,
[PWRAP_WDT_UNIT] = 0xd8,
[PWRAP_WDT_SRC_EN] = 0xdc,
[PWRAP_WDT_FLG] = 0xe0,
[PWRAP_DEBUG_INT_SEL] = 0xe4,
[PWRAP_DVFS_ADR0] = 0xe8,
[PWRAP_DVFS_WDATA0] = 0xec,
[PWRAP_DVFS_ADR1] = 0xf0,
[PWRAP_DVFS_WDATA1] = 0xf4,
[PWRAP_DVFS_ADR2] = 0xf8,
[PWRAP_DVFS_WDATA2] = 0xfc,
[PWRAP_DVFS_ADR3] = 0x100,
[PWRAP_DVFS_WDATA3] = 0x104,
[PWRAP_DVFS_ADR4] = 0x108,
[PWRAP_DVFS_WDATA4] = 0x10c,
[PWRAP_DVFS_ADR5] = 0x110,
[PWRAP_DVFS_WDATA5] = 0x114,
[PWRAP_DVFS_ADR6] = 0x118,
[PWRAP_DVFS_WDATA6] = 0x11c,
[PWRAP_DVFS_ADR7] = 0x120,
[PWRAP_DVFS_WDATA7] = 0x124,
[PWRAP_SPMINF_STA] = 0x128,
[PWRAP_CIPHER_KEY_SEL] = 0x12c,
[PWRAP_CIPHER_IV_SEL] = 0x130,
[PWRAP_CIPHER_EN] = 0x134,
[PWRAP_CIPHER_RDY] = 0x138,
[PWRAP_CIPHER_MODE] = 0x13c,
[PWRAP_CIPHER_SWRST] = 0x140,
[PWRAP_DCM_EN] = 0x144,
[PWRAP_DCM_DBC_PRD] = 0x148,
};
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
static int mt8183_regs[] = {
[PWRAP_MUX_SEL] = 0x0,
[PWRAP_WRAP_EN] = 0x4,
[PWRAP_DIO_EN] = 0x8,
[PWRAP_SI_SAMPLE_CTRL] = 0xC,
[PWRAP_RDDMY] = 0x14,
[PWRAP_CSHEXT_WRITE] = 0x18,
[PWRAP_CSHEXT_READ] = 0x1C,
[PWRAP_CSLEXT_WRITE] = 0x20,
[PWRAP_CSLEXT_READ] = 0x24,
[PWRAP_EXT_CK_WRITE] = 0x28,
[PWRAP_STAUPD_CTRL] = 0x30,
[PWRAP_STAUPD_GRPEN] = 0x34,
[PWRAP_EINT_STA0_ADR] = 0x38,
[PWRAP_HARB_HPRIO] = 0x5C,
[PWRAP_HIPRIO_ARB_EN] = 0x60,
[PWRAP_MAN_EN] = 0x70,
[PWRAP_MAN_CMD] = 0x74,
[PWRAP_WACS0_EN] = 0x80,
[PWRAP_INIT_DONE0] = 0x84,
[PWRAP_WACS1_EN] = 0x88,
[PWRAP_INIT_DONE1] = 0x8C,
[PWRAP_WACS2_EN] = 0x90,
[PWRAP_INIT_DONE2] = 0x94,
[PWRAP_WACS_P2P_EN] = 0xA0,
[PWRAP_INIT_DONE_P2P] = 0xA4,
[PWRAP_WACS_MD32_EN] = 0xA8,
[PWRAP_INIT_DONE_MD32] = 0xAC,
[PWRAP_INT_EN] = 0xB0,
[PWRAP_INT_FLG] = 0xB8,
[PWRAP_INT_CLR] = 0xBC,
[PWRAP_INT1_EN] = 0xC0,
[PWRAP_INT1_FLG] = 0xC8,
[PWRAP_INT1_CLR] = 0xCC,
[PWRAP_SIG_ADR] = 0xD0,
[PWRAP_CRC_EN] = 0xE0,
[PWRAP_TIMER_EN] = 0xE4,
[PWRAP_WDT_UNIT] = 0xEC,
[PWRAP_WDT_SRC_EN] = 0xF0,
[PWRAP_WDT_SRC_EN_1] = 0xF4,
[PWRAP_INT_GPS_AUXADC_CMD_ADDR] = 0x1DC,
[PWRAP_INT_GPS_AUXADC_CMD] = 0x1E0,
[PWRAP_INT_GPS_AUXADC_RDATA_ADDR] = 0x1E4,
[PWRAP_EXT_GPS_AUXADC_RDATA_ADDR] = 0x1E8,
[PWRAP_GPSINF_0_STA] = 0x1EC,
[PWRAP_GPSINF_1_STA] = 0x1F0,
[PWRAP_WACS2_CMD] = 0xC20,
[PWRAP_WACS2_RDATA] = 0xC24,
[PWRAP_WACS2_VLDCLR] = 0xC28,
};
soc: mediatek: pwrap: add pwrap driver for MT8195 SoC MT8195 are highly integrated SoC and use PMIC_MT6359 for power management. This patch adds pwrap master driver to access PMIC_MT6359. Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Link: https://lore.kernel.org/r/20210602112050.12338-3-james.lo@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-06-02 11:20:50 +00:00
static int mt8195_regs[] = {
[PWRAP_INIT_DONE2] = 0x0,
[PWRAP_STAUPD_CTRL] = 0x4C,
[PWRAP_TIMER_EN] = 0x3E4,
[PWRAP_INT_EN] = 0x420,
[PWRAP_INT_FLG] = 0x428,
[PWRAP_INT_CLR] = 0x42C,
[PWRAP_INT1_EN] = 0x450,
[PWRAP_INT1_FLG] = 0x458,
[PWRAP_INT1_CLR] = 0x45C,
[PWRAP_WACS2_CMD] = 0x880,
[PWRAP_SWINF_2_WDATA_31_0] = 0x884,
[PWRAP_SWINF_2_RDATA_31_0] = 0x894,
[PWRAP_WACS2_VLDCLR] = 0x8A4,
[PWRAP_WACS2_RDATA] = 0x8A8,
};
soc: mediatek: pwrap: add support for MT8516 pwrap Add the code to support the pwrap IP on the MediaTek MT8516 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-03-23 21:15:53 +00:00
static int mt8516_regs[] = {
[PWRAP_MUX_SEL] = 0x0,
[PWRAP_WRAP_EN] = 0x4,
[PWRAP_DIO_EN] = 0x8,
[PWRAP_SIDLY] = 0xc,
[PWRAP_RDDMY] = 0x10,
[PWRAP_SI_CK_CON] = 0x14,
[PWRAP_CSHEXT_WRITE] = 0x18,
[PWRAP_CSHEXT_READ] = 0x1c,
[PWRAP_CSLEXT_START] = 0x20,
[PWRAP_CSLEXT_END] = 0x24,
[PWRAP_STAUPD_PRD] = 0x28,
[PWRAP_STAUPD_GRPEN] = 0x2c,
[PWRAP_STAUPD_MAN_TRIG] = 0x40,
[PWRAP_STAUPD_STA] = 0x44,
[PWRAP_WRAP_STA] = 0x48,
[PWRAP_HARB_INIT] = 0x4c,
[PWRAP_HARB_HPRIO] = 0x50,
[PWRAP_HIPRIO_ARB_EN] = 0x54,
[PWRAP_HARB_STA0] = 0x58,
[PWRAP_HARB_STA1] = 0x5c,
[PWRAP_MAN_EN] = 0x60,
[PWRAP_MAN_CMD] = 0x64,
[PWRAP_MAN_RDATA] = 0x68,
[PWRAP_MAN_VLDCLR] = 0x6c,
[PWRAP_WACS0_EN] = 0x70,
[PWRAP_INIT_DONE0] = 0x74,
[PWRAP_WACS0_CMD] = 0x78,
[PWRAP_WACS0_RDATA] = 0x7c,
[PWRAP_WACS0_VLDCLR] = 0x80,
[PWRAP_WACS1_EN] = 0x84,
[PWRAP_INIT_DONE1] = 0x88,
[PWRAP_WACS1_CMD] = 0x8c,
[PWRAP_WACS1_RDATA] = 0x90,
[PWRAP_WACS1_VLDCLR] = 0x94,
[PWRAP_WACS2_EN] = 0x98,
[PWRAP_INIT_DONE2] = 0x9c,
[PWRAP_WACS2_CMD] = 0xa0,
[PWRAP_WACS2_RDATA] = 0xa4,
[PWRAP_WACS2_VLDCLR] = 0xa8,
[PWRAP_INT_EN] = 0xac,
[PWRAP_INT_FLG_RAW] = 0xb0,
[PWRAP_INT_FLG] = 0xb4,
[PWRAP_INT_CLR] = 0xb8,
[PWRAP_SIG_ADR] = 0xbc,
[PWRAP_SIG_MODE] = 0xc0,
[PWRAP_SIG_VALUE] = 0xc4,
[PWRAP_SIG_ERRVAL] = 0xc8,
[PWRAP_CRC_EN] = 0xcc,
[PWRAP_TIMER_EN] = 0xd0,
[PWRAP_TIMER_STA] = 0xd4,
[PWRAP_WDT_UNIT] = 0xd8,
[PWRAP_WDT_SRC_EN] = 0xdc,
[PWRAP_WDT_FLG] = 0xe0,
[PWRAP_DEBUG_INT_SEL] = 0xe4,
[PWRAP_DVFS_ADR0] = 0xe8,
[PWRAP_DVFS_WDATA0] = 0xec,
[PWRAP_DVFS_ADR1] = 0xf0,
[PWRAP_DVFS_WDATA1] = 0xf4,
[PWRAP_DVFS_ADR2] = 0xf8,
[PWRAP_DVFS_WDATA2] = 0xfc,
[PWRAP_DVFS_ADR3] = 0x100,
[PWRAP_DVFS_WDATA3] = 0x104,
[PWRAP_DVFS_ADR4] = 0x108,
[PWRAP_DVFS_WDATA4] = 0x10c,
[PWRAP_DVFS_ADR5] = 0x110,
[PWRAP_DVFS_WDATA5] = 0x114,
[PWRAP_DVFS_ADR6] = 0x118,
[PWRAP_DVFS_WDATA6] = 0x11c,
[PWRAP_DVFS_ADR7] = 0x120,
[PWRAP_DVFS_WDATA7] = 0x124,
[PWRAP_SPMINF_STA] = 0x128,
[PWRAP_CIPHER_KEY_SEL] = 0x12c,
[PWRAP_CIPHER_IV_SEL] = 0x130,
[PWRAP_CIPHER_EN] = 0x134,
[PWRAP_CIPHER_RDY] = 0x138,
[PWRAP_CIPHER_MODE] = 0x13c,
[PWRAP_CIPHER_SWRST] = 0x140,
[PWRAP_DCM_EN] = 0x144,
[PWRAP_DCM_DBC_PRD] = 0x148,
[PWRAP_SW_RST] = 0x168,
[PWRAP_OP_TYPE] = 0x16c,
[PWRAP_MSB_FIRST] = 0x170,
};
soc: mediatek: pwrap: add pwrap driver for MT8186 SoC MT8186 are highly integrated SoC and use PMIC_MT6366 for power management. This patch adds pwrap master driver to access PMIC_MT6366. Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Link: https://lore.kernel.org/r/20220207083034.15327-2-johnson.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-07 08:30:33 +00:00
static int mt8186_regs[] = {
[PWRAP_MUX_SEL] = 0x0,
[PWRAP_WRAP_EN] = 0x4,
[PWRAP_DIO_EN] = 0x8,
[PWRAP_RDDMY] = 0x20,
[PWRAP_CSHEXT_WRITE] = 0x24,
[PWRAP_CSHEXT_READ] = 0x28,
[PWRAP_CSLEXT_WRITE] = 0x2C,
[PWRAP_CSLEXT_READ] = 0x30,
[PWRAP_EXT_CK_WRITE] = 0x34,
[PWRAP_STAUPD_CTRL] = 0x3C,
[PWRAP_STAUPD_GRPEN] = 0x40,
[PWRAP_EINT_STA0_ADR] = 0x44,
[PWRAP_EINT_STA1_ADR] = 0x48,
[PWRAP_INT_CLR] = 0xC8,
[PWRAP_INT_FLG] = 0xC4,
[PWRAP_MAN_EN] = 0x7C,
[PWRAP_MAN_CMD] = 0x80,
[PWRAP_WACS0_EN] = 0x8C,
[PWRAP_WACS1_EN] = 0x94,
[PWRAP_WACS2_EN] = 0x9C,
[PWRAP_INIT_DONE0] = 0x90,
[PWRAP_INIT_DONE1] = 0x98,
[PWRAP_INIT_DONE2] = 0xA0,
[PWRAP_INT_EN] = 0xBC,
[PWRAP_INT1_EN] = 0xCC,
[PWRAP_INT1_FLG] = 0xD4,
[PWRAP_INT1_CLR] = 0xD8,
[PWRAP_TIMER_EN] = 0xF0,
[PWRAP_WDT_UNIT] = 0xF8,
[PWRAP_WDT_SRC_EN] = 0xFC,
[PWRAP_WDT_SRC_EN_1] = 0x100,
[PWRAP_WDT_FLG] = 0x104,
[PWRAP_SPMINF_STA] = 0x1B4,
[PWRAP_DCM_EN] = 0x1EC,
[PWRAP_DCM_DBC_PRD] = 0x1F0,
[PWRAP_GPSINF_0_STA] = 0x204,
[PWRAP_GPSINF_1_STA] = 0x208,
[PWRAP_WACS0_CMD] = 0xC00,
[PWRAP_WACS0_RDATA] = 0xC04,
[PWRAP_WACS0_VLDCLR] = 0xC08,
[PWRAP_WACS1_CMD] = 0xC10,
[PWRAP_WACS1_RDATA] = 0xC14,
[PWRAP_WACS1_VLDCLR] = 0xC18,
[PWRAP_WACS2_CMD] = 0xC20,
[PWRAP_WACS2_RDATA] = 0xC24,
[PWRAP_WACS2_VLDCLR] = 0xC28,
};
soc: mediatek: PMIC wrap: add a slave specific struct This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:13 +00:00
enum pmic_type {
soc: mediatek: PMIC wrap: add mt6323 slave support Add support for MT6323 slaves. This PMIC can be found on MT2701 and MT7623 EVB. The only function that we need to touch is pwrap_init_cipher(). Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:14 +00:00
PMIC_MT6323,
soc: mediatek: pwrap: add mt6351 driver for mt6797 SoCs MT6351 is a new power management IC and it is used for mt6797 SoCs. To define mt6351_regs for pmic register mapping and pmic_mt6351 for accessing register. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-06-11 10:50:00 +00:00
PMIC_MT6351,
soc: mediatek: pwrap: add mt6357 driver for mt6765 SoCs MT6357 is a new power management IC and it is used for mt6765 SoCs. To define mt6357_regs for pmic register mapping and pmic_mt6357 for accessing register. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-04 12:31:54 +00:00
PMIC_MT6357,
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
PMIC_MT6358,
soc: mediatek: pwrap: add support for MT6359 PMIC MT6359 is a new power management IC and it is used for MT6779 SoCs. To define mt6359_regs for pmic register mapping and pmic_mt6359 for accessing register. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-02-16 06:17:23 +00:00
PMIC_MT6359,
soc: mediatek: pwrap: add pwrap_read32 for reading in 32-bit mode Some regulators such as MediaTek MT6380 has to be read in 32-bit mode. So the patch adds pwrap_read32, rename old pwrap_read into pwrap_read16 and one function pointer is introduced for increasing flexibility allowing the determination which mode is used by the pwrap slave detection through device tree. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:43 +00:00
PMIC_MT6380,
soc: mediatek: PMIC wrap: add a slave specific struct This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:13 +00:00
PMIC_MT6397,
};
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
enum pwrap_type {
soc: mediatek: PMIC wrap: add MT2701/7623 support Add the registers, callbacks and data structures required to make the wrapper work on MT2701 and MT7623. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:15 +00:00
PWRAP_MT2701,
soc: mediatek: pwrap: add pwrap driver for mt6765 SoCs mt6765 is a highly integrated SoCs, it uses mt6357 for power management. This patch adds pwrap driver to access mt6357. Pwrap of mt6765 support dynamic priority meichanism, sequence monitor and starvation mechanism to make transaction more reliable. Signed-off-by: Argus Lin <argus.lin@mediatek.com> [mb: change has_bridge to capabilities] Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-04 12:31:53 +00:00
PWRAP_MT6765,
soc: mediatek: pwrap: add pwrap driver for MT6779 SoCs MT6779 is a highly integrated SoCs, it uses PMIC_MT6359 for power management. This patch adds pwrap master driver to access PMIC_MT6359. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-02-16 06:17:22 +00:00
PWRAP_MT6779,
soc: mediatek: pwrap: add pwrap driver for mt6797 SoCs mt6797 is a highly integrated SoCs, it uses mt6351 for power management. This patch adds pwrap driver to access mt6351. Pwrap of mt6797 support dynamic priority meichanism, sequence monitor and starvation mechanism to make transaction more reliable. A big change from V4 to V5 is we remove INT1 interrupt declaration since it is only for debug purpose. The PWRAP_RDDMY, RESET and DCM can use legacy setting, it is backwards compatible. The new caps flag declaration is not needed, just remove it. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-06-11 10:49:59 +00:00
PWRAP_MT6797,
soc: mediatek: pwrap: add pwrap driver for MT6873/8192 SoCs MT6873/8192 are highly integrated SoCs and use PMIC_MT6359 for power management. This patch adds pwrap master driver to access PMIC_MT6359. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-5-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:45 +00:00
PWRAP_MT6873,
soc: mediatek: pwrap: add support for MT7622 SoC Add the registers, callbacks and data structures required to make the PMIC wrapper work on MT7622. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:48 +00:00
PWRAP_MT7622,
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
PWRAP_MT8135,
PWRAP_MT8173,
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
PWRAP_MT8183,
soc: mediatek: pwrap: add pwrap driver for MT8186 SoC MT8186 are highly integrated SoC and use PMIC_MT6366 for power management. This patch adds pwrap master driver to access PMIC_MT6366. Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Link: https://lore.kernel.org/r/20220207083034.15327-2-johnson.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-07 08:30:33 +00:00
PWRAP_MT8186,
soc: mediatek: pwrap: add pwrap driver for MT8195 SoC MT8195 are highly integrated SoC and use PMIC_MT6359 for power management. This patch adds pwrap master driver to access PMIC_MT6359. Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Link: https://lore.kernel.org/r/20210602112050.12338-3-james.lo@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-06-02 11:20:50 +00:00
PWRAP_MT8195,
soc: mediatek: pwrap: add support for MT8516 pwrap Add the code to support the pwrap IP on the MediaTek MT8516 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-03-23 21:15:53 +00:00
PWRAP_MT8516,
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
};
soc: mediatek: pwrap: add pwrap_read32 for reading in 32-bit mode Some regulators such as MediaTek MT6380 has to be read in 32-bit mode. So the patch adds pwrap_read32, rename old pwrap_read into pwrap_read16 and one function pointer is introduced for increasing flexibility allowing the determination which mode is used by the pwrap slave detection through device tree. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:43 +00:00
struct pmic_wrapper;
soc: mediatek: PMIC wrap: add a slave specific struct This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:13 +00:00
struct pwrap_slv_type {
const u32 *dew_regs;
enum pmic_type type;
soc: mediatek: pwrap: add MediaTek MT6380 as one slave of pwrap Add MediaTek MT6380 regulator becoming one of PMIC wrapper slave and also add extra new regmap_config of 32-bit mode for MT6380 since old regmap_config of 16-bit mode can't be fit into the need. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:46 +00:00
const struct regmap_config *regmap;
soc: mediatek: pwrap: refactor pwrap_init for the various PMIC types pwrap initialization is highly associated with the base SoC and the target PMICs, so slight refactorization is made here for allowing pwrap_init to run on those PMICs with different capability from the previous MediaTek PMICs and the determination for the enablement of the pwrap capability depending on PMIC type. Apart from this, the patch makes the driver more extensible especially when more PMICs join into the pwrap driver. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:45 +00:00
/* Flags indicating the capability for the target slave */
u32 caps;
soc: mediatek: pwrap: add pwrap_read32 for reading in 32-bit mode Some regulators such as MediaTek MT6380 has to be read in 32-bit mode. So the patch adds pwrap_read32, rename old pwrap_read into pwrap_read16 and one function pointer is introduced for increasing flexibility allowing the determination which mode is used by the pwrap slave detection through device tree. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:43 +00:00
/*
* pwrap operations are highly associated with the PMIC types,
* so the pointers added increases flexibility allowing determination
* which type is used by the detection through device tree.
*/
int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
soc: mediatek: pwrap: add pwrap_write32 for writing in 32-bit mode Some regulators such as MediaTek MT6380 also has to be written in 32-bit mode. So the patch adds pwrap_write32, rename old pwrap_write into pwrap_write16 and one additional function pointer is introduced for increasing flexibility allowing the determination which mode is used by the pwrap slave detection through device tree. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:44 +00:00
int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata);
soc: mediatek: PMIC wrap: add a slave specific struct This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:13 +00:00
};
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
struct pmic_wrapper {
struct device *dev;
void __iomem *base;
struct regmap *regmap;
soc: mediatek: PMIC wrap: don't duplicate the wrapper data As we add support for more devices struct pmic_wrapper_type will grow and we do not really want to start duplicating all the elements in struct pmic_wrapper. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:06 +00:00
const struct pmic_wrapper_type *master;
soc: mediatek: PMIC wrap: add a slave specific struct This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:13 +00:00
const struct pwrap_slv_type *slave;
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
struct clk *clk_spi;
struct clk *clk_wrap;
struct reset_control *rstc;
struct reset_control *rstc_bridge;
void __iomem *bridge_base;
};
soc: mediatek: PMIC wrap: add wrapper callbacks for init_reg_clock Split init_reg_clock up into SoC specific callbacks. The patch also reorders the code to avoid the need for callback function prototypes. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:07 +00:00
struct pmic_wrapper_type {
int *regs;
enum pwrap_type type;
u32 arb_en_all;
soc: mediatek: PMIC wrap: WRAP_INT_EN needs a different bitmask for MT2701/7623 MT2701 and MT7623 use a different bitmask for PWRAP_INT_EN. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:09 +00:00
u32 int_en_all;
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
u32 int1_en_all;
soc: mediatek: PMIC wrap: SPI_WRITE needs a different bitmask for MT2701/7623 Different SoCs will use different bitmask for the SPI_WRITE command. This patch defines the bitmask in the pmic_wrapper_type struct. This allows us to support new SoCs with a different bitmask to the one currently used. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:10 +00:00
u32 spi_w;
soc: mediatek: PMIC wrap: move wdt_src into the pmic_wrapper_type struct Different SoCs will use different bitmask for the wdt_src. This patch defines the bitmask in the pmic_wrapper_type struct. This allows us to support new SoCs with a different bitmask to the one currently used. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:11 +00:00
u32 wdt_src;
soc: mediatek: pwrap: use group of bits for pwrap capability Use group of bits for pwrap capability instead of elements of structure. This patch is preparing for adding mt8183 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-25 13:48:39 +00:00
/* Flags indicating the capability for the target pwrap */
u32 caps;
soc: mediatek: PMIC wrap: add wrapper callbacks for init_reg_clock Split init_reg_clock up into SoC specific callbacks. The patch also reorders the code to avoid the need for callback function prototypes. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:07 +00:00
int (*init_reg_clock)(struct pmic_wrapper *wrp);
soc: mediatek: PMIC wrap: split SoC specific init into callback This patch moves the SoC specific wrapper init code into separate callback to avoid pwrap_init() getting too large. This is done by adding a new element called init_special to pmic_wrapper_type. Each currently supported SoC gets its own version of the callback and we copy the code that was previously inside pwrap_init() to these new callbacks. Finally we point the 2 instances of pmic_wrapper_type at the 2 new functions. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:08 +00:00
int (*init_soc_specific)(struct pmic_wrapper *wrp);
soc: mediatek: PMIC wrap: add wrapper callbacks for init_reg_clock Split init_reg_clock up into SoC specific callbacks. The patch also reorders the code to avoid the need for callback function prototypes. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:07 +00:00
};
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)
{
soc: mediatek: PMIC wrap: don't duplicate the wrapper data As we add support for more devices struct pmic_wrapper_type will grow and we do not really want to start duplicating all the elements in struct pmic_wrapper. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:06 +00:00
return readl(wrp->base + wrp->master->regs[reg]);
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
}
static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg)
{
soc: mediatek: PMIC wrap: don't duplicate the wrapper data As we add support for more devices struct pmic_wrapper_type will grow and we do not really want to start duplicating all the elements in struct pmic_wrapper. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:06 +00:00
writel(val, wrp->base + wrp->master->regs[reg]);
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
}
soc: mediatek: pwrap: add arbiter capability Add arbiter capability for pwrap driver. The arbiter capability uses new design to judge the priority and latency for multi-channel. The design with arbiter support cannot change the watchdog timer. This patch is preparing for adding mt6873/8192 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-3-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:43 +00:00
static u32 pwrap_get_fsm_state(struct pmic_wrapper *wrp)
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
{
soc: mediatek: pwrap: add arbiter capability Add arbiter capability for pwrap driver. The arbiter capability uses new design to judge the priority and latency for multi-channel. The design with arbiter support cannot change the watchdog timer. This patch is preparing for adding mt6873/8192 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-3-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:43 +00:00
u32 val;
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
soc: mediatek: pwrap: add arbiter capability Add arbiter capability for pwrap driver. The arbiter capability uses new design to judge the priority and latency for multi-channel. The design with arbiter support cannot change the watchdog timer. This patch is preparing for adding mt6873/8192 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-3-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:43 +00:00
val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
return PWRAP_GET_WACS_ARB_FSM(val);
else
return PWRAP_GET_WACS_FSM(val);
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
}
soc: mediatek: pwrap: add arbiter capability Add arbiter capability for pwrap driver. The arbiter capability uses new design to judge the priority and latency for multi-channel. The design with arbiter support cannot change the watchdog timer. This patch is preparing for adding mt6873/8192 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-3-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:43 +00:00
static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
{
soc: mediatek: pwrap: add arbiter capability Add arbiter capability for pwrap driver. The arbiter capability uses new design to judge the priority and latency for multi-channel. The design with arbiter support cannot change the watchdog timer. This patch is preparing for adding mt6873/8192 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-3-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:43 +00:00
return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_IDLE;
}
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
soc: mediatek: pwrap: add arbiter capability Add arbiter capability for pwrap driver. The arbiter capability uses new design to judge the priority and latency for multi-channel. The design with arbiter support cannot change the watchdog timer. This patch is preparing for adding mt6873/8192 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-3-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:43 +00:00
static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
{
return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_WFVLDCLR;
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
}
soc: mediatek: PMIC wrap: Clear the vldclr if state machine stay on FSM_VLDCLR state. Sometimes PMIC is too busy to send data in time to cause pmic wrap timeout, because pmic wrap is waiting for FSM_VLDCLR after finishing WACS2_CMD. It just return error when issue happened, so the state machine will stay on FSM_VLDCLR state when data send back later by PMIC and timeout again in next time because pmic wrap waiting for FSM_IDLE state at the beginning of the read/write function. Clear the vldclr when timeout if state machine stay on FSM_VLDCLR. Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Tested-by: Ricky Liang <jcliang@chromium.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-01-04 12:02:52 +00:00
/*
* Timeout issue sometimes caused by the last read command
* failed because pmic wrap could not got the FSM_VLDCLR
* in time after finishing WACS2_CMD. It made state machine
* still on FSM_VLDCLR and timeout next time.
* Check the status of FSM and clear the vldclr to recovery the
* error.
*/
static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp)
{
if (pwrap_is_fsm_vldclr(wrp))
pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
}
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp)
{
return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0;
}
static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp)
{
u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) &&
(val & PWRAP_STATE_SYNC_IDLE0);
}
static int pwrap_wait_for_state(struct pmic_wrapper *wrp,
bool (*fp)(struct pmic_wrapper *))
{
unsigned long timeout;
soc: mediatek: PMIC wrap: Extend the waiting time to 10ms. Read data fails sometimes because of a timeout that PMIC cannot transfer data to PMIC wrap on time, extend the waiting time to 10ms to reduce the failed rate. Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-07-13 03:34:28 +00:00
timeout = jiffies + usecs_to_jiffies(10000);
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
do {
if (time_after(jiffies, timeout))
return fp(wrp) ? 0 : -ETIMEDOUT;
if (fp(wrp))
return 0;
} while (1);
}
soc: mediatek: pwrap: add pwrap_read32 for reading in 32-bit mode Some regulators such as MediaTek MT6380 has to be read in 32-bit mode. So the patch adds pwrap_read32, rename old pwrap_read into pwrap_read16 and one function pointer is introduced for increasing flexibility allowing the determination which mode is used by the pwrap slave detection through device tree. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:43 +00:00
static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
{
int ret;
soc: mediatek: pwrap: add arbiter capability Add arbiter capability for pwrap driver. The arbiter capability uses new design to judge the priority and latency for multi-channel. The design with arbiter support cannot change the watchdog timer. This patch is preparing for adding mt6873/8192 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-3-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:43 +00:00
u32 val;
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
soc: mediatek: PMIC wrap: Clear the vldclr if state machine stay on FSM_VLDCLR state. Sometimes PMIC is too busy to send data in time to cause pmic wrap timeout, because pmic wrap is waiting for FSM_VLDCLR after finishing WACS2_CMD. It just return error when issue happened, so the state machine will stay on FSM_VLDCLR state when data send back later by PMIC and timeout again in next time because pmic wrap waiting for FSM_IDLE state at the beginning of the read/write function. Clear the vldclr when timeout if state machine stay on FSM_VLDCLR. Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Tested-by: Ricky Liang <jcliang@chromium.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-01-04 12:02:52 +00:00
if (ret) {
pwrap_leave_fsm_vldclr(wrp);
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
return ret;
soc: mediatek: PMIC wrap: Clear the vldclr if state machine stay on FSM_VLDCLR state. Sometimes PMIC is too busy to send data in time to cause pmic wrap timeout, because pmic wrap is waiting for FSM_VLDCLR after finishing WACS2_CMD. It just return error when issue happened, so the state machine will stay on FSM_VLDCLR state when data send back later by PMIC and timeout again in next time because pmic wrap waiting for FSM_IDLE state at the beginning of the read/write function. Clear the vldclr when timeout if state machine stay on FSM_VLDCLR. Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Tested-by: Ricky Liang <jcliang@chromium.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-01-04 12:02:52 +00:00
}
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
soc: mediatek: pwrap: add arbiter capability Add arbiter capability for pwrap driver. The arbiter capability uses new design to judge the priority and latency for multi-channel. The design with arbiter support cannot change the watchdog timer. This patch is preparing for adding mt6873/8192 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-3-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:43 +00:00
if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
val = adr;
else
val = (adr >> 1) << 16;
pwrap_writel(wrp, val, PWRAP_WACS2_CMD);
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
if (ret)
return ret;
soc: mediatek: pwrap: add arbiter capability Add arbiter capability for pwrap driver. The arbiter capability uses new design to judge the priority and latency for multi-channel. The design with arbiter support cannot change the watchdog timer. This patch is preparing for adding mt6873/8192 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-3-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:43 +00:00
if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
val = pwrap_readl(wrp, PWRAP_SWINF_2_RDATA_31_0);
else
val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
*rdata = PWRAP_GET_WACS_RDATA(val);
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
soc: mediatek: PMIC wrap: Fix register state machine handling When the PMIC wrapper state machine has read a register it goes into the "wait for valid clear" (vldclr) state. The state machine stays in this state until the VLDCLR bit is written to. We should write this bit after reading a register because the SCPSYS won't let the system go into suspend as long as the state machine waits for valid clear. Since now we never leave the state machine in vldclr state we no longer have to check for this state on pwrap_read/pwrap_write entry and can remove the corresponding code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-05-26 09:37:44 +00:00
pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
return 0;
}
soc: mediatek: pwrap: add pwrap_read32 for reading in 32-bit mode Some regulators such as MediaTek MT6380 has to be read in 32-bit mode. So the patch adds pwrap_read32, rename old pwrap_read into pwrap_read16 and one function pointer is introduced for increasing flexibility allowing the determination which mode is used by the pwrap slave detection through device tree. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:43 +00:00
static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
{
int ret, msb;
*rdata = 0;
for (msb = 0; msb < 2; msb++) {
ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
if (ret) {
pwrap_leave_fsm_vldclr(wrp);
return ret;
}
pwrap_writel(wrp, ((msb << 30) | (adr << 16)),
PWRAP_WACS2_CMD);
ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
if (ret)
return ret;
*rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp,
PWRAP_WACS2_RDATA)) << (16 * msb));
pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
}
return 0;
}
static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
{
return wrp->slave->pwrap_read(wrp, adr, rdata);
}
soc: mediatek: pwrap: add pwrap_write32 for writing in 32-bit mode Some regulators such as MediaTek MT6380 also has to be written in 32-bit mode. So the patch adds pwrap_write32, rename old pwrap_write into pwrap_write16 and one additional function pointer is introduced for increasing flexibility allowing the determination which mode is used by the pwrap slave detection through device tree. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:44 +00:00
static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
{
int ret;
ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
if (ret) {
pwrap_leave_fsm_vldclr(wrp);
return ret;
}
soc: mediatek: pwrap: add arbiter capability Add arbiter capability for pwrap driver. The arbiter capability uses new design to judge the priority and latency for multi-channel. The design with arbiter support cannot change the watchdog timer. This patch is preparing for adding mt6873/8192 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-3-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:43 +00:00
if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) {
pwrap_writel(wrp, wdata, PWRAP_SWINF_2_WDATA_31_0);
pwrap_writel(wrp, BIT(29) | adr, PWRAP_WACS2_CMD);
} else {
pwrap_writel(wrp, BIT(31) | ((adr >> 1) << 16) | wdata,
PWRAP_WACS2_CMD);
}
soc: mediatek: pwrap: add pwrap_write32 for writing in 32-bit mode Some regulators such as MediaTek MT6380 also has to be written in 32-bit mode. So the patch adds pwrap_write32, rename old pwrap_write into pwrap_write16 and one additional function pointer is introduced for increasing flexibility allowing the determination which mode is used by the pwrap slave detection through device tree. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:44 +00:00
return 0;
}
static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
{
int ret, msb, rdata;
for (msb = 0; msb < 2; msb++) {
ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
if (ret) {
pwrap_leave_fsm_vldclr(wrp);
return ret;
}
pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) |
((wdata >> (msb * 16)) & 0xffff),
PWRAP_WACS2_CMD);
/*
* The pwrap_read operation is the requirement of hardware used
* for the synchronization between two successive 16-bit
* pwrap_writel operations composing one 32-bit bus writing.
* Otherwise, we'll find the result fails on the lower 16-bit
* pwrap writing.
*/
if (!msb)
pwrap_read(wrp, adr, &rdata);
}
return 0;
}
static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
{
return wrp->slave->pwrap_write(wrp, adr, wdata);
}
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
{
return pwrap_read(context, adr, rdata);
}
static int pwrap_regmap_write(void *context, u32 adr, u32 wdata)
{
return pwrap_write(context, adr, wdata);
}
static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
{
int ret, i;
pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN);
pwrap_writel(wrp, 0, PWRAP_WRAP_EN);
pwrap_writel(wrp, 1, PWRAP_MUX_SEL);
pwrap_writel(wrp, 1, PWRAP_MAN_EN);
pwrap_writel(wrp, 0, PWRAP_DIO_EN);
soc: mediatek: PMIC wrap: SPI_WRITE needs a different bitmask for MT2701/7623 Different SoCs will use different bitmask for the SPI_WRITE command. This patch defines the bitmask in the pmic_wrapper_type struct. This allows us to support new SoCs with a different bitmask to the one currently used. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:10 +00:00
pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL,
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
PWRAP_MAN_CMD);
soc: mediatek: PMIC wrap: SPI_WRITE needs a different bitmask for MT2701/7623 Different SoCs will use different bitmask for the SPI_WRITE command. This patch defines the bitmask in the pmic_wrapper_type struct. This allows us to support new SoCs with a different bitmask to the one currently used. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:10 +00:00
pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
PWRAP_MAN_CMD);
soc: mediatek: PMIC wrap: SPI_WRITE needs a different bitmask for MT2701/7623 Different SoCs will use different bitmask for the SPI_WRITE command. This patch defines the bitmask in the pmic_wrapper_type struct. This allows us to support new SoCs with a different bitmask to the one currently used. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:10 +00:00
pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH,
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
PWRAP_MAN_CMD);
for (i = 0; i < 4; i++)
soc: mediatek: PMIC wrap: SPI_WRITE needs a different bitmask for MT2701/7623 Different SoCs will use different bitmask for the SPI_WRITE command. This patch defines the bitmask in the pmic_wrapper_type struct. This allows us to support new SoCs with a different bitmask to the one currently used. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:10 +00:00
pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
PWRAP_MAN_CMD);
ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle);
if (ret) {
dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
return ret;
}
pwrap_writel(wrp, 0, PWRAP_MAN_EN);
pwrap_writel(wrp, 0, PWRAP_MUX_SEL);
return 0;
}
/*
* pwrap_init_sidly - configure serial input delay
*
* This configures the serial input delay. We can configure 0, 2, 4 or 6ns
* delay. Do a read test with all possible values and chose the best delay.
*/
static int pwrap_init_sidly(struct pmic_wrapper *wrp)
{
u32 rdata;
u32 i;
u32 pass = 0;
signed char dly[16] = {
-1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1
};
for (i = 0; i < 4; i++) {
pwrap_writel(wrp, i, PWRAP_SIDLY);
soc: mediatek: PMIC wrap: add a slave specific struct This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:13 +00:00
pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST],
&rdata);
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
if (rdata == PWRAP_DEW_READ_TEST_VAL) {
dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
pass |= 1 << i;
}
}
if (dly[pass] < 0) {
dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n",
pass);
return -EIO;
}
pwrap_writel(wrp, dly[pass], PWRAP_SIDLY);
return 0;
}
soc: mediatek: pwrap: refactor pwrap_init for the various PMIC types pwrap initialization is highly associated with the base SoC and the target PMICs, so slight refactorization is made here for allowing pwrap_init to run on those PMICs with different capability from the previous MediaTek PMICs and the determination for the enablement of the pwrap capability depending on PMIC type. Apart from this, the patch makes the driver more extensible especially when more PMICs join into the pwrap driver. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:45 +00:00
static int pwrap_init_dual_io(struct pmic_wrapper *wrp)
{
int ret;
u32 rdata;
/* Enable dual IO mode */
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
/* Check IDLE & INIT_DONE in advance */
ret = pwrap_wait_for_state(wrp,
pwrap_is_fsm_idle_and_sync_idle);
if (ret) {
dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
return ret;
}
pwrap_writel(wrp, 1, PWRAP_DIO_EN);
/* Read Test */
pwrap_read(wrp,
wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
if (rdata != PWRAP_DEW_READ_TEST_VAL) {
dev_err(wrp->dev,
"Read failed on DIO mode: 0x%04x!=0x%04x\n",
PWRAP_DEW_READ_TEST_VAL, rdata);
return -EFAULT;
}
return 0;
}
soc: mediatek: pwrap: add common way for setup CS timing extenstion Multiple platforms would always use their own way handling CS timing extension on the bus which leads to a little bit code duplication. Therefore, the patch groups the similar logic to handle CS timing extension into the common function which allows the following SoCs have more reusability for configing CS timing. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:47 +00:00
/*
* pwrap_init_chip_select_ext is used to configure CS extension time for each
* phase during data transactions on the pwrap bus.
*/
static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
u8 hext_read, u8 lext_start,
u8 lext_end)
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
{
soc: mediatek: pwrap: add common way for setup CS timing extenstion Multiple platforms would always use their own way handling CS timing extension on the bus which leads to a little bit code duplication. Therefore, the patch groups the similar logic to handle CS timing extension into the common function which allows the following SoCs have more reusability for configing CS timing. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:47 +00:00
/*
* After finishing a write and read transaction, extends CS high time
* to be at least xT of BUS CLK as hext_write and hext_read specifies
* respectively.
*/
pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE);
pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ);
soc: mediatek: PMIC wrap: add wrapper callbacks for init_reg_clock Split init_reg_clock up into SoC specific callbacks. The patch also reorders the code to avoid the need for callback function prototypes. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:07 +00:00
soc: mediatek: pwrap: add common way for setup CS timing extenstion Multiple platforms would always use their own way handling CS timing extension on the bus which leads to a little bit code duplication. Therefore, the patch groups the similar logic to handle CS timing extension into the common function which allows the following SoCs have more reusability for configing CS timing. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:47 +00:00
/*
* Extends CS low time after CSL and before CSH command to be at
* least xT of BUS CLK as lext_start and lext_end specifies
* respectively.
*/
pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START);
pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END);
soc: mediatek: PMIC wrap: add wrapper callbacks for init_reg_clock Split init_reg_clock up into SoC specific callbacks. The patch also reorders the code to avoid the need for callback function prototypes. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:07 +00:00
}
soc: mediatek: pwrap: add common way for setup CS timing extenstion Multiple platforms would always use their own way handling CS timing extension on the bus which leads to a little bit code duplication. Therefore, the patch groups the similar logic to handle CS timing extension into the common function which allows the following SoCs have more reusability for configing CS timing. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:47 +00:00
static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
soc: mediatek: PMIC wrap: add wrapper callbacks for init_reg_clock Split init_reg_clock up into SoC specific callbacks. The patch also reorders the code to avoid the need for callback function prototypes. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:07 +00:00
{
soc: mediatek: pwrap: add common way for setup CS timing extenstion Multiple platforms would always use their own way handling CS timing extension on the bus which leads to a little bit code duplication. Therefore, the patch groups the similar logic to handle CS timing extension into the common function which allows the following SoCs have more reusability for configing CS timing. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:47 +00:00
switch (wrp->master->type) {
case PWRAP_MT8173:
pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);
break;
case PWRAP_MT8135:
pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0);
break;
default:
break;
}
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
return 0;
}
soc: mediatek: PMIC wrap: add MT2701/7623 support Add the registers, callbacks and data structures required to make the wrapper work on MT2701 and MT7623. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:15 +00:00
static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp)
{
switch (wrp->slave->type) {
case PMIC_MT6397:
pwrap_writel(wrp, 0xc, PWRAP_RDDMY);
soc: mediatek: pwrap: add common way for setup CS timing extenstion Multiple platforms would always use their own way handling CS timing extension on the bus which leads to a little bit code duplication. Therefore, the patch groups the similar logic to handle CS timing extension into the common function which allows the following SoCs have more reusability for configing CS timing. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:47 +00:00
pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2);
soc: mediatek: PMIC wrap: add MT2701/7623 support Add the registers, callbacks and data structures required to make the wrapper work on MT2701 and MT7623. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:15 +00:00
break;
case PMIC_MT6323:
pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO],
0x8);
soc: mediatek: pwrap: add common way for setup CS timing extenstion Multiple platforms would always use their own way handling CS timing extension on the bus which leads to a little bit code duplication. Therefore, the patch groups the similar logic to handle CS timing extension into the common function which allows the following SoCs have more reusability for configing CS timing. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:47 +00:00
pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2);
soc: mediatek: PMIC wrap: add MT2701/7623 support Add the registers, callbacks and data structures required to make the wrapper work on MT2701 and MT7623. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:15 +00:00
break;
soc: mediatek: pwrap: add pwrap_read32 for reading in 32-bit mode Some regulators such as MediaTek MT6380 has to be read in 32-bit mode. So the patch adds pwrap_read32, rename old pwrap_read into pwrap_read16 and one function pointer is introduced for increasing flexibility allowing the determination which mode is used by the pwrap slave detection through device tree. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:43 +00:00
default:
break;
soc: mediatek: PMIC wrap: add MT2701/7623 support Add the registers, callbacks and data structures required to make the wrapper work on MT2701 and MT7623. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:15 +00:00
}
return 0;
}
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
{
return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
}
static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
{
u32 rdata;
int ret;
soc: mediatek: PMIC wrap: add a slave specific struct This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:13 +00:00
ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY],
&rdata);
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
if (ret)
soc: mediatek: pwrap: use true and false for boolean values Return statements in functions returning bool should use true or false instead of an integer value. This issue was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Acked-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-08-05 01:02:01 +00:00
return false;
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
return rdata == 1;
}
static int pwrap_init_cipher(struct pmic_wrapper *wrp)
{
int ret;
soc: mediatek: pwrap: Zero initialize rdata in pwrap_init_cipher When building with -Wsometimes-uninitialized, Clang warns: drivers/soc/mediatek/mtk-pmic-wrap.c:1358:6: error: variable 'rdata' is used uninitialized whenever '||' condition is true [-Werror,-Wsometimes-uninitialized] If pwrap_write returns non-zero, pwrap_read will not be called to initialize rdata, meaning that we will use some random uninitialized stack value in our print statement. Zero initialize rdata in case this happens. Link: https://github.com/ClangBuiltLinux/linux/issues/401 Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-03-07 22:56:51 +00:00
u32 rdata = 0;
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST);
pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST);
pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);
pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);
soc: mediatek: PMIC wrap: remove pwrap_is_mt8135() and pwrap_is_mt8173() With more SoCs being added the list of helper functions like these would grow. To mitigate this problem we remove the existing helpers and change the code to test against the pmic type stored inside the pmic specific datastructure that our context structure points at. There is one usage of pwrap_is_mt8135() that is ambiguous as the test should not be dependent on mt8135, but rather on the existence of a bridge. Add a new element to pmic_wrapper_type to indicate if a bridge is present and use this where appropriate. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:12 +00:00
switch (wrp->master->type) {
case PWRAP_MT8135:
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
soc: mediatek: PMIC wrap: remove pwrap_is_mt8135() and pwrap_is_mt8173() With more SoCs being added the list of helper functions like these would grow. To mitigate this problem we remove the existing helpers and change the code to test against the pmic type stored inside the pmic specific datastructure that our context structure points at. There is one usage of pwrap_is_mt8135() that is ambiguous as the test should not be dependent on mt8135, but rather on the existence of a bridge. Add a new element to pmic_wrapper_type to indicate if a bridge is present and use this where appropriate. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:12 +00:00
break;
soc: mediatek: PMIC wrap: add MT2701/7623 support Add the registers, callbacks and data structures required to make the wrapper work on MT2701 and MT7623. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:15 +00:00
case PWRAP_MT2701:
soc: mediatek: pwrap: add pwrap driver for mt6765 SoCs mt6765 is a highly integrated SoCs, it uses mt6357 for power management. This patch adds pwrap driver to access mt6357. Pwrap of mt6765 support dynamic priority meichanism, sequence monitor and starvation mechanism to make transaction more reliable. Signed-off-by: Argus Lin <argus.lin@mediatek.com> [mb: change has_bridge to capabilities] Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-04 12:31:53 +00:00
case PWRAP_MT6765:
soc: mediatek: pwrap: add pwrap driver for MT6779 SoCs MT6779 is a highly integrated SoCs, it uses PMIC_MT6359 for power management. This patch adds pwrap master driver to access PMIC_MT6359. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-02-16 06:17:22 +00:00
case PWRAP_MT6779:
soc: mediatek: pwrap: add pwrap driver for mt6797 SoCs mt6797 is a highly integrated SoCs, it uses mt6351 for power management. This patch adds pwrap driver to access mt6351. Pwrap of mt6797 support dynamic priority meichanism, sequence monitor and starvation mechanism to make transaction more reliable. A big change from V4 to V5 is we remove INT1 interrupt declaration since it is only for debug purpose. The PWRAP_RDDMY, RESET and DCM can use legacy setting, it is backwards compatible. The new caps flag declaration is not needed, just remove it. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-06-11 10:49:59 +00:00
case PWRAP_MT6797:
soc: mediatek: PMIC wrap: remove pwrap_is_mt8135() and pwrap_is_mt8173() With more SoCs being added the list of helper functions like these would grow. To mitigate this problem we remove the existing helpers and change the code to test against the pmic type stored inside the pmic specific datastructure that our context structure points at. There is one usage of pwrap_is_mt8135() that is ambiguous as the test should not be dependent on mt8135, but rather on the existence of a bridge. Add a new element to pmic_wrapper_type to indicate if a bridge is present and use this where appropriate. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:12 +00:00
case PWRAP_MT8173:
soc: mediatek: pwrap: add pwrap driver for MT8186 SoC MT8186 are highly integrated SoC and use PMIC_MT6366 for power management. This patch adds pwrap master driver to access PMIC_MT6366. Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Link: https://lore.kernel.org/r/20220207083034.15327-2-johnson.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-07 08:30:33 +00:00
case PWRAP_MT8186:
soc: mediatek: pwrap: add support for MT8516 pwrap Add the code to support the pwrap IP on the MediaTek MT8516 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-03-23 21:15:53 +00:00
case PWRAP_MT8516:
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
soc: mediatek: PMIC wrap: remove pwrap_is_mt8135() and pwrap_is_mt8173() With more SoCs being added the list of helper functions like these would grow. To mitigate this problem we remove the existing helpers and change the code to test against the pmic type stored inside the pmic specific datastructure that our context structure points at. There is one usage of pwrap_is_mt8135() that is ambiguous as the test should not be dependent on mt8135, but rather on the existence of a bridge. Add a new element to pmic_wrapper_type to indicate if a bridge is present and use this where appropriate. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:12 +00:00
break;
soc: mediatek: pwrap: add support for MT7622 SoC Add the registers, callbacks and data structures required to make the PMIC wrapper work on MT7622. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:48 +00:00
case PWRAP_MT7622:
pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
break;
soc: mediatek: pwrap: add pwrap driver for MT6873/8192 SoCs MT6873/8192 are highly integrated SoCs and use PMIC_MT6359 for power management. This patch adds pwrap master driver to access PMIC_MT6359. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-5-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:45 +00:00
case PWRAP_MT6873:
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
case PWRAP_MT8183:
soc: mediatek: pwrap: add pwrap driver for MT8195 SoC MT8195 are highly integrated SoC and use PMIC_MT6359 for power management. This patch adds pwrap master driver to access PMIC_MT6359. Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Link: https://lore.kernel.org/r/20210602112050.12338-3-james.lo@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-06-02 11:20:50 +00:00
case PWRAP_MT8195:
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
break;
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
}
/* Config cipher mode @PMIC */
soc: mediatek: PMIC wrap: add a slave specific struct This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:13 +00:00
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1);
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
soc: mediatek: PMIC wrap: add mt6323 slave support Add support for MT6323 slaves. This PMIC can be found on MT2701 and MT7623 EVB. The only function that we need to touch is pwrap_init_cipher(). Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:14 +00:00
switch (wrp->slave->type) {
case PMIC_MT6397:
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD],
0x1);
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START],
0x1);
break;
case PMIC_MT6323:
soc: mediatek: pwrap: add mt6351 driver for mt6797 SoCs MT6351 is a new power management IC and it is used for mt6797 SoCs. To define mt6351_regs for pmic register mapping and pmic_mt6351 for accessing register. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-06-11 10:50:00 +00:00
case PMIC_MT6351:
soc: mediatek: pwrap: add mt6357 driver for mt6765 SoCs MT6357 is a new power management IC and it is used for mt6765 SoCs. To define mt6357_regs for pmic register mapping and pmic_mt6357 for accessing register. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-04 12:31:54 +00:00
case PMIC_MT6357:
soc: mediatek: PMIC wrap: add mt6323 slave support Add support for MT6323 slaves. This PMIC can be found on MT2701 and MT7623 EVB. The only function that we need to touch is pwrap_init_cipher(). Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:14 +00:00
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
0x1);
break;
soc: mediatek: pwrap: add pwrap_read32 for reading in 32-bit mode Some regulators such as MediaTek MT6380 has to be read in 32-bit mode. So the patch adds pwrap_read32, rename old pwrap_read into pwrap_read16 and one function pointer is introduced for increasing flexibility allowing the determination which mode is used by the pwrap slave detection through device tree. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:43 +00:00
default:
break;
soc: mediatek: PMIC wrap: add mt6323 slave support Add support for MT6323 slaves. This PMIC can be found on MT2701 and MT7623 EVB. The only function that we need to touch is pwrap_init_cipher(). Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:14 +00:00
}
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
/* wait for cipher data ready@AP */
ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
if (ret) {
dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret);
return ret;
}
/* wait for cipher data ready@PMIC */
ret = pwrap_wait_for_state(wrp, pwrap_is_pmic_cipher_ready);
if (ret) {
soc: mediatek: pwrap: fixup warnings from coding style fixup those warnings such as lines over 80 words and parenthesis alignment which would be complained by checkpatch.pl. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-09-21 08:26:57 +00:00
dev_err(wrp->dev,
"timeout waiting for cipher data ready@PMIC\n");
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
return ret;
}
/* wait for cipher mode idle */
soc: mediatek: PMIC wrap: add a slave specific struct This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:13 +00:00
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1);
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
if (ret) {
dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
return ret;
}
pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
/* Write Test */
soc: mediatek: PMIC wrap: add a slave specific struct This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:13 +00:00
if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
PWRAP_DEW_WRITE_TEST_VAL) ||
pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
&rdata) ||
(rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
return -EFAULT;
}
return 0;
}
soc: mediatek: pwrap: refactor pwrap_init for the various PMIC types pwrap initialization is highly associated with the base SoC and the target PMICs, so slight refactorization is made here for allowing pwrap_init to run on those PMICs with different capability from the previous MediaTek PMICs and the determination for the enablement of the pwrap capability depending on PMIC type. Apart from this, the patch makes the driver more extensible especially when more PMICs join into the pwrap driver. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:45 +00:00
static int pwrap_init_security(struct pmic_wrapper *wrp)
{
int ret;
/* Enable encryption */
ret = pwrap_init_cipher(wrp);
if (ret)
return ret;
/* Signature checking - using CRC */
if (pwrap_write(wrp,
wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
return -EFAULT;
pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
PWRAP_SIG_ADR);
pwrap_writel(wrp,
wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
return 0;
}
soc: mediatek: PMIC wrap: split SoC specific init into callback This patch moves the SoC specific wrapper init code into separate callback to avoid pwrap_init() getting too large. This is done by adding a new element called init_special to pmic_wrapper_type. Each currently supported SoC gets its own version of the callback and we copy the code that was previously inside pwrap_init() to these new callbacks. Finally we point the 2 instances of pmic_wrapper_type at the 2 new functions. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:08 +00:00
static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
{
/* enable pwrap events and pwrap bridge in AP side */
pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN);
pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN);
writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN);
writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN);
writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN);
writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT);
writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN);
writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN);
writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
/* enable PMIC event out and sources */
soc: mediatek: PMIC wrap: add a slave specific struct This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:13 +00:00
if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
0x1) ||
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
0xffff)) {
soc: mediatek: PMIC wrap: split SoC specific init into callback This patch moves the SoC specific wrapper init code into separate callback to avoid pwrap_init() getting too large. This is done by adding a new element called init_special to pmic_wrapper_type. Each currently supported SoC gets its own version of the callback and we copy the code that was previously inside pwrap_init() to these new callbacks. Finally we point the 2 instances of pmic_wrapper_type at the 2 new functions. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:08 +00:00
dev_err(wrp->dev, "enable dewrap fail\n");
return -EFAULT;
}
return 0;
}
static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
{
/* PMIC_DEWRAP enables */
soc: mediatek: PMIC wrap: add a slave specific struct This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:13 +00:00
if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
0x1) ||
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
0xffff)) {
soc: mediatek: PMIC wrap: split SoC specific init into callback This patch moves the SoC specific wrapper init code into separate callback to avoid pwrap_init() getting too large. This is done by adding a new element called init_special to pmic_wrapper_type. Each currently supported SoC gets its own version of the callback and we copy the code that was previously inside pwrap_init() to these new callbacks. Finally we point the 2 instances of pmic_wrapper_type at the 2 new functions. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:08 +00:00
dev_err(wrp->dev, "enable dewrap fail\n");
return -EFAULT;
}
return 0;
}
soc: mediatek: PMIC wrap: add MT2701/7623 support Add the registers, callbacks and data structures required to make the wrapper work on MT2701 and MT7623. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:15 +00:00
static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
{
/* GPS_INTF initialization */
switch (wrp->slave->type) {
case PMIC_MT6323:
pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR);
pwrap_writel(wrp, 0x8000, PWRAP_PWRAP_ADC_CMD);
pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR);
pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1);
pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2);
break;
default:
break;
}
return 0;
}
soc: mediatek: pwrap: add support for MT7622 SoC Add the registers, callbacks and data structures required to make the PMIC wrapper work on MT7622. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:48 +00:00
static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
{
pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);
/* enable 2wire SPI master */
pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL);
return 0;
}
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
static int pwrap_mt8183_init_soc_specific(struct pmic_wrapper *wrp)
{
pwrap_writel(wrp, 0xf5, PWRAP_STAUPD_GRPEN);
pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1);
pwrap_writel(wrp, 1, PWRAP_CRC_EN);
pwrap_writel(wrp, 0x416, PWRAP_SIG_ADR);
pwrap_writel(wrp, 0x42e, PWRAP_EINT_STA0_ADR);
pwrap_writel(wrp, 1, PWRAP_WACS_P2P_EN);
pwrap_writel(wrp, 1, PWRAP_WACS_MD32_EN);
pwrap_writel(wrp, 1, PWRAP_INIT_DONE_P2P);
pwrap_writel(wrp, 1, PWRAP_INIT_DONE_MD32);
return 0;
}
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
static int pwrap_init(struct pmic_wrapper *wrp)
{
int ret;
soc: mediatek: pwrap: add missing check on rstc The variable rstc is set only when the SoC PWRAP have the PWRAP_CAP_RESET capability. Check whether rstc is set before using it to avoid errors. Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-03-23 21:15:52 +00:00
if (wrp->rstc)
reset_control_reset(wrp->rstc);
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
if (wrp->rstc_bridge)
reset_control_reset(wrp->rstc_bridge);
soc: mediatek: PMIC wrap: remove pwrap_is_mt8135() and pwrap_is_mt8173() With more SoCs being added the list of helper functions like these would grow. To mitigate this problem we remove the existing helpers and change the code to test against the pmic type stored inside the pmic specific datastructure that our context structure points at. There is one usage of pwrap_is_mt8135() that is ambiguous as the test should not be dependent on mt8135, but rather on the existence of a bridge. Add a new element to pmic_wrapper_type to indicate if a bridge is present and use this where appropriate. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:12 +00:00
if (wrp->master->type == PWRAP_MT8173) {
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
/* Enable DCM */
pwrap_writel(wrp, 3, PWRAP_DCM_EN);
pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
}
soc: mediatek: pwrap: refactor pwrap_init for the various PMIC types pwrap initialization is highly associated with the base SoC and the target PMICs, so slight refactorization is made here for allowing pwrap_init to run on those PMICs with different capability from the previous MediaTek PMICs and the determination for the enablement of the pwrap capability depending on PMIC type. Apart from this, the patch makes the driver more extensible especially when more PMICs join into the pwrap driver. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:45 +00:00
if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
/* Reset SPI slave */
ret = pwrap_reset_spislave(wrp);
if (ret)
return ret;
}
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
soc: mediatek: PMIC wrap: don't duplicate the wrapper data As we add support for more devices struct pmic_wrapper_type will grow and we do not really want to start duplicating all the elements in struct pmic_wrapper. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:06 +00:00
pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
soc: mediatek: PMIC wrap: add wrapper callbacks for init_reg_clock Split init_reg_clock up into SoC specific callbacks. The patch also reorders the code to avoid the need for callback function prototypes. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:07 +00:00
ret = wrp->master->init_reg_clock(wrp);
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
if (ret)
return ret;
soc: mediatek: pwrap: refactor pwrap_init for the various PMIC types pwrap initialization is highly associated with the base SoC and the target PMICs, so slight refactorization is made here for allowing pwrap_init to run on those PMICs with different capability from the previous MediaTek PMICs and the determination for the enablement of the pwrap capability depending on PMIC type. Apart from this, the patch makes the driver more extensible especially when more PMICs join into the pwrap driver. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:45 +00:00
if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
/* Setup serial input delay */
ret = pwrap_init_sidly(wrp);
if (ret)
return ret;
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
}
soc: mediatek: pwrap: refactor pwrap_init for the various PMIC types pwrap initialization is highly associated with the base SoC and the target PMICs, so slight refactorization is made here for allowing pwrap_init to run on those PMICs with different capability from the previous MediaTek PMICs and the determination for the enablement of the pwrap capability depending on PMIC type. Apart from this, the patch makes the driver more extensible especially when more PMICs join into the pwrap driver. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:45 +00:00
if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) {
/* Enable dual I/O mode */
ret = pwrap_init_dual_io(wrp);
if (ret)
return ret;
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
}
soc: mediatek: pwrap: refactor pwrap_init for the various PMIC types pwrap initialization is highly associated with the base SoC and the target PMICs, so slight refactorization is made here for allowing pwrap_init to run on those PMICs with different capability from the previous MediaTek PMICs and the determination for the enablement of the pwrap capability depending on PMIC type. Apart from this, the patch makes the driver more extensible especially when more PMICs join into the pwrap driver. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:45 +00:00
if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) {
/* Enable security on bus */
ret = pwrap_init_security(wrp);
if (ret)
return ret;
}
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
soc: mediatek: PMIC wrap: remove pwrap_is_mt8135() and pwrap_is_mt8173() With more SoCs being added the list of helper functions like these would grow. To mitigate this problem we remove the existing helpers and change the code to test against the pmic type stored inside the pmic specific datastructure that our context structure points at. There is one usage of pwrap_is_mt8135() that is ambiguous as the test should not be dependent on mt8135, but rather on the existence of a bridge. Add a new element to pmic_wrapper_type to indicate if a bridge is present and use this where appropriate. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:12 +00:00
if (wrp->master->type == PWRAP_MT8135)
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);
pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN);
pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN);
pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);
pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);
soc: mediatek: PMIC wrap: split SoC specific init into callback This patch moves the SoC specific wrapper init code into separate callback to avoid pwrap_init() getting too large. This is done by adding a new element called init_special to pmic_wrapper_type. Each currently supported SoC gets its own version of the callback and we copy the code that was previously inside pwrap_init() to these new callbacks. Finally we point the 2 instances of pmic_wrapper_type at the 2 new functions. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:08 +00:00
if (wrp->master->init_soc_specific) {
ret = wrp->master->init_soc_specific(wrp);
if (ret)
return ret;
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
}
/* Setup the init done registers */
pwrap_writel(wrp, 1, PWRAP_INIT_DONE2);
pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
soc: mediatek: pwrap: use group of bits for pwrap capability Use group of bits for pwrap capability instead of elements of structure. This patch is preparing for adding mt8183 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-25 13:48:39 +00:00
if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
}
return 0;
}
static irqreturn_t pwrap_interrupt(int irqno, void *dev_id)
{
u32 rdata;
struct pmic_wrapper *wrp = dev_id;
rdata = pwrap_readl(wrp, PWRAP_INT_FLG);
dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata);
pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR);
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) {
rdata = pwrap_readl(wrp, PWRAP_INT1_FLG);
dev_err(wrp->dev, "unexpected interrupt int1=0x%x\n", rdata);
pwrap_writel(wrp, 0xffffffff, PWRAP_INT1_CLR);
}
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
return IRQ_HANDLED;
}
soc: mediatek: pwrap: add MediaTek MT6380 as one slave of pwrap Add MediaTek MT6380 regulator becoming one of PMIC wrapper slave and also add extra new regmap_config of 32-bit mode for MT6380 since old regmap_config of 16-bit mode can't be fit into the need. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:46 +00:00
static const struct regmap_config pwrap_regmap_config16 = {
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
.reg_bits = 16,
.val_bits = 16,
.reg_stride = 2,
.reg_read = pwrap_regmap_read,
.reg_write = pwrap_regmap_write,
.max_register = 0xffff,
};
soc: mediatek: pwrap: add MediaTek MT6380 as one slave of pwrap Add MediaTek MT6380 regulator becoming one of PMIC wrapper slave and also add extra new regmap_config of 32-bit mode for MT6380 since old regmap_config of 16-bit mode can't be fit into the need. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:46 +00:00
static const struct regmap_config pwrap_regmap_config32 = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.reg_read = pwrap_regmap_read,
.reg_write = pwrap_regmap_write,
.max_register = 0xffff,
};
soc: mediatek: PMIC wrap: add mt6323 slave support Add support for MT6323 slaves. This PMIC can be found on MT2701 and MT7623 EVB. The only function that we need to touch is pwrap_init_cipher(). Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:14 +00:00
static const struct pwrap_slv_type pmic_mt6323 = {
.dew_regs = mt6323_regs,
.type = PMIC_MT6323,
soc: mediatek: pwrap: add MediaTek MT6380 as one slave of pwrap Add MediaTek MT6380 regulator becoming one of PMIC wrapper slave and also add extra new regmap_config of 32-bit mode for MT6380 since old regmap_config of 16-bit mode can't be fit into the need. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:46 +00:00
.regmap = &pwrap_regmap_config16,
soc: mediatek: pwrap: refactor pwrap_init for the various PMIC types pwrap initialization is highly associated with the base SoC and the target PMICs, so slight refactorization is made here for allowing pwrap_init to run on those PMICs with different capability from the previous MediaTek PMICs and the determination for the enablement of the pwrap capability depending on PMIC type. Apart from this, the patch makes the driver more extensible especially when more PMICs join into the pwrap driver. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:45 +00:00
.caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
PWRAP_SLV_CAP_SECURITY,
soc: mediatek: pwrap: add pwrap_read32 for reading in 32-bit mode Some regulators such as MediaTek MT6380 has to be read in 32-bit mode. So the patch adds pwrap_read32, rename old pwrap_read into pwrap_read16 and one function pointer is introduced for increasing flexibility allowing the determination which mode is used by the pwrap slave detection through device tree. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:43 +00:00
.pwrap_read = pwrap_read16,
soc: mediatek: pwrap: add pwrap_write32 for writing in 32-bit mode Some regulators such as MediaTek MT6380 also has to be written in 32-bit mode. So the patch adds pwrap_write32, rename old pwrap_write into pwrap_write16 and one additional function pointer is introduced for increasing flexibility allowing the determination which mode is used by the pwrap slave detection through device tree. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:44 +00:00
.pwrap_write = pwrap_write16,
soc: mediatek: pwrap: add pwrap_read32 for reading in 32-bit mode Some regulators such as MediaTek MT6380 has to be read in 32-bit mode. So the patch adds pwrap_read32, rename old pwrap_read into pwrap_read16 and one function pointer is introduced for increasing flexibility allowing the determination which mode is used by the pwrap slave detection through device tree. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:43 +00:00
};
soc: mediatek: pwrap: order SoCs and PMICs ascending Order SoC and PMIC numbers ascending to make the code more readable. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-25 13:46:59 +00:00
static const struct pwrap_slv_type pmic_mt6351 = {
.dew_regs = mt6351_regs,
.type = PMIC_MT6351,
.regmap = &pwrap_regmap_config16,
.caps = 0,
.pwrap_read = pwrap_read16,
.pwrap_write = pwrap_write16,
};
soc: mediatek: pwrap: add mt6357 driver for mt6765 SoCs MT6357 is a new power management IC and it is used for mt6765 SoCs. To define mt6357_regs for pmic register mapping and pmic_mt6357 for accessing register. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-04 12:31:54 +00:00
static const struct pwrap_slv_type pmic_mt6357 = {
.dew_regs = mt6357_regs,
.type = PMIC_MT6357,
.regmap = &pwrap_regmap_config16,
.caps = 0,
.pwrap_read = pwrap_read16,
.pwrap_write = pwrap_write16,
};
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
static const struct pwrap_slv_type pmic_mt6358 = {
.dew_regs = mt6358_regs,
.type = PMIC_MT6358,
.regmap = &pwrap_regmap_config16,
.caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO,
.pwrap_read = pwrap_read16,
.pwrap_write = pwrap_write16,
};
soc: mediatek: pwrap: add support for MT6359 PMIC MT6359 is a new power management IC and it is used for MT6779 SoCs. To define mt6359_regs for pmic register mapping and pmic_mt6359 for accessing register. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-02-16 06:17:23 +00:00
static const struct pwrap_slv_type pmic_mt6359 = {
.dew_regs = mt6359_regs,
.type = PMIC_MT6359,
.regmap = &pwrap_regmap_config16,
.caps = PWRAP_SLV_CAP_DUALIO,
.pwrap_read = pwrap_read16,
.pwrap_write = pwrap_write16,
};
soc: mediatek: pwrap: add pwrap_read32 for reading in 32-bit mode Some regulators such as MediaTek MT6380 has to be read in 32-bit mode. So the patch adds pwrap_read32, rename old pwrap_read into pwrap_read16 and one function pointer is introduced for increasing flexibility allowing the determination which mode is used by the pwrap slave detection through device tree. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:43 +00:00
static const struct pwrap_slv_type pmic_mt6380 = {
.dew_regs = NULL,
.type = PMIC_MT6380,
soc: mediatek: pwrap: add MediaTek MT6380 as one slave of pwrap Add MediaTek MT6380 regulator becoming one of PMIC wrapper slave and also add extra new regmap_config of 32-bit mode for MT6380 since old regmap_config of 16-bit mode can't be fit into the need. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:46 +00:00
.regmap = &pwrap_regmap_config32,
soc: mediatek: pwrap: refactor pwrap_init for the various PMIC types pwrap initialization is highly associated with the base SoC and the target PMICs, so slight refactorization is made here for allowing pwrap_init to run on those PMICs with different capability from the previous MediaTek PMICs and the determination for the enablement of the pwrap capability depending on PMIC type. Apart from this, the patch makes the driver more extensible especially when more PMICs join into the pwrap driver. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:45 +00:00
.caps = 0,
soc: mediatek: pwrap: add pwrap_read32 for reading in 32-bit mode Some regulators such as MediaTek MT6380 has to be read in 32-bit mode. So the patch adds pwrap_read32, rename old pwrap_read into pwrap_read16 and one function pointer is introduced for increasing flexibility allowing the determination which mode is used by the pwrap slave detection through device tree. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:43 +00:00
.pwrap_read = pwrap_read32,
soc: mediatek: pwrap: add pwrap_write32 for writing in 32-bit mode Some regulators such as MediaTek MT6380 also has to be written in 32-bit mode. So the patch adds pwrap_write32, rename old pwrap_write into pwrap_write16 and one additional function pointer is introduced for increasing flexibility allowing the determination which mode is used by the pwrap slave detection through device tree. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:44 +00:00
.pwrap_write = pwrap_write32,
soc: mediatek: PMIC wrap: add mt6323 slave support Add support for MT6323 slaves. This PMIC can be found on MT2701 and MT7623 EVB. The only function that we need to touch is pwrap_init_cipher(). Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:14 +00:00
};
soc: mediatek: PMIC wrap: add a slave specific struct This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:13 +00:00
static const struct pwrap_slv_type pmic_mt6397 = {
.dew_regs = mt6397_regs,
.type = PMIC_MT6397,
soc: mediatek: pwrap: add MediaTek MT6380 as one slave of pwrap Add MediaTek MT6380 regulator becoming one of PMIC wrapper slave and also add extra new regmap_config of 32-bit mode for MT6380 since old regmap_config of 16-bit mode can't be fit into the need. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:46 +00:00
.regmap = &pwrap_regmap_config16,
soc: mediatek: pwrap: refactor pwrap_init for the various PMIC types pwrap initialization is highly associated with the base SoC and the target PMICs, so slight refactorization is made here for allowing pwrap_init to run on those PMICs with different capability from the previous MediaTek PMICs and the determination for the enablement of the pwrap capability depending on PMIC type. Apart from this, the patch makes the driver more extensible especially when more PMICs join into the pwrap driver. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:45 +00:00
.caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
PWRAP_SLV_CAP_SECURITY,
soc: mediatek: pwrap: add pwrap_read32 for reading in 32-bit mode Some regulators such as MediaTek MT6380 has to be read in 32-bit mode. So the patch adds pwrap_read32, rename old pwrap_read into pwrap_read16 and one function pointer is introduced for increasing flexibility allowing the determination which mode is used by the pwrap slave detection through device tree. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:43 +00:00
.pwrap_read = pwrap_read16,
soc: mediatek: pwrap: add pwrap_write32 for writing in 32-bit mode Some regulators such as MediaTek MT6380 also has to be written in 32-bit mode. So the patch adds pwrap_write32, rename old pwrap_write into pwrap_write16 and one additional function pointer is introduced for increasing flexibility allowing the determination which mode is used by the pwrap slave detection through device tree. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:44 +00:00
.pwrap_write = pwrap_write16,
soc: mediatek: PMIC wrap: add a slave specific struct This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:13 +00:00
};
static const struct of_device_id of_slave_match_tbl[] = {
{
soc: mediatek: PMIC wrap: add mt6323 slave support Add support for MT6323 slaves. This PMIC can be found on MT2701 and MT7623 EVB. The only function that we need to touch is pwrap_init_cipher(). Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:14 +00:00
.compatible = "mediatek,mt6323",
.data = &pmic_mt6323,
soc: mediatek: pwrap: order SoCs and PMICs ascending Order SoC and PMIC numbers ascending to make the code more readable. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-25 13:46:59 +00:00
}, {
.compatible = "mediatek,mt6351",
.data = &pmic_mt6351,
soc: mediatek: pwrap: add mt6357 driver for mt6765 SoCs MT6357 is a new power management IC and it is used for mt6765 SoCs. To define mt6357_regs for pmic register mapping and pmic_mt6357 for accessing register. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-04 12:31:54 +00:00
}, {
.compatible = "mediatek,mt6357",
.data = &pmic_mt6357,
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
}, {
.compatible = "mediatek,mt6358",
.data = &pmic_mt6358,
soc: mediatek: pwrap: add support for MT6359 PMIC MT6359 is a new power management IC and it is used for MT6779 SoCs. To define mt6359_regs for pmic register mapping and pmic_mt6359 for accessing register. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-02-16 06:17:23 +00:00
}, {
.compatible = "mediatek,mt6359",
.data = &pmic_mt6359,
soc: mediatek: pwrap: add MediaTek MT6380 as one slave of pwrap Add MediaTek MT6380 regulator becoming one of PMIC wrapper slave and also add extra new regmap_config of 32-bit mode for MT6380 since old regmap_config of 16-bit mode can't be fit into the need. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:46 +00:00
}, {
/* The MT6380 PMIC only implements a regulator, so we bind it
* directly instead of using a MFD.
*/
.compatible = "mediatek,mt6380-regulator",
.data = &pmic_mt6380,
soc: mediatek: PMIC wrap: add mt6323 slave support Add support for MT6323 slaves. This PMIC can be found on MT2701 and MT7623 EVB. The only function that we need to touch is pwrap_init_cipher(). Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:14 +00:00
}, {
soc: mediatek: PMIC wrap: add a slave specific struct This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:13 +00:00
.compatible = "mediatek,mt6397",
.data = &pmic_mt6397,
soc: mediatek: pwrap: fix fatal compiler error When adding the MT6380 compatible, the sentinel for of_device_id was deleted, which leades to the following compiler error: FATAL: drivers/soc/mediatek/mtk-pmic-wrap: struct of_device_id is not terminated with a NULL entry! Fix this by adding the sentinel again. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-21 08:18:20 +00:00
}, {
soc: mediatek: PMIC wrap: add a slave specific struct This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:13 +00:00
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_slave_match_tbl);
soc: mediatek: PMIC wrap: add MT2701/7623 support Add the registers, callbacks and data structures required to make the wrapper work on MT2701 and MT7623. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:15 +00:00
static const struct pmic_wrapper_type pwrap_mt2701 = {
.regs = mt2701_regs,
.type = PWRAP_MT2701,
.arb_en_all = 0x3f,
soc: mtk-pmic-wrap: avoid integer overflow warning On ARM64, the mtk-pmic-wrap driver causes a harmless warning: mtk-pmic-wrap.c:1062:16: warning: large integer implicitly truncated to unsigned type [-Woverflow] mtk-pmic-wrap.c:1074:16: warning: large integer implicitly truncated to unsigned type [-Woverflow] mtk-pmic-wrap.c:1086:16: warning: large integer implicitly truncated to unsigned type [-Woverflow] .int_en_all = ~(BIT(31) | BIT(1)), The problem is that the result of the BIT() macro is an 'unsigned long', so taking the bitwise NOT operation of that results in an integer with the upper 32 bits all set and that cannot be assigned to a 'u32' variable without loss of information. This is harmless because we were never interested in the upper bits here anyway, so we can shut up the warning by adding a simple cast to 'u32'. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-05-12 12:28:14 +00:00
.int_en_all = ~(u32)(BIT(31) | BIT(2)),
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
.int1_en_all = 0,
soc: mediatek: PMIC wrap: add MT2701/7623 support Add the registers, callbacks and data structures required to make the wrapper work on MT2701 and MT7623. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:15 +00:00
.spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW,
.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
soc: mediatek: pwrap: use group of bits for pwrap capability Use group of bits for pwrap capability instead of elements of structure. This patch is preparing for adding mt8183 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-25 13:48:39 +00:00
.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
soc: mediatek: PMIC wrap: add MT2701/7623 support Add the registers, callbacks and data structures required to make the wrapper work on MT2701 and MT7623. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:15 +00:00
.init_reg_clock = pwrap_mt2701_init_reg_clock,
.init_soc_specific = pwrap_mt2701_init_soc_specific,
};
soc: mediatek: pwrap: add pwrap driver for mt6765 SoCs mt6765 is a highly integrated SoCs, it uses mt6357 for power management. This patch adds pwrap driver to access mt6357. Pwrap of mt6765 support dynamic priority meichanism, sequence monitor and starvation mechanism to make transaction more reliable. Signed-off-by: Argus Lin <argus.lin@mediatek.com> [mb: change has_bridge to capabilities] Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-04 12:31:53 +00:00
static const struct pmic_wrapper_type pwrap_mt6765 = {
.regs = mt6765_regs,
.type = PWRAP_MT6765,
.arb_en_all = 0x3fd35,
.int_en_all = 0xffffffff,
.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
.init_reg_clock = pwrap_common_init_reg_clock,
.init_soc_specific = NULL,
};
soc: mediatek: pwrap: add pwrap driver for MT6779 SoCs MT6779 is a highly integrated SoCs, it uses PMIC_MT6359 for power management. This patch adds pwrap master driver to access PMIC_MT6359. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-02-16 06:17:22 +00:00
static const struct pmic_wrapper_type pwrap_mt6779 = {
.regs = mt6779_regs,
.type = PWRAP_MT6779,
.arb_en_all = 0xfbb7f,
.int_en_all = 0xfffffffe,
.int1_en_all = 0,
.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
.caps = 0,
.init_reg_clock = pwrap_common_init_reg_clock,
.init_soc_specific = NULL,
};
soc: mediatek: pwrap: add pwrap driver for mt6797 SoCs mt6797 is a highly integrated SoCs, it uses mt6351 for power management. This patch adds pwrap driver to access mt6351. Pwrap of mt6797 support dynamic priority meichanism, sequence monitor and starvation mechanism to make transaction more reliable. A big change from V4 to V5 is we remove INT1 interrupt declaration since it is only for debug purpose. The PWRAP_RDDMY, RESET and DCM can use legacy setting, it is backwards compatible. The new caps flag declaration is not needed, just remove it. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-06-11 10:49:59 +00:00
static const struct pmic_wrapper_type pwrap_mt6797 = {
.regs = mt6797_regs,
.type = PWRAP_MT6797,
.arb_en_all = 0x01fff,
.int_en_all = 0xffffffc6,
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
.int1_en_all = 0,
soc: mediatek: pwrap: add pwrap driver for mt6797 SoCs mt6797 is a highly integrated SoCs, it uses mt6351 for power management. This patch adds pwrap driver to access mt6351. Pwrap of mt6797 support dynamic priority meichanism, sequence monitor and starvation mechanism to make transaction more reliable. A big change from V4 to V5 is we remove INT1 interrupt declaration since it is only for debug purpose. The PWRAP_RDDMY, RESET and DCM can use legacy setting, it is backwards compatible. The new caps flag declaration is not needed, just remove it. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-06-11 10:49:59 +00:00
.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
soc: mediatek: pwrap: use group of bits for pwrap capability Use group of bits for pwrap capability instead of elements of structure. This patch is preparing for adding mt8183 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-25 13:48:39 +00:00
.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
soc: mediatek: pwrap: add pwrap driver for mt6797 SoCs mt6797 is a highly integrated SoCs, it uses mt6351 for power management. This patch adds pwrap driver to access mt6351. Pwrap of mt6797 support dynamic priority meichanism, sequence monitor and starvation mechanism to make transaction more reliable. A big change from V4 to V5 is we remove INT1 interrupt declaration since it is only for debug purpose. The PWRAP_RDDMY, RESET and DCM can use legacy setting, it is backwards compatible. The new caps flag declaration is not needed, just remove it. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-06-11 10:49:59 +00:00
.init_reg_clock = pwrap_common_init_reg_clock,
.init_soc_specific = NULL,
};
soc: mediatek: pwrap: add pwrap driver for MT6873/8192 SoCs MT6873/8192 are highly integrated SoCs and use PMIC_MT6359 for power management. This patch adds pwrap master driver to access PMIC_MT6359. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-5-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:45 +00:00
static const struct pmic_wrapper_type pwrap_mt6873 = {
.regs = mt6873_regs,
.type = PWRAP_MT6873,
.arb_en_all = 0x777f,
.int_en_all = BIT(4) | BIT(5),
.int1_en_all = 0,
.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
.caps = PWRAP_CAP_ARB,
.init_reg_clock = pwrap_common_init_reg_clock,
.init_soc_specific = NULL,
};
soc: mediatek: pwrap: add support for MT7622 SoC Add the registers, callbacks and data structures required to make the PMIC wrapper work on MT7622. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:48 +00:00
static const struct pmic_wrapper_type pwrap_mt7622 = {
.regs = mt7622_regs,
.type = PWRAP_MT7622,
.arb_en_all = 0xff,
.int_en_all = ~(u32)BIT(31),
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
.int1_en_all = 0,
soc: mediatek: pwrap: add support for MT7622 SoC Add the registers, callbacks and data structures required to make the PMIC wrapper work on MT7622. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:48 +00:00
.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
soc: mediatek: pwrap: use group of bits for pwrap capability Use group of bits for pwrap capability instead of elements of structure. This patch is preparing for adding mt8183 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-25 13:48:39 +00:00
.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
soc: mediatek: pwrap: add support for MT7622 SoC Add the registers, callbacks and data structures required to make the PMIC wrapper work on MT7622. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:48 +00:00
.init_reg_clock = pwrap_common_init_reg_clock,
.init_soc_specific = pwrap_mt7622_init_soc_specific,
};
soc: mtk-pmic-wrap: make of_device_ids const. of_device_ids are not supposed to change at runtime. All functions working with of_device_ids provided by <linux/of.h> work with const of_device_ids. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-06-28 04:58:21 +00:00
static const struct pmic_wrapper_type pwrap_mt8135 = {
soc: mediatek: PMIC wrap: add wrapper callbacks for init_reg_clock Split init_reg_clock up into SoC specific callbacks. The patch also reorders the code to avoid the need for callback function prototypes. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:07 +00:00
.regs = mt8135_regs,
.type = PWRAP_MT8135,
.arb_en_all = 0x1ff,
soc: mtk-pmic-wrap: avoid integer overflow warning On ARM64, the mtk-pmic-wrap driver causes a harmless warning: mtk-pmic-wrap.c:1062:16: warning: large integer implicitly truncated to unsigned type [-Woverflow] mtk-pmic-wrap.c:1074:16: warning: large integer implicitly truncated to unsigned type [-Woverflow] mtk-pmic-wrap.c:1086:16: warning: large integer implicitly truncated to unsigned type [-Woverflow] .int_en_all = ~(BIT(31) | BIT(1)), The problem is that the result of the BIT() macro is an 'unsigned long', so taking the bitwise NOT operation of that results in an integer with the upper 32 bits all set and that cannot be assigned to a 'u32' variable without loss of information. This is harmless because we were never interested in the upper bits here anyway, so we can shut up the warning by adding a simple cast to 'u32'. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-05-12 12:28:14 +00:00
.int_en_all = ~(u32)(BIT(31) | BIT(1)),
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
.int1_en_all = 0,
soc: mediatek: PMIC wrap: SPI_WRITE needs a different bitmask for MT2701/7623 Different SoCs will use different bitmask for the SPI_WRITE command. This patch defines the bitmask in the pmic_wrapper_type struct. This allows us to support new SoCs with a different bitmask to the one currently used. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:10 +00:00
.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
soc: mediatek: PMIC wrap: move wdt_src into the pmic_wrapper_type struct Different SoCs will use different bitmask for the wdt_src. This patch defines the bitmask in the pmic_wrapper_type struct. This allows us to support new SoCs with a different bitmask to the one currently used. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:11 +00:00
.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
soc: mediatek: pwrap: use group of bits for pwrap capability Use group of bits for pwrap capability instead of elements of structure. This patch is preparing for adding mt8183 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-25 13:48:39 +00:00
.caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM,
soc: mediatek: pwrap: add common way for setup CS timing extenstion Multiple platforms would always use their own way handling CS timing extension on the bus which leads to a little bit code duplication. Therefore, the patch groups the similar logic to handle CS timing extension into the common function which allows the following SoCs have more reusability for configing CS timing. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:47 +00:00
.init_reg_clock = pwrap_common_init_reg_clock,
soc: mediatek: PMIC wrap: split SoC specific init into callback This patch moves the SoC specific wrapper init code into separate callback to avoid pwrap_init() getting too large. This is done by adding a new element called init_special to pmic_wrapper_type. Each currently supported SoC gets its own version of the callback and we copy the code that was previously inside pwrap_init() to these new callbacks. Finally we point the 2 instances of pmic_wrapper_type at the 2 new functions. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:08 +00:00
.init_soc_specific = pwrap_mt8135_init_soc_specific,
soc: mediatek: PMIC wrap: add wrapper callbacks for init_reg_clock Split init_reg_clock up into SoC specific callbacks. The patch also reorders the code to avoid the need for callback function prototypes. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:07 +00:00
};
soc: mtk-pmic-wrap: make of_device_ids const. of_device_ids are not supposed to change at runtime. All functions working with of_device_ids provided by <linux/of.h> work with const of_device_ids. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-06-28 04:58:21 +00:00
static const struct pmic_wrapper_type pwrap_mt8173 = {
soc: mediatek: PMIC wrap: add wrapper callbacks for init_reg_clock Split init_reg_clock up into SoC specific callbacks. The patch also reorders the code to avoid the need for callback function prototypes. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:07 +00:00
.regs = mt8173_regs,
.type = PWRAP_MT8173,
.arb_en_all = 0x3f,
soc: mtk-pmic-wrap: avoid integer overflow warning On ARM64, the mtk-pmic-wrap driver causes a harmless warning: mtk-pmic-wrap.c:1062:16: warning: large integer implicitly truncated to unsigned type [-Woverflow] mtk-pmic-wrap.c:1074:16: warning: large integer implicitly truncated to unsigned type [-Woverflow] mtk-pmic-wrap.c:1086:16: warning: large integer implicitly truncated to unsigned type [-Woverflow] .int_en_all = ~(BIT(31) | BIT(1)), The problem is that the result of the BIT() macro is an 'unsigned long', so taking the bitwise NOT operation of that results in an integer with the upper 32 bits all set and that cannot be assigned to a 'u32' variable without loss of information. This is harmless because we were never interested in the upper bits here anyway, so we can shut up the warning by adding a simple cast to 'u32'. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-05-12 12:28:14 +00:00
.int_en_all = ~(u32)(BIT(31) | BIT(1)),
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
.int1_en_all = 0,
soc: mediatek: PMIC wrap: SPI_WRITE needs a different bitmask for MT2701/7623 Different SoCs will use different bitmask for the SPI_WRITE command. This patch defines the bitmask in the pmic_wrapper_type struct. This allows us to support new SoCs with a different bitmask to the one currently used. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:10 +00:00
.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
soc: mediatek: PMIC wrap: move wdt_src into the pmic_wrapper_type struct Different SoCs will use different bitmask for the wdt_src. This patch defines the bitmask in the pmic_wrapper_type struct. This allows us to support new SoCs with a different bitmask to the one currently used. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:11 +00:00
.wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
soc: mediatek: pwrap: use group of bits for pwrap capability Use group of bits for pwrap capability instead of elements of structure. This patch is preparing for adding mt8183 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-25 13:48:39 +00:00
.caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
soc: mediatek: pwrap: add common way for setup CS timing extenstion Multiple platforms would always use their own way handling CS timing extension on the bus which leads to a little bit code duplication. Therefore, the patch groups the similar logic to handle CS timing extension into the common function which allows the following SoCs have more reusability for configing CS timing. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:47 +00:00
.init_reg_clock = pwrap_common_init_reg_clock,
soc: mediatek: PMIC wrap: split SoC specific init into callback This patch moves the SoC specific wrapper init code into separate callback to avoid pwrap_init() getting too large. This is done by adding a new element called init_special to pmic_wrapper_type. Each currently supported SoC gets its own version of the callback and we copy the code that was previously inside pwrap_init() to these new callbacks. Finally we point the 2 instances of pmic_wrapper_type at the 2 new functions. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:08 +00:00
.init_soc_specific = pwrap_mt8173_init_soc_specific,
soc: mediatek: PMIC wrap: add wrapper callbacks for init_reg_clock Split init_reg_clock up into SoC specific callbacks. The patch also reorders the code to avoid the need for callback function prototypes. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:07 +00:00
};
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
static const struct pmic_wrapper_type pwrap_mt8183 = {
.regs = mt8183_regs,
.type = PWRAP_MT8183,
.arb_en_all = 0x3fa75,
.int_en_all = 0xffffffff,
.int1_en_all = 0xeef7ffff,
.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
.caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1,
.init_reg_clock = pwrap_common_init_reg_clock,
.init_soc_specific = pwrap_mt8183_init_soc_specific,
};
soc: mediatek: pwrap: add pwrap driver for MT8195 SoC MT8195 are highly integrated SoC and use PMIC_MT6359 for power management. This patch adds pwrap master driver to access PMIC_MT6359. Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Link: https://lore.kernel.org/r/20210602112050.12338-3-james.lo@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-06-02 11:20:50 +00:00
static struct pmic_wrapper_type pwrap_mt8195 = {
.regs = mt8195_regs,
.type = PWRAP_MT8195,
.arb_en_all = 0x777f, /* NEED CONFIRM */
.int_en_all = 0x180000, /* NEED CONFIRM */
.int1_en_all = 0,
.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
.caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB,
.init_reg_clock = pwrap_common_init_reg_clock,
.init_soc_specific = NULL,
};
soc: mediatek: pwrap: add support for MT8516 pwrap Add the code to support the pwrap IP on the MediaTek MT8516 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-03-23 21:15:53 +00:00
static struct pmic_wrapper_type pwrap_mt8516 = {
.regs = mt8516_regs,
.type = PWRAP_MT8516,
.arb_en_all = 0xff,
.int_en_all = ~(u32)(BIT(31) | BIT(2)),
.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
.caps = PWRAP_CAP_DCM,
.init_reg_clock = pwrap_mt2701_init_reg_clock,
.init_soc_specific = NULL,
};
soc: mediatek: pwrap: add pwrap driver for MT8186 SoC MT8186 are highly integrated SoC and use PMIC_MT6366 for power management. This patch adds pwrap master driver to access PMIC_MT6366. Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Link: https://lore.kernel.org/r/20220207083034.15327-2-johnson.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-07 08:30:33 +00:00
static struct pmic_wrapper_type pwrap_mt8186 = {
.regs = mt8186_regs,
.type = PWRAP_MT8186,
.arb_en_all = 0xfb27f,
.int_en_all = 0xfffffffe, /* disable WatchDog Timeout for bit 1 */
.int1_en_all = 0x000017ff, /* disable Matching interrupt for bit 13 */
.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
.caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB_MT8186,
.init_reg_clock = pwrap_common_init_reg_clock,
.init_soc_specific = NULL,
};
soc: mtk-pmic-wrap: make of_device_ids const. of_device_ids are not supposed to change at runtime. All functions working with of_device_ids provided by <linux/of.h> work with const of_device_ids. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-06-28 04:58:21 +00:00
static const struct of_device_id of_pwrap_match_tbl[] = {
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
{
soc: mediatek: PMIC wrap: add MT2701/7623 support Add the registers, callbacks and data structures required to make the wrapper work on MT2701 and MT7623. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:15 +00:00
.compatible = "mediatek,mt2701-pwrap",
.data = &pwrap_mt2701,
soc: mediatek: pwrap: add pwrap driver for mt6765 SoCs mt6765 is a highly integrated SoCs, it uses mt6357 for power management. This patch adds pwrap driver to access mt6357. Pwrap of mt6765 support dynamic priority meichanism, sequence monitor and starvation mechanism to make transaction more reliable. Signed-off-by: Argus Lin <argus.lin@mediatek.com> [mb: change has_bridge to capabilities] Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-04 12:31:53 +00:00
}, {
.compatible = "mediatek,mt6765-pwrap",
.data = &pwrap_mt6765,
soc: mediatek: pwrap: add pwrap driver for MT6779 SoCs MT6779 is a highly integrated SoCs, it uses PMIC_MT6359 for power management. This patch adds pwrap master driver to access PMIC_MT6359. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-02-16 06:17:22 +00:00
}, {
.compatible = "mediatek,mt6779-pwrap",
.data = &pwrap_mt6779,
soc: mediatek: pwrap: add pwrap driver for mt6797 SoCs mt6797 is a highly integrated SoCs, it uses mt6351 for power management. This patch adds pwrap driver to access mt6351. Pwrap of mt6797 support dynamic priority meichanism, sequence monitor and starvation mechanism to make transaction more reliable. A big change from V4 to V5 is we remove INT1 interrupt declaration since it is only for debug purpose. The PWRAP_RDDMY, RESET and DCM can use legacy setting, it is backwards compatible. The new caps flag declaration is not needed, just remove it. Signed-off-by: Argus Lin <argus.lin@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-06-11 10:49:59 +00:00
}, {
.compatible = "mediatek,mt6797-pwrap",
.data = &pwrap_mt6797,
soc: mediatek: pwrap: add pwrap driver for MT6873/8192 SoCs MT6873/8192 are highly integrated SoCs and use PMIC_MT6359 for power management. This patch adds pwrap master driver to access PMIC_MT6359. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-5-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:45 +00:00
}, {
.compatible = "mediatek,mt6873-pwrap",
.data = &pwrap_mt6873,
soc: mediatek: pwrap: add support for MT7622 SoC Add the registers, callbacks and data structures required to make the PMIC wrapper work on MT7622. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:48 +00:00
}, {
.compatible = "mediatek,mt7622-pwrap",
.data = &pwrap_mt7622,
soc: mediatek: PMIC wrap: add MT2701/7623 support Add the registers, callbacks and data structures required to make the wrapper work on MT2701 and MT7623. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:15 +00:00
}, {
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
.compatible = "mediatek,mt8135-pwrap",
.data = &pwrap_mt8135,
}, {
.compatible = "mediatek,mt8173-pwrap",
.data = &pwrap_mt8173,
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
}, {
.compatible = "mediatek,mt8183-pwrap",
.data = &pwrap_mt8183,
soc: mediatek: pwrap: add pwrap driver for MT8186 SoC MT8186 are highly integrated SoC and use PMIC_MT6366 for power management. This patch adds pwrap master driver to access PMIC_MT6366. Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Link: https://lore.kernel.org/r/20220207083034.15327-2-johnson.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-07 08:30:33 +00:00
}, {
.compatible = "mediatek,mt8186-pwrap",
.data = &pwrap_mt8186,
soc: mediatek: pwrap: add pwrap driver for MT8195 SoC MT8195 are highly integrated SoC and use PMIC_MT6359 for power management. This patch adds pwrap master driver to access PMIC_MT6359. Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Link: https://lore.kernel.org/r/20210602112050.12338-3-james.lo@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-06-02 11:20:50 +00:00
}, {
.compatible = "mediatek,mt8195-pwrap",
.data = &pwrap_mt8195,
soc: mediatek: pwrap: add support for MT8516 pwrap Add the code to support the pwrap IP on the MediaTek MT8516 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-03-23 21:15:53 +00:00
}, {
.compatible = "mediatek,mt8516-pwrap",
.data = &pwrap_mt8516,
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
static int pwrap_probe(struct platform_device *pdev)
{
soc: mediatek: PMIC wrap: move wdt_src into the pmic_wrapper_type struct Different SoCs will use different bitmask for the wdt_src. This patch defines the bitmask in the pmic_wrapper_type struct. This allows us to support new SoCs with a different bitmask to the one currently used. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:11 +00:00
int ret, irq;
soc: mediatek: pwrap: add arbiter capability Add arbiter capability for pwrap driver. The arbiter capability uses new design to judge the priority and latency for multi-channel. The design with arbiter support cannot change the watchdog timer. This patch is preparing for adding mt6873/8192 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-3-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:43 +00:00
u32 mask_done;
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
struct pmic_wrapper *wrp;
struct device_node *np = pdev->dev.of_node;
soc: mediatek: PMIC wrap: add a slave specific struct This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:13 +00:00
const struct of_device_id *of_slave_id = NULL;
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
struct resource *res;
soc: mediatek: use of_device_get_match_data() The usage of of_device_get_match_data() reduce the code size a bit. Also, the only way to call pwrap_probe() is to match an entry in of_pwrap_match_tbl[], so of_id cannot be NULL. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-04-16 02:33:34 +00:00
if (np->child)
of_slave_id = of_match_node(of_slave_match_tbl, np->child);
soc: mediatek: PMIC wrap: Fix possible NULL derefrence. of_match_device could return NULL, and so can cause a NULL pointer dereference later. Signed-off-by: Shailendra Verma <shailendra.v@samsung.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-01-27 11:17:48 +00:00
soc: mediatek: PMIC wrap: add a slave specific struct This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:13 +00:00
if (!of_slave_id) {
dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n");
return -EINVAL;
}
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
if (!wrp)
return -ENOMEM;
platform_set_drvdata(pdev, wrp);
soc: mediatek: use of_device_get_match_data() The usage of of_device_get_match_data() reduce the code size a bit. Also, the only way to call pwrap_probe() is to match an entry in of_pwrap_match_tbl[], so of_id cannot be NULL. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-04-16 02:33:34 +00:00
wrp->master = of_device_get_match_data(&pdev->dev);
soc: mediatek: PMIC wrap: add a slave specific struct This patch adds a new struct pwrap_slv_type that we use to store the slave specific data. The patch adds 2 new helper functions to access the dew registers. The slave type is looked up via the wrappers child node. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:13 +00:00
wrp->slave = of_slave_id->data;
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
wrp->dev = &pdev->dev;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
wrp->base = devm_ioremap_resource(wrp->dev, res);
if (IS_ERR(wrp->base))
return PTR_ERR(wrp->base);
soc: mediatek: pwrap: use group of bits for pwrap capability Use group of bits for pwrap capability instead of elements of structure. This patch is preparing for adding mt8183 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-25 13:48:39 +00:00
if (HAS_CAP(wrp->master->caps, PWRAP_CAP_RESET)) {
wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
if (IS_ERR(wrp->rstc)) {
ret = PTR_ERR(wrp->rstc);
dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);
return ret;
}
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
}
soc: mediatek: pwrap: use group of bits for pwrap capability Use group of bits for pwrap capability instead of elements of structure. This patch is preparing for adding mt8183 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-25 13:48:39 +00:00
if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"pwrap-bridge");
wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);
if (IS_ERR(wrp->bridge_base))
return PTR_ERR(wrp->bridge_base);
soc: mediatek: pwrap: fixup warnings from coding style fixup those warnings such as lines over 80 words and parenthesis alignment which would be complained by checkpatch.pl. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-09-21 08:26:57 +00:00
wrp->rstc_bridge = devm_reset_control_get(wrp->dev,
"pwrap-bridge");
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
if (IS_ERR(wrp->rstc_bridge)) {
ret = PTR_ERR(wrp->rstc_bridge);
soc: mediatek: pwrap: fixup warnings from coding style fixup those warnings such as lines over 80 words and parenthesis alignment which would be complained by checkpatch.pl. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-09-21 08:26:57 +00:00
dev_dbg(wrp->dev,
"cannot get pwrap-bridge reset: %d\n", ret);
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
return ret;
}
}
wrp->clk_spi = devm_clk_get(wrp->dev, "spi");
if (IS_ERR(wrp->clk_spi)) {
soc: mediatek: pwrap: fixup warnings from coding style fixup those warnings such as lines over 80 words and parenthesis alignment which would be complained by checkpatch.pl. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-09-21 08:26:57 +00:00
dev_dbg(wrp->dev, "failed to get clock: %ld\n",
PTR_ERR(wrp->clk_spi));
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
return PTR_ERR(wrp->clk_spi);
}
wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap");
if (IS_ERR(wrp->clk_wrap)) {
soc: mediatek: pwrap: fixup warnings from coding style fixup those warnings such as lines over 80 words and parenthesis alignment which would be complained by checkpatch.pl. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-09-21 08:26:57 +00:00
dev_dbg(wrp->dev, "failed to get clock: %ld\n",
PTR_ERR(wrp->clk_wrap));
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
return PTR_ERR(wrp->clk_wrap);
}
ret = clk_prepare_enable(wrp->clk_spi);
if (ret)
return ret;
ret = clk_prepare_enable(wrp->clk_wrap);
if (ret)
goto err_out1;
/* Enable internal dynamic clock */
soc: mediatek: pwrap: use group of bits for pwrap capability Use group of bits for pwrap capability instead of elements of structure. This patch is preparing for adding mt8183 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-25 13:48:39 +00:00
if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) {
pwrap_writel(wrp, 1, PWRAP_DCM_EN);
pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
}
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
/*
* The PMIC could already be initialized by the bootloader.
* Skip initialization here in this case.
*/
if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) {
ret = pwrap_init(wrp);
if (ret) {
dev_dbg(wrp->dev, "init failed with %d\n", ret);
goto err_out2;
}
}
soc: mediatek: pwrap: add arbiter capability Add arbiter capability for pwrap driver. The arbiter capability uses new design to judge the priority and latency for multi-channel. The design with arbiter support cannot change the watchdog timer. This patch is preparing for adding mt6873/8192 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-3-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:43 +00:00
if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
mask_done = PWRAP_STATE_INIT_DONE1;
soc: mediatek: pwrap: add pwrap driver for MT8186 SoC MT8186 are highly integrated SoC and use PMIC_MT6366 for power management. This patch adds pwrap master driver to access PMIC_MT6366. Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Link: https://lore.kernel.org/r/20220207083034.15327-2-johnson.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-07 08:30:33 +00:00
else if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB_MT8186))
mask_done = PWRAP_STATE_INIT_DONE0_MT8186;
soc: mediatek: pwrap: add arbiter capability Add arbiter capability for pwrap driver. The arbiter capability uses new design to judge the priority and latency for multi-channel. The design with arbiter support cannot change the watchdog timer. This patch is preparing for adding mt6873/8192 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-3-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:43 +00:00
else
mask_done = PWRAP_STATE_INIT_DONE0;
if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & mask_done)) {
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
dev_dbg(wrp->dev, "initialization isn't finished\n");
soc: mediatek: PMIC wrap: Fix error handling According to error handling in this function, it is likely that going to 'err_out2' was expected here. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-02-19 13:12:49 +00:00
ret = -ENODEV;
goto err_out2;
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
}
soc: mediatek: Move the initial setting of pmic wrap interrupt before requesting irq. The watchdog may not be initialized by the bootloader, even if the rest of the pwrap is. Move the watchdog initialization out of pwrap_init() to make sure the watchdog is always initialized and not only when the pwrap is uninitialized. Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-09-11 13:05:20 +00:00
/* Initialize watchdog, may not be done by the bootloader */
soc: mediatek: pwrap: add arbiter capability Add arbiter capability for pwrap driver. The arbiter capability uses new design to judge the priority and latency for multi-channel. The design with arbiter support cannot change the watchdog timer. This patch is preparing for adding mt6873/8192 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-3-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:43 +00:00
if (!HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
soc: mediatek: PMIC wrap: clear the STAUPD_TRIG bit of WDT_SRC_EN Since STAUPD interrupts aren't handled on mt8173, disable watchdog timeout monitor of STAUPD to avoid WDT_INT triggered by STAUPD. Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-01-21 11:04:00 +00:00
/*
* Since STAUPD was not used on mt8173 platform,
* so STAUPD of WDT_SRC which should be turned off
*/
soc: mediatek: PMIC wrap: move wdt_src into the pmic_wrapper_type struct Different SoCs will use different bitmask for the wdt_src. This patch defines the bitmask in the pmic_wrapper_type struct. This allows us to support new SoCs with a different bitmask to the one currently used. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:11 +00:00
pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN);
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1))
pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1);
soc: mediatek: pwrap: add arbiter capability Add arbiter capability for pwrap driver. The arbiter capability uses new design to judge the priority and latency for multi-channel. The design with arbiter support cannot change the watchdog timer. This patch is preparing for adding mt6873/8192 pwrap support. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Link: https://lore.kernel.org/r/1615563286-22126-3-git-send-email-hsin-hsiung.wang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-12 15:34:43 +00:00
if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
pwrap_writel(wrp, 0x3, PWRAP_TIMER_EN);
else
pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
soc: mediatek: PMIC wrap: WRAP_INT_EN needs a different bitmask for MT2701/7623 MT2701 and MT7623 use a different bitmask for PWRAP_INT_EN. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 08:44:09 +00:00
pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
soc: mediatek: add mt8183 pwrap support MT6358 is a new power management IC and it is used for mt8183 SoCs. To define mt6358_regs for pmic register mapping and pmic_mt6358 for accessing register. Adding one more interrupt and wdt source. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2018-09-19 07:26:00 +00:00
/*
* We add INT1 interrupt to handle starvation and request exception
* If we support it, we should enable it here.
*/
if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN))
pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN);
soc: mediatek: Move the initial setting of pmic wrap interrupt before requesting irq. The watchdog may not be initialized by the bootloader, even if the rest of the pwrap is. Move the watchdog initialization out of pwrap_init() to make sure the watchdog is always initialized and not only when the pwrap is uninitialized. Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-09-11 13:05:20 +00:00
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
irq = platform_get_irq(pdev, 0);
soc: mediatek: pwrap: fixup warnings from coding style fixup those warnings such as lines over 80 words and parenthesis alignment which would be complained by checkpatch.pl. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-09-21 08:26:57 +00:00
ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt,
IRQF_TRIGGER_HIGH,
"mt-pmic-pwrap", wrp);
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
if (ret)
goto err_out2;
soc: mediatek: pwrap: add MediaTek MT6380 as one slave of pwrap Add MediaTek MT6380 regulator becoming one of PMIC wrapper slave and also add extra new regmap_config of 32-bit mode for MT6380 since old regmap_config of 16-bit mode can't be fit into the need. Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-10-18 08:28:46 +00:00
wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regmap);
soc: mediatek: PMIC wrap: Fix error handling According to error handling in this function, it is likely that going to 'err_out2' was expected here. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2017-02-19 13:12:49 +00:00
if (IS_ERR(wrp->regmap)) {
ret = PTR_ERR(wrp->regmap);
goto err_out2;
}
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
ret = of_platform_populate(np, NULL, NULL, wrp->dev);
if (ret) {
soc: Convert to using %pOF instead of full_name Now that we have a custom printf format specifier, convert users of full_name to use %pOF instead. This is preparation to remove storing of the full path string for each node. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Cc: Scott Wood <oss@buserror.net> Cc: Qiang Zhao <qiang.zhao@nxp.com> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-07-18 21:43:29 +00:00
dev_dbg(wrp->dev, "failed to create child devices at %pOF\n",
np);
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs This adds support for the PMIC wrapper found on MediaTek MT8135 and MT8173 SoCs. The PMIC wrapper is found on MT6xxx SoCs aswell but these are currently not supported. On MediaTek MT8135, MT8173 and other SoCs the PMIC is connected via SPI. The SPI master interface is not directly visible to the CPU, but only through the PMIC wrapper inside the SoC. The communication between the SoC and the PMIC can optionally be encrypted. Also a non standard Dual IO SPI mode can be used to increase speed. The MT8135 also supports a special feature named "IP Pairing". With IP Pairing the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. Because of these optional non SPI conform features the PMIC driver is not implemented as a SPI bus master driver. Signed-off-by: Flora Fu, MediaTek Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2015-03-17 10:14:34 +00:00
goto err_out2;
}
return 0;
err_out2:
clk_disable_unprepare(wrp->clk_wrap);
err_out1:
clk_disable_unprepare(wrp->clk_spi);
return ret;
}
static struct platform_driver pwrap_drv = {
.driver = {
.name = "mt-pmic-pwrap",
.of_match_table = of_match_ptr(of_pwrap_match_tbl),
},
.probe = pwrap_probe,
};
module_platform_driver(pwrap_drv);
MODULE_AUTHOR("Flora Fu, MediaTek");
MODULE_DESCRIPTION("MediaTek MT8135 PMIC Wrapper Driver");
MODULE_LICENSE("GPL v2");
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