2019-06-04 08:11:33 +00:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0-only */
|
2010-02-02 19:23:15 +00:00
|
|
|
/*
|
|
|
|
* linux/arch/arm/include/asm/pmu.h
|
|
|
|
*
|
|
|
|
* Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef __ARM_PMU_H__
|
|
|
|
#define __ARM_PMU_H__
|
|
|
|
|
2011-02-08 03:54:36 +00:00
|
|
|
#include <linux/interrupt.h>
|
2011-05-19 09:07:57 +00:00
|
|
|
#include <linux/perf_event.h>
|
2017-10-09 16:09:05 +00:00
|
|
|
#include <linux/platform_device.h>
|
2016-09-09 13:08:26 +00:00
|
|
|
#include <linux/sysfs.h>
|
2014-05-23 17:11:14 +00:00
|
|
|
#include <asm/cputype.h>
|
|
|
|
|
2015-07-06 11:23:53 +00:00
|
|
|
#ifdef CONFIG_ARM_PMU
|
2011-05-19 09:07:57 +00:00
|
|
|
|
2014-05-28 17:08:40 +00:00
|
|
|
/*
|
|
|
|
* The ARMv7 CPU PMU supports up to 32 event counters.
|
|
|
|
*/
|
|
|
|
#define ARMPMU_MAX_HWEVENTS 32
|
|
|
|
|
2018-07-10 08:58:00 +00:00
|
|
|
/*
|
|
|
|
* ARM PMU hw_event flags
|
|
|
|
*/
|
2022-09-07 09:19:23 +00:00
|
|
|
#define ARMPMU_EVT_64BIT 0x00001 /* Event uses a 64bit counter */
|
|
|
|
#define ARMPMU_EVT_47BIT 0x00002 /* Event uses a 47bit counter */
|
drivers/perf: apple_m1: Force 63bit counters for M2 CPUs
Sidharth reports that on M2, the PMU never generates any interrupt
when using 'perf record', which is a annoying as you get no sample.
I'm temped to say "no sample, no problem", but others may have
a different opinion.
Upon investigation, it appears that the counters on M2 are
significantly different from the ones on M1, as they count on
64 bits instead of 48. Which of course, in the fine M1 tradition,
means that we can only use 63 bits, as the top bit is used to signal
the interrupt...
This results in having to introduce yet another flag to indicate yet
another odd counter width. Who knows what the next crazy implementation
will do...
With this, perf can work out the correct offset, and 'perf record'
works as intended.
Tested on M2 and M2-Pro CPUs.
Cc: Janne Grunau <j@jannau.net>
Cc: Hector Martin <marcan@marcan.st>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>
Fixes: 7d0bfb7c9977 ("drivers/perf: apple_m1: Add Apple M2 support")
Reported-by: Sidharth Kshatriya <sid.kshatriya@gmail.com>
Tested-by: Sidharth Kshatriya <sid.kshatriya@gmail.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230528080205.288446-1-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
2023-05-28 08:02:05 +00:00
|
|
|
#define ARMPMU_EVT_63BIT 0x00004 /* Event uses a 63bit counter */
|
2022-09-07 09:19:23 +00:00
|
|
|
|
|
|
|
static_assert((PERF_EVENT_FLAG_ARCH & ARMPMU_EVT_64BIT) == ARMPMU_EVT_64BIT);
|
|
|
|
static_assert((PERF_EVENT_FLAG_ARCH & ARMPMU_EVT_47BIT) == ARMPMU_EVT_47BIT);
|
drivers/perf: apple_m1: Force 63bit counters for M2 CPUs
Sidharth reports that on M2, the PMU never generates any interrupt
when using 'perf record', which is a annoying as you get no sample.
I'm temped to say "no sample, no problem", but others may have
a different opinion.
Upon investigation, it appears that the counters on M2 are
significantly different from the ones on M1, as they count on
64 bits instead of 48. Which of course, in the fine M1 tradition,
means that we can only use 63 bits, as the top bit is used to signal
the interrupt...
This results in having to introduce yet another flag to indicate yet
another odd counter width. Who knows what the next crazy implementation
will do...
With this, perf can work out the correct offset, and 'perf record'
works as intended.
Tested on M2 and M2-Pro CPUs.
Cc: Janne Grunau <j@jannau.net>
Cc: Hector Martin <marcan@marcan.st>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>
Fixes: 7d0bfb7c9977 ("drivers/perf: apple_m1: Add Apple M2 support")
Reported-by: Sidharth Kshatriya <sid.kshatriya@gmail.com>
Tested-by: Sidharth Kshatriya <sid.kshatriya@gmail.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230528080205.288446-1-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
2023-05-28 08:02:05 +00:00
|
|
|
static_assert((PERF_EVENT_FLAG_ARCH & ARMPMU_EVT_63BIT) == ARMPMU_EVT_63BIT);
|
2018-07-10 08:58:00 +00:00
|
|
|
|
2014-05-28 17:08:40 +00:00
|
|
|
#define HW_OP_UNSUPPORTED 0xFFFF
|
|
|
|
#define C(_x) PERF_COUNT_HW_CACHE_##_x
|
|
|
|
#define CACHE_OP_UNSUPPORTED 0xFFFF
|
|
|
|
|
2014-05-29 16:29:51 +00:00
|
|
|
#define PERF_MAP_ALL_UNSUPPORTED \
|
|
|
|
[0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
|
|
|
|
|
|
|
|
#define PERF_CACHE_MAP_ALL_UNSUPPORTED \
|
|
|
|
[0 ... C(MAX) - 1] = { \
|
|
|
|
[0 ... C(OP_MAX) - 1] = { \
|
|
|
|
[0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \
|
|
|
|
}, \
|
|
|
|
}
|
|
|
|
|
2011-05-19 09:07:57 +00:00
|
|
|
/* The events for a given PMU register set. */
|
|
|
|
struct pmu_hw_events {
|
|
|
|
/*
|
|
|
|
* The events that are active on the PMU for the given index.
|
|
|
|
*/
|
2014-05-13 18:08:19 +00:00
|
|
|
struct perf_event *events[ARMPMU_MAX_HWEVENTS];
|
2011-05-19 09:07:57 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* A 1 bit for an index indicates that the counter is being used for
|
|
|
|
* an event. A 0 means that the counter can be used.
|
|
|
|
*/
|
2014-05-13 18:08:19 +00:00
|
|
|
DECLARE_BITMAP(used_mask, ARMPMU_MAX_HWEVENTS);
|
2011-05-19 09:07:57 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Hardware lock to serialize accesses to PMU registers. Needed for the
|
|
|
|
* read/modify/write sequences.
|
|
|
|
*/
|
|
|
|
raw_spinlock_t pmu_lock;
|
2014-05-13 18:46:10 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* When using percpu IRQs, we need a percpu dev_id. Place it here as we
|
|
|
|
* already have to allocate this struct per cpu.
|
|
|
|
*/
|
|
|
|
struct arm_pmu *percpu_pmu;
|
2017-03-10 10:46:14 +00:00
|
|
|
|
|
|
|
int irq;
|
2011-05-19 09:07:57 +00:00
|
|
|
};
|
|
|
|
|
2016-09-09 13:08:26 +00:00
|
|
|
enum armpmu_attr_groups {
|
drivers/perf: arm_pmu: expose a cpumask in sysfs
In systems with heterogeneous CPUs, there are multiple logical CPU PMUs,
each of which covers a subset of CPUs in the system. In some cases
userspace needs to know which CPUs a given logical PMU covers, so we'd
like to expose a cpumask under sysfs, similar to what is done for uncore
PMUs.
Unfortunately, prior to commit 00e727bb389359c8 ("perf stat: Balance
opening and reading events"), perf stat only correctly handled a cpumask
holding a single CPU, and only when profiling in system-wide mode. In
other cases, the presence of a cpumask file could cause perf stat to
behave erratically.
Thus, exposing a cpumask file would break older perf binaries in cases
where they would otherwise work.
To avoid this issue while still providing userspace with the information
it needs, this patch exposes a differently-named file (cpus) under
sysfs. New tools can look for this and operate correctly, while older
tools will not be adversely affected by its presence.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-09-09 13:08:30 +00:00
|
|
|
ARMPMU_ATTR_GROUP_COMMON,
|
2016-09-09 13:08:26 +00:00
|
|
|
ARMPMU_ATTR_GROUP_EVENTS,
|
|
|
|
ARMPMU_ATTR_GROUP_FORMATS,
|
2020-09-22 05:53:45 +00:00
|
|
|
ARMPMU_ATTR_GROUP_CAPS,
|
2016-09-09 13:08:26 +00:00
|
|
|
ARMPMU_NR_ATTR_GROUPS
|
|
|
|
};
|
|
|
|
|
2011-05-19 09:07:57 +00:00
|
|
|
struct arm_pmu {
|
|
|
|
struct pmu pmu;
|
2015-05-13 16:12:25 +00:00
|
|
|
cpumask_t supported_cpus;
|
2012-07-06 14:45:00 +00:00
|
|
|
char *name;
|
2020-03-02 18:17:52 +00:00
|
|
|
int pmuver;
|
2018-05-10 10:35:15 +00:00
|
|
|
irqreturn_t (*handle_irq)(struct arm_pmu *pmu);
|
2012-07-30 11:00:02 +00:00
|
|
|
void (*enable)(struct perf_event *event);
|
|
|
|
void (*disable)(struct perf_event *event);
|
2011-05-19 09:07:57 +00:00
|
|
|
int (*get_event_idx)(struct pmu_hw_events *hw_events,
|
2012-07-30 11:00:02 +00:00
|
|
|
struct perf_event *event);
|
2014-02-07 21:01:22 +00:00
|
|
|
void (*clear_event_idx)(struct pmu_hw_events *hw_events,
|
|
|
|
struct perf_event *event);
|
2011-05-19 09:07:57 +00:00
|
|
|
int (*set_event_filter)(struct hw_perf_event *evt,
|
|
|
|
struct perf_event_attr *attr);
|
2018-07-10 08:57:59 +00:00
|
|
|
u64 (*read_counter)(struct perf_event *event);
|
|
|
|
void (*write_counter)(struct perf_event *event, u64 val);
|
2012-07-30 11:00:02 +00:00
|
|
|
void (*start)(struct arm_pmu *);
|
|
|
|
void (*stop)(struct arm_pmu *);
|
2011-05-19 09:07:57 +00:00
|
|
|
void (*reset)(void *);
|
|
|
|
int (*map_event)(struct perf_event *event);
|
|
|
|
int num_events;
|
2016-01-14 04:36:26 +00:00
|
|
|
bool secure_access; /* 32-bit ARM only */
|
2018-10-05 12:28:07 +00:00
|
|
|
#define ARMV8_PMUV3_MAX_COMMON_EVENTS 0x40
|
2016-04-21 12:58:44 +00:00
|
|
|
DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
|
2018-10-05 12:28:07 +00:00
|
|
|
#define ARMV8_PMUV3_EXT_COMMON_EVENT_BASE 0x4000
|
|
|
|
DECLARE_BITMAP(pmceid_ext_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
|
2011-05-19 09:07:57 +00:00
|
|
|
struct platform_device *plat_device;
|
2014-05-13 18:36:31 +00:00
|
|
|
struct pmu_hw_events __percpu *hw_events;
|
2016-08-17 17:14:20 +00:00
|
|
|
struct hlist_node node;
|
2016-02-23 18:22:39 +00:00
|
|
|
struct notifier_block cpu_pm_nb;
|
2016-09-09 13:08:26 +00:00
|
|
|
/* the attr_groups array must be NULL-terminated */
|
|
|
|
const struct attribute_group *attr_groups[ARMPMU_NR_ATTR_GROUPS + 1];
|
2020-09-22 05:53:45 +00:00
|
|
|
/* store the PMMIR_EL1 to expose slots */
|
|
|
|
u64 reg_pmmir;
|
2017-04-11 08:39:55 +00:00
|
|
|
|
|
|
|
/* Only to be used by ACPI probing code */
|
|
|
|
unsigned long acpi_cpuid;
|
2011-05-19 09:07:57 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
|
|
|
|
|
2012-07-30 11:00:02 +00:00
|
|
|
u64 armpmu_event_update(struct perf_event *event);
|
2011-05-19 09:07:57 +00:00
|
|
|
|
2012-07-30 11:00:02 +00:00
|
|
|
int armpmu_event_set_period(struct perf_event *event);
|
2011-05-19 09:07:57 +00:00
|
|
|
|
2012-07-29 11:36:28 +00:00
|
|
|
int armpmu_map_event(struct perf_event *event,
|
|
|
|
const unsigned (*event_map)[PERF_COUNT_HW_MAX],
|
|
|
|
const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
|
|
|
|
[PERF_COUNT_HW_CACHE_OP_MAX]
|
|
|
|
[PERF_COUNT_HW_CACHE_RESULT_MAX],
|
|
|
|
u32 raw_event_mask);
|
|
|
|
|
2017-04-11 08:39:45 +00:00
|
|
|
typedef int (*armpmu_init_fn)(struct arm_pmu *);
|
|
|
|
|
2014-05-23 17:11:14 +00:00
|
|
|
struct pmu_probe_info {
|
|
|
|
unsigned int cpuid;
|
|
|
|
unsigned int mask;
|
2017-04-11 08:39:45 +00:00
|
|
|
armpmu_init_fn init;
|
2014-05-23 17:11:14 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
#define PMU_PROBE(_cpuid, _mask, _fn) \
|
|
|
|
{ \
|
|
|
|
.cpuid = (_cpuid), \
|
|
|
|
.mask = (_mask), \
|
|
|
|
.init = (_fn), \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define ARM_PMU_PROBE(_cpuid, _fn) \
|
|
|
|
PMU_PROBE(_cpuid, ARM_CPU_PART_MASK, _fn)
|
|
|
|
|
|
|
|
#define ARM_PMU_XSCALE_MASK ((0xff << 24) | ARM_CPU_XSCALE_ARCH_MASK)
|
|
|
|
|
|
|
|
#define XSCALE_PMU_PROBE(_version, _fn) \
|
|
|
|
PMU_PROBE(ARM_CPU_IMP_INTEL << 24 | _version, ARM_PMU_XSCALE_MASK, _fn)
|
|
|
|
|
2015-05-26 16:23:35 +00:00
|
|
|
int arm_pmu_device_probe(struct platform_device *pdev,
|
|
|
|
const struct of_device_id *of_table,
|
|
|
|
const struct pmu_probe_info *probe_table);
|
|
|
|
|
2017-04-11 08:39:55 +00:00
|
|
|
#ifdef CONFIG_ACPI
|
|
|
|
int arm_pmu_acpi_probe(armpmu_init_fn init_fn);
|
|
|
|
#else
|
|
|
|
static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; }
|
|
|
|
#endif
|
|
|
|
|
2021-09-19 13:09:49 +00:00
|
|
|
#ifdef CONFIG_KVM
|
|
|
|
void kvm_host_pmu_init(struct arm_pmu *pmu);
|
|
|
|
#else
|
|
|
|
#define kvm_host_pmu_init(x) do { } while(0)
|
|
|
|
#endif
|
|
|
|
|
2023-05-19 17:18:42 +00:00
|
|
|
bool arm_pmu_irq_is_nmi(void);
|
|
|
|
|
2017-04-11 08:39:53 +00:00
|
|
|
/* Internal functions only for core arm_pmu code */
|
|
|
|
struct arm_pmu *armpmu_alloc(void);
|
|
|
|
void armpmu_free(struct arm_pmu *pmu);
|
|
|
|
int armpmu_register(struct arm_pmu *pmu);
|
2017-10-09 16:09:05 +00:00
|
|
|
int armpmu_request_irq(int irq, int cpu);
|
|
|
|
void armpmu_free_irq(int irq, int cpu);
|
2017-04-11 08:39:53 +00:00
|
|
|
|
2016-09-14 22:32:31 +00:00
|
|
|
#define ARMV8_PMU_PDEV_NAME "armv8-pmu"
|
|
|
|
|
2015-07-06 11:23:53 +00:00
|
|
|
#endif /* CONFIG_ARM_PMU */
|
2011-05-19 09:07:57 +00:00
|
|
|
|
2019-06-26 21:37:17 +00:00
|
|
|
#define ARMV8_SPE_PDEV_NAME "arm,spe-v1"
|
2023-08-17 05:54:03 +00:00
|
|
|
#define ARMV8_TRBE_PDEV_NAME "arm,trbe"
|
2019-06-26 21:37:17 +00:00
|
|
|
|
2010-02-02 19:23:15 +00:00
|
|
|
#endif /* __ARM_PMU_H__ */
|