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33 lines
945 B
C
33 lines
945 B
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2020,2022 NXP
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*/
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#ifndef __PHY_LVDS_H_
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#define __PHY_LVDS_H_
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/**
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* struct phy_configure_opts_lvds - LVDS configuration set
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* @bits_per_lane_and_dclk_cycle: Number of bits per lane per differential
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* clock cycle.
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* @differential_clk_rate: Clock rate, in Hertz, of the LVDS
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* differential clock.
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* @lanes: Number of active, consecutive,
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* data lanes, starting from lane 0,
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* used for the transmissions.
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* @is_slave: Boolean, true if the phy is a slave
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* which works together with a master
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* phy to support dual link transmission,
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* otherwise a regular phy or a master phy.
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*
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* This structure is used to represent the configuration state of a LVDS phy.
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*/
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struct phy_configure_opts_lvds {
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unsigned int bits_per_lane_and_dclk_cycle;
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unsigned long differential_clk_rate;
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unsigned int lanes;
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bool is_slave;
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};
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#endif /* __PHY_LVDS_H_ */
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