2020-09-08 13:15:20 +00:00
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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// Copyright(c) 2015-2020 Intel Corporation.
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/*
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* Bandwidth management algorithm based on 2^n gears
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*
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*/
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/slab.h>
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#include <linux/soundwire/sdw.h>
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#include "bus.h"
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#define SDW_STRM_RATE_GROUPING 1
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struct sdw_group_params {
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unsigned int rate;
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int full_bw;
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int payload_bw;
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int hwidth;
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};
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struct sdw_group {
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unsigned int count;
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unsigned int max_size;
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unsigned int *rates;
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};
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struct sdw_transport_data {
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int hstart;
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int hstop;
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int block_offset;
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int sub_block_offset;
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};
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static void sdw_compute_slave_ports(struct sdw_master_runtime *m_rt,
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struct sdw_transport_data *t_data)
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{
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struct sdw_slave_runtime *s_rt = NULL;
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struct sdw_port_runtime *p_rt;
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int port_bo, sample_int;
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unsigned int rate, bps, ch = 0;
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unsigned int slave_total_ch;
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2020-09-20 19:32:05 +00:00
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struct sdw_bus_params *b_params = &m_rt->bus->params;
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2020-09-08 13:15:20 +00:00
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port_bo = t_data->block_offset;
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list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
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rate = m_rt->stream->params.rate;
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bps = m_rt->stream->params.bps;
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sample_int = (m_rt->bus->params.curr_dr_freq / rate);
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slave_total_ch = 0;
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list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
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ch = sdw_ch_mask_to_ch(p_rt->ch_mask);
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sdw_fill_xport_params(&p_rt->transport_params,
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p_rt->num, false,
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SDW_BLK_GRP_CNT_1,
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sample_int, port_bo, port_bo >> 8,
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t_data->hstart,
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t_data->hstop,
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2021-03-23 05:07:01 +00:00
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SDW_BLK_PKG_PER_PORT, 0x0);
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2020-09-08 13:15:20 +00:00
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sdw_fill_port_params(&p_rt->port_params,
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p_rt->num, bps,
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SDW_PORT_FLOW_MODE_ISOCH,
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2020-09-20 19:32:05 +00:00
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b_params->s_data_mode);
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2020-09-08 13:15:20 +00:00
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port_bo += bps * ch;
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slave_total_ch += ch;
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}
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if (m_rt->direction == SDW_DATA_DIR_TX &&
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m_rt->ch_count == slave_total_ch) {
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/*
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* Slave devices were configured to access all channels
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* of the stream, which indicates that they operate in
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* 'mirror mode'. Make sure we reset the port offset for
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* the next device in the list
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*/
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port_bo = t_data->block_offset;
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}
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}
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}
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static void sdw_compute_master_ports(struct sdw_master_runtime *m_rt,
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struct sdw_group_params *params,
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int port_bo, int hstop)
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{
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struct sdw_transport_data t_data = {0};
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struct sdw_port_runtime *p_rt;
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struct sdw_bus *bus = m_rt->bus;
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2020-09-20 19:32:05 +00:00
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struct sdw_bus_params *b_params = &bus->params;
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2020-09-08 13:15:20 +00:00
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int sample_int, hstart = 0;
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2021-03-23 05:07:01 +00:00
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unsigned int rate, bps, ch;
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2020-09-08 13:15:20 +00:00
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rate = m_rt->stream->params.rate;
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bps = m_rt->stream->params.bps;
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ch = m_rt->ch_count;
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sample_int = (bus->params.curr_dr_freq / rate);
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if (rate != params->rate)
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return;
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t_data.hstop = hstop;
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hstart = hstop - params->hwidth + 1;
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t_data.hstart = hstart;
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list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
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sdw_fill_xport_params(&p_rt->transport_params, p_rt->num,
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false, SDW_BLK_GRP_CNT_1, sample_int,
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port_bo, port_bo >> 8, hstart, hstop,
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2021-03-23 05:07:01 +00:00
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SDW_BLK_PKG_PER_PORT, 0x0);
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2020-09-08 13:15:20 +00:00
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sdw_fill_port_params(&p_rt->port_params,
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p_rt->num, bps,
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SDW_PORT_FLOW_MODE_ISOCH,
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2020-09-20 19:32:05 +00:00
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b_params->m_data_mode);
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2020-09-08 13:15:20 +00:00
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/* Check for first entry */
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if (!(p_rt == list_first_entry(&m_rt->port_list,
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struct sdw_port_runtime,
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port_node))) {
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port_bo += bps * ch;
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continue;
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}
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t_data.hstart = hstart;
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t_data.hstop = hstop;
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t_data.block_offset = port_bo;
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t_data.sub_block_offset = 0;
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port_bo += bps * ch;
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}
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sdw_compute_slave_ports(m_rt, &t_data);
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}
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static void _sdw_compute_port_params(struct sdw_bus *bus,
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struct sdw_group_params *params, int count)
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{
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2021-03-02 09:11:18 +00:00
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struct sdw_master_runtime *m_rt;
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2020-09-08 13:15:20 +00:00
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int hstop = bus->params.col - 1;
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int block_offset, port_bo, i;
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/* Run loop for all groups to compute transport parameters */
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for (i = 0; i < count; i++) {
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port_bo = 1;
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block_offset = 1;
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list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
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sdw_compute_master_ports(m_rt, ¶ms[i],
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port_bo, hstop);
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block_offset += m_rt->ch_count *
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m_rt->stream->params.bps;
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port_bo = block_offset;
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}
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hstop = hstop - params[i].hwidth;
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}
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}
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static int sdw_compute_group_params(struct sdw_bus *bus,
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struct sdw_group_params *params,
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int *rates, int count)
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{
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2021-03-02 09:11:18 +00:00
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struct sdw_master_runtime *m_rt;
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2020-09-08 13:15:20 +00:00
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int sel_col = bus->params.col;
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unsigned int rate, bps, ch;
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int i, column_needed = 0;
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/* Calculate bandwidth per group */
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for (i = 0; i < count; i++) {
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params[i].rate = rates[i];
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params[i].full_bw = bus->params.curr_dr_freq / params[i].rate;
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}
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list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
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rate = m_rt->stream->params.rate;
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bps = m_rt->stream->params.bps;
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ch = m_rt->ch_count;
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for (i = 0; i < count; i++) {
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if (rate == params[i].rate)
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params[i].payload_bw += bps * ch;
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}
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}
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for (i = 0; i < count; i++) {
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params[i].hwidth = (sel_col *
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params[i].payload_bw + params[i].full_bw - 1) /
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params[i].full_bw;
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column_needed += params[i].hwidth;
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}
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if (column_needed > sel_col - 1)
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return -EINVAL;
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return 0;
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}
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static int sdw_add_element_group_count(struct sdw_group *group,
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unsigned int rate)
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{
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int num = group->count;
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int i;
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for (i = 0; i <= num; i++) {
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if (rate == group->rates[i])
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break;
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if (i != num)
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continue;
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if (group->count >= group->max_size) {
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unsigned int *rates;
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group->max_size += 1;
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rates = krealloc(group->rates,
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(sizeof(int) * group->max_size),
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GFP_KERNEL);
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if (!rates)
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return -ENOMEM;
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group->rates = rates;
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}
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group->rates[group->count++] = rate;
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}
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return 0;
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}
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static int sdw_get_group_count(struct sdw_bus *bus,
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struct sdw_group *group)
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{
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struct sdw_master_runtime *m_rt;
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unsigned int rate;
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int ret = 0;
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group->count = 0;
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group->max_size = SDW_STRM_RATE_GROUPING;
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group->rates = kcalloc(group->max_size, sizeof(int), GFP_KERNEL);
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if (!group->rates)
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return -ENOMEM;
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list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
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rate = m_rt->stream->params.rate;
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if (m_rt == list_first_entry(&bus->m_rt_list,
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struct sdw_master_runtime,
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bus_node)) {
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group->rates[group->count++] = rate;
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} else {
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ret = sdw_add_element_group_count(group, rate);
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if (ret < 0) {
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kfree(group->rates);
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return ret;
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}
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}
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}
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return ret;
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}
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/**
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* sdw_compute_port_params: Compute transport and port parameters
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*
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* @bus: SDW Bus instance
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*/
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static int sdw_compute_port_params(struct sdw_bus *bus)
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{
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struct sdw_group_params *params = NULL;
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struct sdw_group group;
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int ret;
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ret = sdw_get_group_count(bus, &group);
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if (ret < 0)
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return ret;
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if (group.count == 0)
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goto out;
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params = kcalloc(group.count, sizeof(*params), GFP_KERNEL);
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if (!params) {
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ret = -ENOMEM;
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goto out;
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}
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/* Compute transport parameters for grouped streams */
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ret = sdw_compute_group_params(bus, params,
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&group.rates[0], group.count);
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if (ret < 0)
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goto free_params;
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_sdw_compute_port_params(bus, params, group.count);
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free_params:
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kfree(params);
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out:
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kfree(group.rates);
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return ret;
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}
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static int sdw_select_row_col(struct sdw_bus *bus, int clk_freq)
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{
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struct sdw_master_prop *prop = &bus->prop;
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int frame_int, frame_freq;
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int r, c;
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for (c = 0; c < SDW_FRAME_COLS; c++) {
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for (r = 0; r < SDW_FRAME_ROWS; r++) {
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if (sdw_rows[r] != prop->default_row ||
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sdw_cols[c] != prop->default_col)
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continue;
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frame_int = sdw_rows[r] * sdw_cols[c];
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frame_freq = clk_freq / frame_int;
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if ((clk_freq - (frame_freq * SDW_FRAME_CTRL_BITS)) <
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bus->params.bandwidth)
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continue;
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bus->params.row = sdw_rows[r];
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bus->params.col = sdw_cols[c];
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return 0;
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}
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}
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return -EINVAL;
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}
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/**
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* sdw_compute_bus_params: Compute bus parameters
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*
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* @bus: SDW Bus instance
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*/
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static int sdw_compute_bus_params(struct sdw_bus *bus)
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{
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unsigned int max_dr_freq, curr_dr_freq = 0;
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2020-09-23 08:32:35 +00:00
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struct sdw_master_prop *mstr_prop = &bus->prop;
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2020-09-08 13:15:20 +00:00
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int i, clk_values, ret;
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bool is_gear = false;
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u32 *clk_buf;
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if (mstr_prop->num_clk_gears) {
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clk_values = mstr_prop->num_clk_gears;
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clk_buf = mstr_prop->clk_gears;
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is_gear = true;
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} else if (mstr_prop->num_clk_freq) {
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clk_values = mstr_prop->num_clk_freq;
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clk_buf = mstr_prop->clk_freq;
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} else {
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clk_values = 1;
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clk_buf = NULL;
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}
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max_dr_freq = mstr_prop->max_clk_freq * SDW_DOUBLE_RATE_FACTOR;
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for (i = 0; i < clk_values; i++) {
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if (!clk_buf)
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curr_dr_freq = max_dr_freq;
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else
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curr_dr_freq = (is_gear) ?
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|
|
|
(max_dr_freq >> clk_buf[i]) :
|
|
|
|
clk_buf[i] * SDW_DOUBLE_RATE_FACTOR;
|
|
|
|
|
|
|
|
if (curr_dr_freq <= bus->params.bandwidth)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* TODO: Check all the Slave(s) port(s) audio modes and find
|
|
|
|
* whether given clock rate is supported with glitchless
|
|
|
|
* transition.
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
|
2021-05-11 05:49:45 +00:00
|
|
|
if (i == clk_values) {
|
|
|
|
dev_err(bus->dev, "%s: could not find clock value for bandwidth %d\n",
|
|
|
|
__func__, bus->params.bandwidth);
|
2020-09-08 13:15:20 +00:00
|
|
|
return -EINVAL;
|
2021-05-11 05:49:45 +00:00
|
|
|
}
|
2020-09-08 13:15:20 +00:00
|
|
|
|
|
|
|
ret = sdw_select_row_col(bus, curr_dr_freq);
|
2021-05-11 05:49:45 +00:00
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(bus->dev, "%s: could not find frame configuration for bus dr_freq %d\n",
|
|
|
|
__func__, curr_dr_freq);
|
2020-09-08 13:15:20 +00:00
|
|
|
return -EINVAL;
|
2021-05-11 05:49:45 +00:00
|
|
|
}
|
2020-09-08 13:15:20 +00:00
|
|
|
|
|
|
|
bus->params.curr_dr_freq = curr_dr_freq;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* sdw_compute_params: Compute bus, transport and port parameters
|
|
|
|
*
|
|
|
|
* @bus: SDW Bus instance
|
|
|
|
*/
|
|
|
|
int sdw_compute_params(struct sdw_bus *bus)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Computes clock frequency, frame shape and frame frequency */
|
|
|
|
ret = sdw_compute_bus_params(bus);
|
2021-05-11 05:49:45 +00:00
|
|
|
if (ret < 0)
|
2020-09-08 13:15:20 +00:00
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* Compute transport and port params */
|
|
|
|
ret = sdw_compute_port_params(bus);
|
|
|
|
if (ret < 0) {
|
2021-03-23 00:58:52 +00:00
|
|
|
dev_err(bus->dev, "Compute transport params failed: %d\n", ret);
|
2020-09-08 13:15:20 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(sdw_compute_params);
|
|
|
|
|
|
|
|
MODULE_LICENSE("Dual BSD/GPL");
|
|
|
|
MODULE_DESCRIPTION("SoundWire Generic Bandwidth Allocation");
|