2017-11-06 17:11:51 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2011-08-26 18:04:50 +00:00
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/*
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* Synopsys DesignWare 8250 driver.
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*
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* Copyright 2011 Picochip, Jamie Iles.
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2013-01-10 09:25:10 +00:00
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* Copyright 2013 Intel Corporation
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2011-08-26 18:04:50 +00:00
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*
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* The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
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* LCR is written whilst busy. If it is, then a busy detect interrupt is
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* raised, the LCR needs to be rewritten and the uart status register read.
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*/
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2022-06-30 09:38:16 +00:00
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#include <linux/clk.h>
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2018-02-08 21:59:56 +00:00
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#include <linux/delay.h>
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2011-08-26 18:04:50 +00:00
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#include <linux/device.h>
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#include <linux/io.h>
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2022-05-09 16:19:11 +00:00
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#include <linux/mod_devicetable.h>
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2011-08-26 18:04:50 +00:00
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#include <linux/module.h>
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2022-06-30 09:38:16 +00:00
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#include <linux/notifier.h>
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2011-08-26 18:04:50 +00:00
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#include <linux/platform_device.h>
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2022-06-30 09:38:16 +00:00
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#include <linux/pm_runtime.h>
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2022-04-22 18:06:08 +00:00
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#include <linux/property.h>
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2014-07-23 15:33:06 +00:00
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#include <linux/reset.h>
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2022-06-30 09:38:16 +00:00
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#include <linux/slab.h>
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#include <linux/workqueue.h>
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2011-08-26 18:04:50 +00:00
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2013-06-19 20:37:27 +00:00
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#include <asm/byteorder.h>
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2022-06-30 09:38:16 +00:00
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#include <linux/serial_8250.h>
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#include <linux/serial_reg.h>
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2019-08-06 09:43:17 +00:00
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#include "8250_dwlib.h"
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2013-01-10 09:25:12 +00:00
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2013-01-10 09:25:09 +00:00
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/* Offsets for the DesignWare specific registers */
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#define DW_UART_USR 0x1f /* UART Status Register */
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2022-04-22 18:06:14 +00:00
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#define DW_UART_DMASA 0xa8 /* DMA Software Ack */
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2013-01-10 09:25:09 +00:00
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2022-04-22 18:06:09 +00:00
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#define OCTEON_UART_USR 0x27 /* UART Status Register */
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2022-04-22 18:06:14 +00:00
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#define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */
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#define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */
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2016-11-10 18:07:56 +00:00
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/* DesignWare specific register fields */
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#define DW_UART_MCR_SIRE BIT(6)
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2013-01-10 09:25:09 +00:00
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2022-04-22 18:06:14 +00:00
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/* Renesas specific register fields */
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#define RZN1_UART_xDMACR_DMA_EN BIT(0)
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#define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1)
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#define RZN1_UART_xDMACR_4_WORD_BURST (1 << 1)
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2022-06-30 08:39:09 +00:00
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#define RZN1_UART_xDMACR_8_WORD_BURST (2 << 1)
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2022-04-22 18:06:14 +00:00
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#define RZN1_UART_xDMACR_BLK_SZ(x) ((x) << 3)
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2022-04-22 18:06:08 +00:00
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/* Quirks */
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#define DW_UART_QUIRK_OCTEON BIT(0)
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#define DW_UART_QUIRK_ARMADA_38X BIT(1)
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#define DW_UART_QUIRK_SKIP_SET_RATE BIT(2)
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2022-04-22 18:06:14 +00:00
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#define DW_UART_QUIRK_IS_DMA_FC BIT(3)
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2024-03-06 14:33:22 +00:00
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#define DW_UART_QUIRK_APMC0D08 BIT(4)
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2022-04-22 18:06:08 +00:00
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2020-07-23 00:33:57 +00:00
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static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb)
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{
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return container_of(nb, struct dw8250_data, clk_notifier);
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}
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static inline struct dw8250_data *work_to_dw8250_data(struct work_struct *work)
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{
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return container_of(work, struct dw8250_data, clk_work);
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}
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2013-08-16 20:50:15 +00:00
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static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
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{
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2019-08-06 09:43:17 +00:00
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struct dw8250_data *d = to_dw8250_data(p->private_data);
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2013-08-16 20:50:15 +00:00
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2015-02-27 00:35:57 +00:00
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/* Override any modem control signals if needed */
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if (offset == UART_MSR) {
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value |= d->msr_mask_on;
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value &= ~d->msr_mask_off;
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}
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2013-08-16 20:50:15 +00:00
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return value;
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}
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serial: 8250_dw: Improve unwritable LCR workaround
When configured with UART_16550_COMPATIBLE=NO or in versions prior to
the introduction of this option, the Designware UART will ignore writes
to the LCR if the UART is busy. The current workaround saves a copy of
the last written LCR and re-writes it in the ISR for a special interrupt
that is raised when a write was ignored.
Unfortunately, interrupts are typically disabled prior to performing a
sequence of register writes that include the LCR so the point at which
the retry occurs is too late. An example is serial8250_do_set_termios()
where an ignored LCR write results in the baud divisor not being set and
instead a garbage character is sent out the transmitter.
Furthermore, since serial_port_out() offers no way to indicate failure,
a serious effort must be made to ensure that the LCR is actually updated
before returning back to the caller. This is difficult, however, as a
UART that was busy during the first attempt is likely to still be busy
when a subsequent attempt is made unless some extra action is taken.
This updated workaround reads back the LCR after each write to confirm
that the new value was accepted by the hardware. Should the hardware
ignore a write, the TX/RX FIFOs are cleared and the receive buffer read
before attempting to rewrite the LCR out of the hope that doing so will
force the UART into an idle state. While this may seem unnecessarily
aggressive, writes to the LCR are used to change the baud rate, parity,
stop bit, or data length so the data that may be lost is likely not
important. Admittedly, this is far from ideal but it seems to be the
best that can be done given the hardware limitations.
Lastly, the revised workaround doesn't touch the LCR in the ISR, so it
avoids the possibility of a "serial8250: too much work for irq" lock up.
This problem is rare in real situations but can be reproduced easily by
wiring up two UARTs and running the following commands.
# stty -F /dev/ttyS1 echo
# stty -F /dev/ttyS2 echo
# cat /dev/ttyS1 &
[1] 375
# echo asdf > /dev/ttyS1
asdf
[ 27.700000] serial8250: too much work for irq96
[ 27.700000] serial8250: too much work for irq96
[ 27.710000] serial8250: too much work for irq96
[ 27.710000] serial8250: too much work for irq96
[ 27.720000] serial8250: too much work for irq96
[ 27.720000] serial8250: too much work for irq96
[ 27.730000] serial8250: too much work for irq96
[ 27.730000] serial8250: too much work for irq96
[ 27.740000] serial8250: too much work for irq96
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <matt.porter@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-10-01 17:18:08 +00:00
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static void dw8250_force_idle(struct uart_port *p)
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{
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2014-07-14 11:26:14 +00:00
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struct uart_8250_port *up = up_to_u8250p(p);
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2022-07-13 13:17:22 +00:00
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unsigned int lsr;
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2014-07-14 11:26:14 +00:00
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serial8250_clear_and_reinit_fifos(up);
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2022-07-13 13:17:22 +00:00
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/*
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* With PSLVERR_RESP_EN parameter set to 1, the device generates an
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* error response when an attempt to read an empty RBR with FIFO
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* enabled.
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*/
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if (up->fcr & UART_FCR_ENABLE_FIFO) {
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lsr = p->serial_in(p, UART_LSR);
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if (!(lsr & UART_LSR_DR))
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return;
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}
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serial: 8250_dw: Improve unwritable LCR workaround
When configured with UART_16550_COMPATIBLE=NO or in versions prior to
the introduction of this option, the Designware UART will ignore writes
to the LCR if the UART is busy. The current workaround saves a copy of
the last written LCR and re-writes it in the ISR for a special interrupt
that is raised when a write was ignored.
Unfortunately, interrupts are typically disabled prior to performing a
sequence of register writes that include the LCR so the point at which
the retry occurs is too late. An example is serial8250_do_set_termios()
where an ignored LCR write results in the baud divisor not being set and
instead a garbage character is sent out the transmitter.
Furthermore, since serial_port_out() offers no way to indicate failure,
a serious effort must be made to ensure that the LCR is actually updated
before returning back to the caller. This is difficult, however, as a
UART that was busy during the first attempt is likely to still be busy
when a subsequent attempt is made unless some extra action is taken.
This updated workaround reads back the LCR after each write to confirm
that the new value was accepted by the hardware. Should the hardware
ignore a write, the TX/RX FIFOs are cleared and the receive buffer read
before attempting to rewrite the LCR out of the hope that doing so will
force the UART into an idle state. While this may seem unnecessarily
aggressive, writes to the LCR are used to change the baud rate, parity,
stop bit, or data length so the data that may be lost is likely not
important. Admittedly, this is far from ideal but it seems to be the
best that can be done given the hardware limitations.
Lastly, the revised workaround doesn't touch the LCR in the ISR, so it
avoids the possibility of a "serial8250: too much work for irq" lock up.
This problem is rare in real situations but can be reproduced easily by
wiring up two UARTs and running the following commands.
# stty -F /dev/ttyS1 echo
# stty -F /dev/ttyS2 echo
# cat /dev/ttyS1 &
[1] 375
# echo asdf > /dev/ttyS1
asdf
[ 27.700000] serial8250: too much work for irq96
[ 27.700000] serial8250: too much work for irq96
[ 27.710000] serial8250: too much work for irq96
[ 27.710000] serial8250: too much work for irq96
[ 27.720000] serial8250: too much work for irq96
[ 27.720000] serial8250: too much work for irq96
[ 27.730000] serial8250: too much work for irq96
[ 27.730000] serial8250: too much work for irq96
[ 27.740000] serial8250: too much work for irq96
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <matt.porter@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-10-01 17:18:08 +00:00
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(void)p->serial_in(p, UART_RX);
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}
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2015-12-12 17:18:25 +00:00
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static void dw8250_check_lcr(struct uart_port *p, int value)
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2011-08-26 18:04:50 +00:00
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{
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2015-12-12 17:18:25 +00:00
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void __iomem *offset = p->membase + (UART_LCR << p->regshift);
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int tries = 1000;
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serial: 8250_dw: Improve unwritable LCR workaround
When configured with UART_16550_COMPATIBLE=NO or in versions prior to
the introduction of this option, the Designware UART will ignore writes
to the LCR if the UART is busy. The current workaround saves a copy of
the last written LCR and re-writes it in the ISR for a special interrupt
that is raised when a write was ignored.
Unfortunately, interrupts are typically disabled prior to performing a
sequence of register writes that include the LCR so the point at which
the retry occurs is too late. An example is serial8250_do_set_termios()
where an ignored LCR write results in the baud divisor not being set and
instead a garbage character is sent out the transmitter.
Furthermore, since serial_port_out() offers no way to indicate failure,
a serious effort must be made to ensure that the LCR is actually updated
before returning back to the caller. This is difficult, however, as a
UART that was busy during the first attempt is likely to still be busy
when a subsequent attempt is made unless some extra action is taken.
This updated workaround reads back the LCR after each write to confirm
that the new value was accepted by the hardware. Should the hardware
ignore a write, the TX/RX FIFOs are cleared and the receive buffer read
before attempting to rewrite the LCR out of the hope that doing so will
force the UART into an idle state. While this may seem unnecessarily
aggressive, writes to the LCR are used to change the baud rate, parity,
stop bit, or data length so the data that may be lost is likely not
important. Admittedly, this is far from ideal but it seems to be the
best that can be done given the hardware limitations.
Lastly, the revised workaround doesn't touch the LCR in the ISR, so it
avoids the possibility of a "serial8250: too much work for irq" lock up.
This problem is rare in real situations but can be reproduced easily by
wiring up two UARTs and running the following commands.
# stty -F /dev/ttyS1 echo
# stty -F /dev/ttyS2 echo
# cat /dev/ttyS1 &
[1] 375
# echo asdf > /dev/ttyS1
asdf
[ 27.700000] serial8250: too much work for irq96
[ 27.700000] serial8250: too much work for irq96
[ 27.710000] serial8250: too much work for irq96
[ 27.710000] serial8250: too much work for irq96
[ 27.720000] serial8250: too much work for irq96
[ 27.720000] serial8250: too much work for irq96
[ 27.730000] serial8250: too much work for irq96
[ 27.730000] serial8250: too much work for irq96
[ 27.740000] serial8250: too much work for irq96
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <matt.porter@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-10-01 17:18:08 +00:00
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/* Make sure LCR write wasn't ignored */
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2015-12-12 17:18:25 +00:00
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while (tries--) {
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unsigned int lcr = p->serial_in(p, UART_LCR);
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if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
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return;
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dw8250_force_idle(p);
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#ifdef CONFIG_64BIT
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2016-05-02 09:19:46 +00:00
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if (p->type == PORT_OCTEON)
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__raw_writeq(value & 0xff, offset);
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else
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#endif
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2015-12-12 17:18:25 +00:00
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if (p->iotype == UPIO_MEM32)
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writel(value, offset);
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2015-12-12 17:18:27 +00:00
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else if (p->iotype == UPIO_MEM32BE)
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iowrite32be(value, offset);
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2015-12-12 17:18:25 +00:00
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else
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writeb(value, offset);
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serial: 8250_dw: Improve unwritable LCR workaround
When configured with UART_16550_COMPATIBLE=NO or in versions prior to
the introduction of this option, the Designware UART will ignore writes
to the LCR if the UART is busy. The current workaround saves a copy of
the last written LCR and re-writes it in the ISR for a special interrupt
that is raised when a write was ignored.
Unfortunately, interrupts are typically disabled prior to performing a
sequence of register writes that include the LCR so the point at which
the retry occurs is too late. An example is serial8250_do_set_termios()
where an ignored LCR write results in the baud divisor not being set and
instead a garbage character is sent out the transmitter.
Furthermore, since serial_port_out() offers no way to indicate failure,
a serious effort must be made to ensure that the LCR is actually updated
before returning back to the caller. This is difficult, however, as a
UART that was busy during the first attempt is likely to still be busy
when a subsequent attempt is made unless some extra action is taken.
This updated workaround reads back the LCR after each write to confirm
that the new value was accepted by the hardware. Should the hardware
ignore a write, the TX/RX FIFOs are cleared and the receive buffer read
before attempting to rewrite the LCR out of the hope that doing so will
force the UART into an idle state. While this may seem unnecessarily
aggressive, writes to the LCR are used to change the baud rate, parity,
stop bit, or data length so the data that may be lost is likely not
important. Admittedly, this is far from ideal but it seems to be the
best that can be done given the hardware limitations.
Lastly, the revised workaround doesn't touch the LCR in the ISR, so it
avoids the possibility of a "serial8250: too much work for irq" lock up.
This problem is rare in real situations but can be reproduced easily by
wiring up two UARTs and running the following commands.
# stty -F /dev/ttyS1 echo
# stty -F /dev/ttyS2 echo
# cat /dev/ttyS1 &
[1] 375
# echo asdf > /dev/ttyS1
asdf
[ 27.700000] serial8250: too much work for irq96
[ 27.700000] serial8250: too much work for irq96
[ 27.710000] serial8250: too much work for irq96
[ 27.710000] serial8250: too much work for irq96
[ 27.720000] serial8250: too much work for irq96
[ 27.720000] serial8250: too much work for irq96
[ 27.730000] serial8250: too much work for irq96
[ 27.730000] serial8250: too much work for irq96
[ 27.740000] serial8250: too much work for irq96
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <matt.porter@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-10-01 17:18:08 +00:00
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}
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2015-12-12 17:18:25 +00:00
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/*
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* FIXME: this deadlocks if port->lock is already held
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* dev_err(p->dev, "Couldn't set LCR to %d\n", value);
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*/
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}
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2018-02-08 21:59:56 +00:00
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/* Returns once the transmitter is empty or we run out of retries */
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2018-03-16 00:42:00 +00:00
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static void dw8250_tx_wait_empty(struct uart_port *p)
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2018-02-08 21:59:56 +00:00
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{
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2022-06-08 09:54:31 +00:00
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struct uart_8250_port *up = up_to_u8250p(p);
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2018-03-16 00:42:00 +00:00
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unsigned int tries = 20000;
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unsigned int delay_threshold = tries - 1000;
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2018-02-08 21:59:56 +00:00
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unsigned int lsr;
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while (tries--) {
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lsr = readb (p->membase + (UART_LSR << p->regshift));
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2022-06-24 20:42:06 +00:00
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up->lsr_saved_flags |= lsr & up->lsr_save_mask;
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2022-06-08 09:54:31 +00:00
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2018-02-08 21:59:56 +00:00
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if (lsr & UART_LSR_TEMT)
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break;
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2018-03-16 00:42:00 +00:00
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|
|
/* The device is first given a chance to empty without delay,
|
|
|
|
|
* to avoid slowdowns at high bitrates. If after 1000 tries
|
|
|
|
|
* the buffer has still not emptied, allow more time for low-
|
|
|
|
|
* speed links. */
|
|
|
|
|
if (tries < delay_threshold)
|
|
|
|
|
udelay (1);
|
2018-02-08 21:59:56 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2022-06-28 13:42:31 +00:00
|
|
|
static void dw8250_serial_out(struct uart_port *p, int offset, int value)
|
2015-12-12 17:18:25 +00:00
|
|
|
{
|
2019-08-06 09:43:17 +00:00
|
|
|
struct dw8250_data *d = to_dw8250_data(p->private_data);
|
2015-12-12 17:18:25 +00:00
|
|
|
|
2018-03-16 00:42:00 +00:00
|
|
|
writeb(value, p->membase + (offset << p->regshift));
|
|
|
|
|
|
|
|
|
|
if (offset == UART_LCR && !d->uart_16550_compatible)
|
|
|
|
|
dw8250_check_lcr(p, value);
|
|
|
|
|
}
|
|
|
|
|
|
2022-06-28 13:42:31 +00:00
|
|
|
static void dw8250_serial_out38x(struct uart_port *p, int offset, int value)
|
2018-03-16 00:42:00 +00:00
|
|
|
{
|
2022-06-28 13:42:31 +00:00
|
|
|
/* Allow the TX to drain before we reconfigure */
|
|
|
|
|
if (offset == UART_LCR)
|
|
|
|
|
dw8250_tx_wait_empty(p);
|
2015-12-12 17:18:25 +00:00
|
|
|
|
2022-06-28 13:42:31 +00:00
|
|
|
dw8250_serial_out(p, offset, value);
|
2011-08-26 18:04:50 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
|
|
|
|
|
{
|
2013-08-16 20:50:15 +00:00
|
|
|
unsigned int value = readb(p->membase + (offset << p->regshift));
|
2011-08-26 18:04:50 +00:00
|
|
|
|
2013-08-16 20:50:15 +00:00
|
|
|
return dw8250_modify_msr(p, offset, value);
|
2011-08-26 18:04:50 +00:00
|
|
|
}
|
|
|
|
|
|
2014-11-14 14:26:19 +00:00
|
|
|
#ifdef CONFIG_64BIT
|
|
|
|
|
static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
|
2013-06-19 20:37:27 +00:00
|
|
|
{
|
2014-11-14 14:26:19 +00:00
|
|
|
unsigned int value;
|
|
|
|
|
|
|
|
|
|
value = (u8)__raw_readq(p->membase + (offset << p->regshift));
|
|
|
|
|
|
|
|
|
|
return dw8250_modify_msr(p, offset, value);
|
2013-06-19 20:37:27 +00:00
|
|
|
}
|
|
|
|
|
|
2014-11-14 14:26:19 +00:00
|
|
|
static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
|
|
|
|
|
{
|
2019-08-06 09:43:17 +00:00
|
|
|
struct dw8250_data *d = to_dw8250_data(p->private_data);
|
2015-12-12 17:18:25 +00:00
|
|
|
|
2014-11-14 14:26:19 +00:00
|
|
|
value &= 0xff;
|
|
|
|
|
__raw_writeq(value, p->membase + (offset << p->regshift));
|
|
|
|
|
/* Read back to ensure register write ordering. */
|
|
|
|
|
__raw_readq(p->membase + (UART_LCR << p->regshift));
|
|
|
|
|
|
2015-12-12 17:18:25 +00:00
|
|
|
if (offset == UART_LCR && !d->uart_16550_compatible)
|
|
|
|
|
dw8250_check_lcr(p, value);
|
2014-11-14 14:26:19 +00:00
|
|
|
}
|
|
|
|
|
#endif /* CONFIG_64BIT */
|
|
|
|
|
|
2011-08-26 18:04:50 +00:00
|
|
|
static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
|
|
|
|
|
{
|
2019-08-06 09:43:17 +00:00
|
|
|
struct dw8250_data *d = to_dw8250_data(p->private_data);
|
2015-12-12 17:18:25 +00:00
|
|
|
|
2013-08-16 20:50:15 +00:00
|
|
|
writel(value, p->membase + (offset << p->regshift));
|
serial: 8250_dw: Improve unwritable LCR workaround
When configured with UART_16550_COMPATIBLE=NO or in versions prior to
the introduction of this option, the Designware UART will ignore writes
to the LCR if the UART is busy. The current workaround saves a copy of
the last written LCR and re-writes it in the ISR for a special interrupt
that is raised when a write was ignored.
Unfortunately, interrupts are typically disabled prior to performing a
sequence of register writes that include the LCR so the point at which
the retry occurs is too late. An example is serial8250_do_set_termios()
where an ignored LCR write results in the baud divisor not being set and
instead a garbage character is sent out the transmitter.
Furthermore, since serial_port_out() offers no way to indicate failure,
a serious effort must be made to ensure that the LCR is actually updated
before returning back to the caller. This is difficult, however, as a
UART that was busy during the first attempt is likely to still be busy
when a subsequent attempt is made unless some extra action is taken.
This updated workaround reads back the LCR after each write to confirm
that the new value was accepted by the hardware. Should the hardware
ignore a write, the TX/RX FIFOs are cleared and the receive buffer read
before attempting to rewrite the LCR out of the hope that doing so will
force the UART into an idle state. While this may seem unnecessarily
aggressive, writes to the LCR are used to change the baud rate, parity,
stop bit, or data length so the data that may be lost is likely not
important. Admittedly, this is far from ideal but it seems to be the
best that can be done given the hardware limitations.
Lastly, the revised workaround doesn't touch the LCR in the ISR, so it
avoids the possibility of a "serial8250: too much work for irq" lock up.
This problem is rare in real situations but can be reproduced easily by
wiring up two UARTs and running the following commands.
# stty -F /dev/ttyS1 echo
# stty -F /dev/ttyS2 echo
# cat /dev/ttyS1 &
[1] 375
# echo asdf > /dev/ttyS1
asdf
[ 27.700000] serial8250: too much work for irq96
[ 27.700000] serial8250: too much work for irq96
[ 27.710000] serial8250: too much work for irq96
[ 27.710000] serial8250: too much work for irq96
[ 27.720000] serial8250: too much work for irq96
[ 27.720000] serial8250: too much work for irq96
[ 27.730000] serial8250: too much work for irq96
[ 27.730000] serial8250: too much work for irq96
[ 27.740000] serial8250: too much work for irq96
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <matt.porter@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-10-01 17:18:08 +00:00
|
|
|
|
2015-12-12 17:18:25 +00:00
|
|
|
if (offset == UART_LCR && !d->uart_16550_compatible)
|
|
|
|
|
dw8250_check_lcr(p, value);
|
2011-08-26 18:04:50 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
|
|
|
|
|
{
|
2013-08-16 20:50:15 +00:00
|
|
|
unsigned int value = readl(p->membase + (offset << p->regshift));
|
2011-08-26 18:04:50 +00:00
|
|
|
|
2013-08-16 20:50:15 +00:00
|
|
|
return dw8250_modify_msr(p, offset, value);
|
2011-08-26 18:04:50 +00:00
|
|
|
}
|
|
|
|
|
|
2015-12-12 17:18:26 +00:00
|
|
|
static void dw8250_serial_out32be(struct uart_port *p, int offset, int value)
|
|
|
|
|
{
|
2019-08-06 09:43:17 +00:00
|
|
|
struct dw8250_data *d = to_dw8250_data(p->private_data);
|
2015-12-12 17:18:26 +00:00
|
|
|
|
|
|
|
|
iowrite32be(value, p->membase + (offset << p->regshift));
|
|
|
|
|
|
|
|
|
|
if (offset == UART_LCR && !d->uart_16550_compatible)
|
|
|
|
|
dw8250_check_lcr(p, value);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset)
|
|
|
|
|
{
|
|
|
|
|
unsigned int value = ioread32be(p->membase + (offset << p->regshift));
|
|
|
|
|
|
|
|
|
|
return dw8250_modify_msr(p, offset, value);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2011-08-26 18:04:50 +00:00
|
|
|
static int dw8250_handle_irq(struct uart_port *p)
|
|
|
|
|
{
|
2017-02-06 23:30:00 +00:00
|
|
|
struct uart_8250_port *up = up_to_u8250p(p);
|
2019-08-06 09:43:17 +00:00
|
|
|
struct dw8250_data *d = to_dw8250_data(p->private_data);
|
2011-08-26 18:04:50 +00:00
|
|
|
unsigned int iir = p->serial_in(p, UART_IIR);
|
2022-04-22 18:06:12 +00:00
|
|
|
bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT;
|
2022-04-22 18:06:14 +00:00
|
|
|
unsigned int quirks = d->pdata->quirks;
|
2017-02-06 23:30:00 +00:00
|
|
|
unsigned int status;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* There are ways to get Designware-based UARTs into a state where
|
|
|
|
|
* they are asserting UART_IIR_RX_TIMEOUT but there is no actual
|
|
|
|
|
* data available. If we see such a case then we'll do a bogus
|
|
|
|
|
* read. If we don't do this then the "RX TIMEOUT" interrupt will
|
|
|
|
|
* fire forever.
|
|
|
|
|
*
|
|
|
|
|
* This problem has only been observed so far when not in DMA mode
|
|
|
|
|
* so we limit the workaround only to non-DMA mode.
|
|
|
|
|
*/
|
2022-04-22 18:06:12 +00:00
|
|
|
if (!up->dma && rx_timeout) {
|
2023-09-14 18:37:25 +00:00
|
|
|
uart_port_lock_irqsave(p, &flags);
|
2022-06-08 09:54:30 +00:00
|
|
|
status = serial_lsr_in(up);
|
2017-02-06 23:30:00 +00:00
|
|
|
|
|
|
|
|
if (!(status & (UART_LSR_DR | UART_LSR_BI)))
|
|
|
|
|
(void) p->serial_in(p, UART_RX);
|
|
|
|
|
|
2023-09-14 18:37:25 +00:00
|
|
|
uart_port_unlock_irqrestore(p, flags);
|
2017-02-06 23:30:00 +00:00
|
|
|
}
|
2011-08-26 18:04:50 +00:00
|
|
|
|
2022-04-22 18:06:14 +00:00
|
|
|
/* Manually stop the Rx DMA transfer when acting as flow controller */
|
|
|
|
|
if (quirks & DW_UART_QUIRK_IS_DMA_FC && up->dma && up->dma->rx_running && rx_timeout) {
|
2023-09-14 18:37:25 +00:00
|
|
|
uart_port_lock_irqsave(p, &flags);
|
2022-06-08 09:54:30 +00:00
|
|
|
status = serial_lsr_in(up);
|
2023-09-14 18:37:25 +00:00
|
|
|
uart_port_unlock_irqrestore(p, flags);
|
2022-06-28 09:01:28 +00:00
|
|
|
|
2022-04-22 18:06:14 +00:00
|
|
|
if (status & (UART_LSR_DR | UART_LSR_BI)) {
|
|
|
|
|
dw8250_writel_ext(p, RZN1_UART_RDMACR, 0);
|
|
|
|
|
dw8250_writel_ext(p, DW_UART_DMASA, 1);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2016-02-15 15:38:45 +00:00
|
|
|
if (serial8250_handle_irq(p, iir))
|
2011-08-26 18:04:50 +00:00
|
|
|
return 1;
|
2016-02-15 15:38:45 +00:00
|
|
|
|
|
|
|
|
if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
|
serial: 8250_dw: Improve unwritable LCR workaround
When configured with UART_16550_COMPATIBLE=NO or in versions prior to
the introduction of this option, the Designware UART will ignore writes
to the LCR if the UART is busy. The current workaround saves a copy of
the last written LCR and re-writes it in the ISR for a special interrupt
that is raised when a write was ignored.
Unfortunately, interrupts are typically disabled prior to performing a
sequence of register writes that include the LCR so the point at which
the retry occurs is too late. An example is serial8250_do_set_termios()
where an ignored LCR write results in the baud divisor not being set and
instead a garbage character is sent out the transmitter.
Furthermore, since serial_port_out() offers no way to indicate failure,
a serious effort must be made to ensure that the LCR is actually updated
before returning back to the caller. This is difficult, however, as a
UART that was busy during the first attempt is likely to still be busy
when a subsequent attempt is made unless some extra action is taken.
This updated workaround reads back the LCR after each write to confirm
that the new value was accepted by the hardware. Should the hardware
ignore a write, the TX/RX FIFOs are cleared and the receive buffer read
before attempting to rewrite the LCR out of the hope that doing so will
force the UART into an idle state. While this may seem unnecessarily
aggressive, writes to the LCR are used to change the baud rate, parity,
stop bit, or data length so the data that may be lost is likely not
important. Admittedly, this is far from ideal but it seems to be the
best that can be done given the hardware limitations.
Lastly, the revised workaround doesn't touch the LCR in the ISR, so it
avoids the possibility of a "serial8250: too much work for irq" lock up.
This problem is rare in real situations but can be reproduced easily by
wiring up two UARTs and running the following commands.
# stty -F /dev/ttyS1 echo
# stty -F /dev/ttyS2 echo
# cat /dev/ttyS1 &
[1] 375
# echo asdf > /dev/ttyS1
asdf
[ 27.700000] serial8250: too much work for irq96
[ 27.700000] serial8250: too much work for irq96
[ 27.710000] serial8250: too much work for irq96
[ 27.710000] serial8250: too much work for irq96
[ 27.720000] serial8250: too much work for irq96
[ 27.720000] serial8250: too much work for irq96
[ 27.730000] serial8250: too much work for irq96
[ 27.730000] serial8250: too much work for irq96
[ 27.740000] serial8250: too much work for irq96
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <matt.porter@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-10-01 17:18:08 +00:00
|
|
|
/* Clear the USR */
|
2022-04-22 18:06:09 +00:00
|
|
|
(void)p->serial_in(p, d->pdata->usr_reg);
|
2011-08-26 18:04:50 +00:00
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2020-07-23 00:33:57 +00:00
|
|
|
static void dw8250_clk_work_cb(struct work_struct *work)
|
|
|
|
|
{
|
|
|
|
|
struct dw8250_data *d = work_to_dw8250_data(work);
|
|
|
|
|
struct uart_8250_port *up;
|
|
|
|
|
unsigned long rate;
|
|
|
|
|
|
|
|
|
|
rate = clk_get_rate(d->clk);
|
|
|
|
|
if (rate <= 0)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
up = serial8250_get_port(d->data.line);
|
|
|
|
|
|
|
|
|
|
serial8250_update_uartclk(&up->port, rate);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dw8250_clk_notifier_cb(struct notifier_block *nb,
|
|
|
|
|
unsigned long event, void *data)
|
|
|
|
|
{
|
|
|
|
|
struct dw8250_data *d = clk_to_dw8250_data(nb);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* We have no choice but to defer the uartclk update due to two
|
|
|
|
|
* deadlocks. First one is caused by a recursive mutex lock which
|
|
|
|
|
* happens when clk_set_rate() is called from dw8250_set_termios().
|
|
|
|
|
* Second deadlock is more tricky and is caused by an inverted order of
|
|
|
|
|
* the clk and tty-port mutexes lock. It happens if clock rate change
|
|
|
|
|
* is requested asynchronously while set_termios() is executed between
|
|
|
|
|
* tty-port mutex lock and clk_set_rate() function invocation and
|
|
|
|
|
* vise-versa. Anyway if we didn't have the reference clock alteration
|
|
|
|
|
* in the dw8250_set_termios() method we wouldn't have needed this
|
|
|
|
|
* deferred event handling complication.
|
|
|
|
|
*/
|
|
|
|
|
if (event == POST_RATE_CHANGE) {
|
|
|
|
|
queue_work(system_unbound_wq, &d->clk_work);
|
|
|
|
|
return NOTIFY_OK;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
|
}
|
|
|
|
|
|
2013-04-10 13:58:28 +00:00
|
|
|
static void
|
|
|
|
|
dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
|
|
|
|
|
{
|
|
|
|
|
if (!state)
|
|
|
|
|
pm_runtime_get_sync(port->dev);
|
|
|
|
|
|
|
|
|
|
serial8250_do_pm(port, state, old);
|
|
|
|
|
|
|
|
|
|
if (state)
|
|
|
|
|
pm_runtime_put_sync_suspend(port->dev);
|
|
|
|
|
}
|
|
|
|
|
|
2014-06-05 13:51:40 +00:00
|
|
|
static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
|
2022-08-16 11:57:37 +00:00
|
|
|
const struct ktermios *old)
|
2014-06-05 13:51:40 +00:00
|
|
|
{
|
2020-07-23 00:33:56 +00:00
|
|
|
unsigned long newrate = tty_termios_baud_rate(termios) * 16;
|
2019-08-06 09:43:17 +00:00
|
|
|
struct dw8250_data *d = to_dw8250_data(p->private_data);
|
2017-03-09 06:41:16 +00:00
|
|
|
long rate;
|
2018-01-19 16:02:05 +00:00
|
|
|
int ret;
|
2014-06-05 13:51:40 +00:00
|
|
|
|
2020-07-23 00:33:56 +00:00
|
|
|
rate = clk_round_rate(d->clk, newrate);
|
2024-02-22 19:26:34 +00:00
|
|
|
if (rate > 0 && p->uartclk != rate) {
|
|
|
|
|
clk_disable_unprepare(d->clk);
|
2020-07-23 00:33:57 +00:00
|
|
|
/*
|
2021-10-15 11:14:22 +00:00
|
|
|
* Note that any clock-notifer worker will block in
|
|
|
|
|
* serial8250_update_uartclk() until we are done.
|
2020-07-23 00:33:57 +00:00
|
|
|
*/
|
2020-07-23 00:33:56 +00:00
|
|
|
ret = clk_set_rate(d->clk, newrate);
|
2021-10-15 11:14:22 +00:00
|
|
|
if (!ret)
|
|
|
|
|
p->uartclk = rate;
|
2024-02-22 19:26:34 +00:00
|
|
|
clk_prepare_enable(d->clk);
|
2020-07-23 00:33:55 +00:00
|
|
|
}
|
2018-01-19 16:02:05 +00:00
|
|
|
|
2021-10-05 13:30:25 +00:00
|
|
|
dw8250_do_set_termios(p, termios, old);
|
2014-06-05 13:51:40 +00:00
|
|
|
}
|
|
|
|
|
|
2016-11-10 18:07:56 +00:00
|
|
|
static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios)
|
|
|
|
|
{
|
|
|
|
|
struct uart_8250_port *up = up_to_u8250p(p);
|
|
|
|
|
unsigned int mcr = p->serial_in(p, UART_MCR);
|
|
|
|
|
|
|
|
|
|
if (up->capabilities & UART_CAP_IRDA) {
|
|
|
|
|
if (termios->c_line == N_IRDA)
|
|
|
|
|
mcr |= DW_UART_MCR_SIRE;
|
|
|
|
|
else
|
|
|
|
|
mcr &= ~DW_UART_MCR_SIRE;
|
|
|
|
|
|
|
|
|
|
p->serial_out(p, UART_MCR, mcr);
|
|
|
|
|
}
|
|
|
|
|
serial8250_do_set_ldisc(p, termios);
|
|
|
|
|
}
|
|
|
|
|
|
2015-09-21 11:17:30 +00:00
|
|
|
/*
|
|
|
|
|
* dw8250_fallback_dma_filter will prevent the UART from getting just any free
|
|
|
|
|
* channel on platforms that have DMA engines, but don't have any channels
|
|
|
|
|
* assigned to the UART.
|
|
|
|
|
*
|
|
|
|
|
* REVISIT: This is a work around for limitation in the DMA Engine API. Once the
|
|
|
|
|
* core problem is fixed, this function is no longer needed.
|
|
|
|
|
*/
|
|
|
|
|
static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param)
|
2013-09-05 14:34:54 +00:00
|
|
|
{
|
2014-08-19 17:29:22 +00:00
|
|
|
return false;
|
2013-09-05 14:34:54 +00:00
|
|
|
}
|
|
|
|
|
|
2015-05-26 12:59:32 +00:00
|
|
|
static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
|
|
|
|
|
{
|
dmaengine: idma64: Use actual device for DMA transfers
Intel IOMMU, when enabled, tries to find the domain of the device,
assuming it's a PCI one, during DMA operations, such as mapping or
unmapping. Since we are splitting the actual PCI device to couple of
children via MFD framework (see drivers/mfd/intel-lpss.c for details),
the DMA device appears to be a platform one, and thus not an actual one
that performs DMA. In a such situation IOMMU can't find or allocate
a proper domain for its operations. As a result, all DMA operations are
failed.
In order to fix this, supply parent of the platform device
to the DMA engine framework and fix filter functions accordingly.
We may rely on the fact that parent is a real PCI device, because no
other configuration is present in the wild.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> [for tty parts]
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-03-18 15:39:30 +00:00
|
|
|
return param == chan->device->dev;
|
2015-05-26 12:59:32 +00:00
|
|
|
}
|
|
|
|
|
|
2022-04-22 18:06:14 +00:00
|
|
|
static u32 dw8250_rzn1_get_dmacr_burst(int max_burst)
|
|
|
|
|
{
|
|
|
|
|
if (max_burst >= 8)
|
|
|
|
|
return RZN1_UART_xDMACR_8_WORD_BURST;
|
|
|
|
|
else if (max_burst >= 4)
|
|
|
|
|
return RZN1_UART_xDMACR_4_WORD_BURST;
|
|
|
|
|
else
|
|
|
|
|
return RZN1_UART_xDMACR_1_WORD_BURST;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dw8250_prepare_tx_dma(struct uart_8250_port *p)
|
|
|
|
|
{
|
|
|
|
|
struct uart_port *up = &p->port;
|
|
|
|
|
struct uart_8250_dma *dma = p->dma;
|
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
dw8250_writel_ext(up, RZN1_UART_TDMACR, 0);
|
|
|
|
|
val = dw8250_rzn1_get_dmacr_burst(dma->txconf.dst_maxburst) |
|
|
|
|
|
RZN1_UART_xDMACR_BLK_SZ(dma->tx_size) |
|
|
|
|
|
RZN1_UART_xDMACR_DMA_EN;
|
|
|
|
|
dw8250_writel_ext(up, RZN1_UART_TDMACR, val);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dw8250_prepare_rx_dma(struct uart_8250_port *p)
|
|
|
|
|
{
|
|
|
|
|
struct uart_port *up = &p->port;
|
|
|
|
|
struct uart_8250_dma *dma = p->dma;
|
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
dw8250_writel_ext(up, RZN1_UART_RDMACR, 0);
|
|
|
|
|
val = dw8250_rzn1_get_dmacr_burst(dma->rxconf.src_maxburst) |
|
|
|
|
|
RZN1_UART_xDMACR_BLK_SZ(dma->rx_size) |
|
|
|
|
|
RZN1_UART_xDMACR_DMA_EN;
|
|
|
|
|
dw8250_writel_ext(up, RZN1_UART_RDMACR, val);
|
|
|
|
|
}
|
|
|
|
|
|
2015-09-21 11:17:28 +00:00
|
|
|
static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
|
2013-01-10 09:25:10 +00:00
|
|
|
{
|
2024-03-06 14:33:22 +00:00
|
|
|
unsigned int quirks = data->pdata ? data->pdata->quirks : 0;
|
2021-10-05 13:45:28 +00:00
|
|
|
|
2015-09-21 11:17:28 +00:00
|
|
|
#ifdef CONFIG_64BIT
|
2024-03-06 14:33:22 +00:00
|
|
|
if (quirks & DW_UART_QUIRK_OCTEON) {
|
|
|
|
|
p->serial_in = dw8250_serial_inq;
|
|
|
|
|
p->serial_out = dw8250_serial_outq;
|
|
|
|
|
p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
|
|
|
|
|
p->type = PORT_OCTEON;
|
|
|
|
|
data->skip_autocfg = true;
|
|
|
|
|
}
|
2015-09-21 11:17:28 +00:00
|
|
|
#endif
|
2021-10-05 13:45:28 +00:00
|
|
|
|
2024-03-06 14:33:22 +00:00
|
|
|
if (quirks & DW_UART_QUIRK_ARMADA_38X)
|
|
|
|
|
p->serial_out = dw8250_serial_out38x;
|
|
|
|
|
if (quirks & DW_UART_QUIRK_SKIP_SET_RATE)
|
|
|
|
|
p->set_termios = dw8250_do_set_termios;
|
|
|
|
|
if (quirks & DW_UART_QUIRK_IS_DMA_FC) {
|
|
|
|
|
data->data.dma.txconf.device_fc = 1;
|
|
|
|
|
data->data.dma.rxconf.device_fc = 1;
|
|
|
|
|
data->data.dma.prepare_tx_dma = dw8250_prepare_tx_dma;
|
|
|
|
|
data->data.dma.prepare_rx_dma = dw8250_prepare_rx_dma;
|
|
|
|
|
}
|
|
|
|
|
if (quirks & DW_UART_QUIRK_APMC0D08) {
|
2018-03-01 11:41:29 +00:00
|
|
|
p->iotype = UPIO_MEM32;
|
|
|
|
|
p->regshift = 2;
|
|
|
|
|
p->serial_in = dw8250_serial_in32;
|
|
|
|
|
data->uart_16550_compatible = true;
|
2015-09-21 11:17:28 +00:00
|
|
|
}
|
2013-04-10 13:58:29 +00:00
|
|
|
|
dmaengine: idma64: Use actual device for DMA transfers
Intel IOMMU, when enabled, tries to find the domain of the device,
assuming it's a PCI one, during DMA operations, such as mapping or
unmapping. Since we are splitting the actual PCI device to couple of
children via MFD framework (see drivers/mfd/intel-lpss.c for details),
the DMA device appears to be a platform one, and thus not an actual one
that performs DMA. In a such situation IOMMU can't find or allocate
a proper domain for its operations. As a result, all DMA operations are
failed.
In order to fix this, supply parent of the platform device
to the DMA engine framework and fix filter functions accordingly.
We may rely on the fact that parent is a real PCI device, because no
other configuration is present in the wild.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> [for tty parts]
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-03-18 15:39:30 +00:00
|
|
|
/* Platforms with iDMA 64-bit */
|
2015-09-21 11:17:28 +00:00
|
|
|
if (platform_get_resource_byname(to_platform_device(p->dev),
|
2015-05-26 12:59:32 +00:00
|
|
|
IORESOURCE_MEM, "lpss_priv")) {
|
2019-08-06 09:43:17 +00:00
|
|
|
data->data.dma.rx_param = p->dev->parent;
|
|
|
|
|
data->data.dma.tx_param = p->dev->parent;
|
|
|
|
|
data->data.dma.fn = dw8250_idma_filter;
|
2015-05-26 12:59:32 +00:00
|
|
|
}
|
2013-01-10 09:25:10 +00:00
|
|
|
}
|
|
|
|
|
|
2022-05-09 17:21:28 +00:00
|
|
|
static void dw8250_reset_control_assert(void *data)
|
|
|
|
|
{
|
|
|
|
|
reset_control_assert(data);
|
|
|
|
|
}
|
|
|
|
|
|
2012-11-19 18:21:50 +00:00
|
|
|
static int dw8250_probe(struct platform_device *pdev)
|
2011-08-26 18:04:50 +00:00
|
|
|
{
|
2019-08-06 09:43:15 +00:00
|
|
|
struct uart_8250_port uart = {}, *up = &uart;
|
|
|
|
|
struct uart_port *p = &up->port;
|
2016-09-01 02:24:19 +00:00
|
|
|
struct device *dev = &pdev->dev;
|
2011-08-26 18:04:50 +00:00
|
|
|
struct dw8250_data *data;
|
2022-05-09 17:21:29 +00:00
|
|
|
struct resource *regs;
|
2013-01-10 09:25:08 +00:00
|
|
|
int err;
|
2011-08-26 18:04:50 +00:00
|
|
|
|
2022-05-09 17:21:29 +00:00
|
|
|
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
|
if (!regs)
|
|
|
|
|
return dev_err_probe(dev, -EINVAL, "no registers defined\n");
|
2011-08-26 18:04:50 +00:00
|
|
|
|
2015-09-21 11:17:24 +00:00
|
|
|
spin_lock_init(&p->lock);
|
|
|
|
|
p->handle_irq = dw8250_handle_irq;
|
|
|
|
|
p->pm = dw8250_do_pm;
|
|
|
|
|
p->type = PORT_8250;
|
2024-03-04 12:27:08 +00:00
|
|
|
p->flags = UPF_FIXED_PORT;
|
2016-09-01 02:24:19 +00:00
|
|
|
p->dev = dev;
|
2016-11-10 18:07:56 +00:00
|
|
|
p->set_ldisc = dw8250_set_ldisc;
|
2017-01-11 19:48:20 +00:00
|
|
|
p->set_termios = dw8250_set_termios;
|
2015-09-21 11:17:24 +00:00
|
|
|
|
2016-09-01 02:24:19 +00:00
|
|
|
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
|
2013-03-28 23:15:49 +00:00
|
|
|
if (!data)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
2019-08-06 09:43:17 +00:00
|
|
|
data->data.dma.fn = dw8250_fallback_dma_filter;
|
2022-04-22 18:06:08 +00:00
|
|
|
data->pdata = device_get_match_data(p->dev);
|
2019-08-06 09:43:17 +00:00
|
|
|
p->private_data = &data->data;
|
2015-03-18 10:55:13 +00:00
|
|
|
|
2016-09-01 02:24:19 +00:00
|
|
|
data->uart_16550_compatible = device_property_read_bool(dev,
|
2015-09-21 11:17:29 +00:00
|
|
|
"snps,uart-16550-compatible");
|
|
|
|
|
|
2024-03-04 12:27:08 +00:00
|
|
|
p->mapbase = regs->start;
|
|
|
|
|
p->mapsize = resource_size(regs);
|
2015-09-21 11:17:25 +00:00
|
|
|
|
2024-03-04 12:27:08 +00:00
|
|
|
p->membase = devm_ioremap(dev, p->mapbase, p->mapsize);
|
|
|
|
|
if (!p->membase)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
err = uart_read_port_properties(p);
|
|
|
|
|
/* no interrupt -> fall back to polling */
|
|
|
|
|
if (err == -ENXIO)
|
|
|
|
|
err = 0;
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
|
|
switch (p->iotype) {
|
|
|
|
|
case UPIO_MEM:
|
|
|
|
|
p->serial_in = dw8250_serial_in;
|
|
|
|
|
p->serial_out = dw8250_serial_out;
|
|
|
|
|
break;
|
|
|
|
|
case UPIO_MEM32:
|
2015-09-21 11:17:25 +00:00
|
|
|
p->serial_in = dw8250_serial_in32;
|
|
|
|
|
p->serial_out = dw8250_serial_out32;
|
2024-03-04 12:27:08 +00:00
|
|
|
break;
|
|
|
|
|
case UPIO_MEM32BE:
|
|
|
|
|
p->serial_in = dw8250_serial_in32be;
|
|
|
|
|
p->serial_out = dw8250_serial_out32be;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
return -ENODEV;
|
2015-09-21 11:17:25 +00:00
|
|
|
}
|
|
|
|
|
|
2016-09-01 02:24:19 +00:00
|
|
|
if (device_property_read_bool(dev, "dcd-override")) {
|
2015-09-21 11:17:25 +00:00
|
|
|
/* Always report DCD as active */
|
|
|
|
|
data->msr_mask_on |= UART_MSR_DCD;
|
|
|
|
|
data->msr_mask_off |= UART_MSR_DDCD;
|
|
|
|
|
}
|
|
|
|
|
|
2016-09-01 02:24:19 +00:00
|
|
|
if (device_property_read_bool(dev, "dsr-override")) {
|
2015-09-21 11:17:25 +00:00
|
|
|
/* Always report DSR as active */
|
|
|
|
|
data->msr_mask_on |= UART_MSR_DSR;
|
|
|
|
|
data->msr_mask_off |= UART_MSR_DDSR;
|
|
|
|
|
}
|
|
|
|
|
|
2016-09-01 02:24:19 +00:00
|
|
|
if (device_property_read_bool(dev, "cts-override")) {
|
2015-09-21 11:17:25 +00:00
|
|
|
/* Always report CTS as active */
|
|
|
|
|
data->msr_mask_on |= UART_MSR_CTS;
|
|
|
|
|
data->msr_mask_off |= UART_MSR_DCTS;
|
|
|
|
|
}
|
|
|
|
|
|
2016-09-01 02:24:19 +00:00
|
|
|
if (device_property_read_bool(dev, "ri-override")) {
|
2015-09-21 11:17:25 +00:00
|
|
|
/* Always report Ring indicator as inactive */
|
|
|
|
|
data->msr_mask_off |= UART_MSR_RI;
|
|
|
|
|
data->msr_mask_off |= UART_MSR_TERI;
|
|
|
|
|
}
|
|
|
|
|
|
2015-03-18 10:55:13 +00:00
|
|
|
/* If there is separate baudclk, get the rate from it. */
|
2023-09-19 19:55:13 +00:00
|
|
|
data->clk = devm_clk_get_optional_enabled(dev, "baudclk");
|
2019-09-25 16:26:17 +00:00
|
|
|
if (data->clk == NULL)
|
2023-09-19 19:55:13 +00:00
|
|
|
data->clk = devm_clk_get_optional_enabled(dev, NULL);
|
2019-09-25 16:26:17 +00:00
|
|
|
if (IS_ERR(data->clk))
|
2024-02-22 11:19:23 +00:00
|
|
|
return dev_err_probe(dev, PTR_ERR(data->clk),
|
|
|
|
|
"failed to get baudclk\n");
|
2019-09-25 16:26:17 +00:00
|
|
|
|
2020-07-23 00:33:57 +00:00
|
|
|
INIT_WORK(&data->clk_work, dw8250_clk_work_cb);
|
|
|
|
|
data->clk_notifier.notifier_call = dw8250_clk_notifier_cb;
|
|
|
|
|
|
2019-09-25 16:26:17 +00:00
|
|
|
if (data->clk)
|
|
|
|
|
p->uartclk = clk_get_rate(data->clk);
|
2014-06-16 13:25:17 +00:00
|
|
|
|
2015-03-18 10:55:13 +00:00
|
|
|
/* If no clock rate is defined, fail. */
|
2022-05-09 17:21:29 +00:00
|
|
|
if (!p->uartclk)
|
|
|
|
|
return dev_err_probe(dev, -EINVAL, "clock rate not defined\n");
|
2015-03-18 10:55:13 +00:00
|
|
|
|
2023-09-19 19:55:13 +00:00
|
|
|
data->pclk = devm_clk_get_optional_enabled(dev, "apb_pclk");
|
2022-05-09 17:21:28 +00:00
|
|
|
if (IS_ERR(data->pclk))
|
|
|
|
|
return PTR_ERR(data->pclk);
|
2019-09-25 16:26:17 +00:00
|
|
|
|
2017-07-19 15:26:28 +00:00
|
|
|
data->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
|
2022-05-09 17:21:28 +00:00
|
|
|
if (IS_ERR(data->rst))
|
|
|
|
|
return PTR_ERR(data->rst);
|
|
|
|
|
|
2017-03-15 11:31:50 +00:00
|
|
|
reset_control_deassert(data->rst);
|
2014-07-23 15:33:06 +00:00
|
|
|
|
2022-05-09 17:21:28 +00:00
|
|
|
err = devm_add_action_or_reset(dev, dw8250_reset_control_assert, data->rst);
|
|
|
|
|
if (err)
|
|
|
|
|
return err;
|
|
|
|
|
|
2015-09-21 11:17:28 +00:00
|
|
|
dw8250_quirks(p, data);
|
2011-08-26 18:04:50 +00:00
|
|
|
|
2015-09-21 11:17:29 +00:00
|
|
|
/* If the Busy Functionality is not implemented, don't handle it */
|
2015-12-12 17:18:25 +00:00
|
|
|
if (data->uart_16550_compatible)
|
2015-09-21 11:17:29 +00:00
|
|
|
p->handle_irq = NULL;
|
|
|
|
|
|
2015-09-21 11:17:27 +00:00
|
|
|
if (!data->skip_autocfg)
|
2015-09-21 11:17:32 +00:00
|
|
|
dw8250_setup_port(p);
|
2015-09-21 11:17:27 +00:00
|
|
|
|
2015-09-21 11:17:26 +00:00
|
|
|
/* If we have a valid fifosize, try hooking up DMA */
|
|
|
|
|
if (p->fifosize) {
|
2019-08-06 09:43:17 +00:00
|
|
|
data->data.dma.rxconf.src_maxburst = p->fifosize / 4;
|
|
|
|
|
data->data.dma.txconf.dst_maxburst = p->fifosize / 4;
|
|
|
|
|
up->dma = &data->data.dma;
|
2015-09-21 11:17:26 +00:00
|
|
|
}
|
|
|
|
|
|
2019-08-06 09:43:17 +00:00
|
|
|
data->data.line = serial8250_register_8250_port(up);
|
2022-05-09 17:21:28 +00:00
|
|
|
if (data->data.line < 0)
|
|
|
|
|
return data->data.line;
|
2011-08-26 18:04:50 +00:00
|
|
|
|
2020-09-23 16:19:50 +00:00
|
|
|
/*
|
|
|
|
|
* Some platforms may provide a reference clock shared between several
|
|
|
|
|
* devices. In this case any clock state change must be known to the
|
|
|
|
|
* UART port at least post factum.
|
|
|
|
|
*/
|
|
|
|
|
if (data->clk) {
|
|
|
|
|
err = clk_notifier_register(data->clk, &data->clk_notifier);
|
|
|
|
|
if (err)
|
2022-05-09 17:21:29 +00:00
|
|
|
return dev_err_probe(dev, err, "Failed to set the clock notifier\n");
|
|
|
|
|
queue_work(system_unbound_wq, &data->clk_work);
|
2020-09-23 16:19:50 +00:00
|
|
|
}
|
|
|
|
|
|
2011-08-26 18:04:50 +00:00
|
|
|
platform_set_drvdata(pdev, data);
|
|
|
|
|
|
2016-09-01 02:24:19 +00:00
|
|
|
pm_runtime_set_active(dev);
|
|
|
|
|
pm_runtime_enable(dev);
|
2013-04-10 13:58:28 +00:00
|
|
|
|
2011-08-26 18:04:50 +00:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2023-11-10 15:29:31 +00:00
|
|
|
static void dw8250_remove(struct platform_device *pdev)
|
2011-08-26 18:04:50 +00:00
|
|
|
{
|
|
|
|
|
struct dw8250_data *data = platform_get_drvdata(pdev);
|
2019-08-06 09:43:14 +00:00
|
|
|
struct device *dev = &pdev->dev;
|
2011-08-26 18:04:50 +00:00
|
|
|
|
2019-08-06 09:43:14 +00:00
|
|
|
pm_runtime_get_sync(dev);
|
2013-04-10 13:58:28 +00:00
|
|
|
|
2020-09-23 16:19:50 +00:00
|
|
|
if (data->clk) {
|
|
|
|
|
clk_notifier_unregister(data->clk, &data->clk_notifier);
|
|
|
|
|
|
|
|
|
|
flush_work(&data->clk_work);
|
|
|
|
|
}
|
|
|
|
|
|
2019-08-06 09:43:17 +00:00
|
|
|
serial8250_unregister_port(data->data.line);
|
2011-08-26 18:04:50 +00:00
|
|
|
|
2019-08-06 09:43:14 +00:00
|
|
|
pm_runtime_disable(dev);
|
|
|
|
|
pm_runtime_put_noidle(dev);
|
2011-08-26 18:04:50 +00:00
|
|
|
}
|
|
|
|
|
|
2013-04-10 13:58:28 +00:00
|
|
|
static int dw8250_suspend(struct device *dev)
|
2012-10-15 09:25:58 +00:00
|
|
|
{
|
2013-04-10 13:58:28 +00:00
|
|
|
struct dw8250_data *data = dev_get_drvdata(dev);
|
2012-10-15 09:25:58 +00:00
|
|
|
|
2019-08-06 09:43:17 +00:00
|
|
|
serial8250_suspend_port(data->data.line);
|
2012-10-15 09:25:58 +00:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2013-04-10 13:58:28 +00:00
|
|
|
static int dw8250_resume(struct device *dev)
|
2012-10-15 09:25:58 +00:00
|
|
|
{
|
2013-04-10 13:58:28 +00:00
|
|
|
struct dw8250_data *data = dev_get_drvdata(dev);
|
2012-10-15 09:25:58 +00:00
|
|
|
|
2019-08-06 09:43:17 +00:00
|
|
|
serial8250_resume_port(data->data.line);
|
2012-10-15 09:25:58 +00:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2013-04-10 13:58:28 +00:00
|
|
|
static int dw8250_runtime_suspend(struct device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct dw8250_data *data = dev_get_drvdata(dev);
|
|
|
|
|
|
2019-09-25 16:26:17 +00:00
|
|
|
clk_disable_unprepare(data->clk);
|
2013-04-10 13:58:28 +00:00
|
|
|
|
2019-09-25 16:26:17 +00:00
|
|
|
clk_disable_unprepare(data->pclk);
|
2014-06-16 13:25:17 +00:00
|
|
|
|
2013-04-10 13:58:28 +00:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dw8250_runtime_resume(struct device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct dw8250_data *data = dev_get_drvdata(dev);
|
|
|
|
|
|
2019-09-25 16:26:17 +00:00
|
|
|
clk_prepare_enable(data->pclk);
|
2014-06-16 13:25:17 +00:00
|
|
|
|
2019-09-25 16:26:17 +00:00
|
|
|
clk_prepare_enable(data->clk);
|
2013-04-10 13:58:28 +00:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct dev_pm_ops dw8250_pm_ops = {
|
2022-06-30 10:05:07 +00:00
|
|
|
SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
|
|
|
|
|
RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
|
2013-04-10 13:58:28 +00:00
|
|
|
};
|
|
|
|
|
|
2022-04-22 18:06:08 +00:00
|
|
|
static const struct dw8250_platform_data dw8250_dw_apb = {
|
2022-04-22 18:06:09 +00:00
|
|
|
.usr_reg = DW_UART_USR,
|
2022-04-22 18:06:08 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct dw8250_platform_data dw8250_octeon_3860_data = {
|
2022-04-22 18:06:09 +00:00
|
|
|
.usr_reg = OCTEON_UART_USR,
|
2022-04-22 18:06:08 +00:00
|
|
|
.quirks = DW_UART_QUIRK_OCTEON,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct dw8250_platform_data dw8250_armada_38x_data = {
|
2022-04-22 18:06:09 +00:00
|
|
|
.usr_reg = DW_UART_USR,
|
2022-04-22 18:06:08 +00:00
|
|
|
.quirks = DW_UART_QUIRK_ARMADA_38X,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
|
2022-04-22 18:06:09 +00:00
|
|
|
.usr_reg = DW_UART_USR,
|
2022-04-22 18:06:15 +00:00
|
|
|
.cpr_val = 0x00012f32,
|
|
|
|
|
.quirks = DW_UART_QUIRK_IS_DMA_FC,
|
2022-04-22 18:06:08 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
|
2022-04-22 18:06:09 +00:00
|
|
|
.usr_reg = DW_UART_USR,
|
2022-04-22 18:06:08 +00:00
|
|
|
.quirks = DW_UART_QUIRK_SKIP_SET_RATE,
|
|
|
|
|
};
|
|
|
|
|
|
2013-01-10 09:25:08 +00:00
|
|
|
static const struct of_device_id dw8250_of_match[] = {
|
2022-04-22 18:06:08 +00:00
|
|
|
{ .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
|
|
|
|
|
{ .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
|
|
|
|
|
{ .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
|
|
|
|
|
{ .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
|
|
|
|
|
{ .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
|
2011-08-26 18:04:50 +00:00
|
|
|
{ /* Sentinel */ }
|
|
|
|
|
};
|
2013-01-10 09:25:08 +00:00
|
|
|
MODULE_DEVICE_TABLE(of, dw8250_of_match);
|
2011-08-26 18:04:50 +00:00
|
|
|
|
2024-03-06 14:33:22 +00:00
|
|
|
static const struct dw8250_platform_data dw8250_apmc0d08 = {
|
|
|
|
|
.usr_reg = DW_UART_USR,
|
|
|
|
|
.quirks = DW_UART_QUIRK_APMC0D08,
|
|
|
|
|
};
|
|
|
|
|
|
2013-01-10 09:25:10 +00:00
|
|
|
static const struct acpi_device_id dw8250_acpi_match[] = {
|
2022-06-20 12:10:46 +00:00
|
|
|
{ "80860F0A", (kernel_ulong_t)&dw8250_dw_apb },
|
|
|
|
|
{ "8086228A", (kernel_ulong_t)&dw8250_dw_apb },
|
|
|
|
|
{ "AMD0020", (kernel_ulong_t)&dw8250_dw_apb },
|
|
|
|
|
{ "AMDI0020", (kernel_ulong_t)&dw8250_dw_apb },
|
|
|
|
|
{ "AMDI0022", (kernel_ulong_t)&dw8250_dw_apb },
|
2024-03-06 14:33:22 +00:00
|
|
|
{ "APMC0D08", (kernel_ulong_t)&dw8250_apmc0d08 },
|
2022-06-20 12:10:46 +00:00
|
|
|
{ "BRCM2032", (kernel_ulong_t)&dw8250_dw_apb },
|
|
|
|
|
{ "HISI0031", (kernel_ulong_t)&dw8250_dw_apb },
|
|
|
|
|
{ "INT33C4", (kernel_ulong_t)&dw8250_dw_apb },
|
|
|
|
|
{ "INT33C5", (kernel_ulong_t)&dw8250_dw_apb },
|
|
|
|
|
{ "INT3434", (kernel_ulong_t)&dw8250_dw_apb },
|
|
|
|
|
{ "INT3435", (kernel_ulong_t)&dw8250_dw_apb },
|
2023-12-05 19:55:24 +00:00
|
|
|
{ "INTC10EE", (kernel_ulong_t)&dw8250_dw_apb },
|
2013-01-10 09:25:10 +00:00
|
|
|
{ },
|
|
|
|
|
};
|
|
|
|
|
MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
|
|
|
|
|
|
2011-08-26 18:04:50 +00:00
|
|
|
static struct platform_driver dw8250_platform_driver = {
|
|
|
|
|
.driver = {
|
|
|
|
|
.name = "dw-apb-uart",
|
2022-06-30 10:05:07 +00:00
|
|
|
.pm = pm_ptr(&dw8250_pm_ops),
|
2013-01-10 09:25:08 +00:00
|
|
|
.of_match_table = dw8250_of_match,
|
2021-10-05 13:45:16 +00:00
|
|
|
.acpi_match_table = dw8250_acpi_match,
|
2011-08-26 18:04:50 +00:00
|
|
|
},
|
|
|
|
|
.probe = dw8250_probe,
|
2023-11-10 15:29:31 +00:00
|
|
|
.remove_new = dw8250_remove,
|
2011-08-26 18:04:50 +00:00
|
|
|
};
|
|
|
|
|
|
2011-11-28 11:22:15 +00:00
|
|
|
module_platform_driver(dw8250_platform_driver);
|
2011-08-26 18:04:50 +00:00
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Jamie Iles");
|
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
|
MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
|
2015-02-04 13:03:48 +00:00
|
|
|
MODULE_ALIAS("platform:dw-apb-uart");
|