2013-02-02 00:26:00 +00:00
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/*
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* Copyright (C) 2012 Invensense, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/i2c.h>
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2016-04-20 06:40:49 +00:00
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#include <linux/i2c-mux.h>
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2017-06-07 13:41:42 +00:00
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#include <linux/mutex.h>
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2013-02-02 00:26:00 +00:00
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#include <linux/iio/iio.h>
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#include <linux/iio/buffer.h>
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2016-02-12 11:44:43 +00:00
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#include <linux/regmap.h>
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2013-02-02 00:26:00 +00:00
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#include <linux/iio/sysfs.h>
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#include <linux/iio/kfifo_buf.h>
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#include <linux/iio/trigger.h>
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#include <linux/iio/triggered_buffer.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/platform_data/invensense_mpu6050.h>
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/**
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* struct inv_mpu6050_reg_map - Notable registers.
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* @sample_rate_div: Divider applied to gyro output rate.
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* @lpf: Configures internal low pass filter.
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2017-05-29 09:59:40 +00:00
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* @accel_lpf: Configures accelerometer low pass filter.
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2013-02-02 00:26:00 +00:00
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* @user_ctrl: Enables/resets the FIFO.
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* @fifo_en: Determines which data will appear in FIFO.
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* @gyro_config: gyro config register.
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* @accl_config: accel config register
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* @fifo_count_h: Upper byte of FIFO count.
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* @fifo_r_w: FIFO register.
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* @raw_gyro: Address of first gyro register.
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* @raw_accl: Address of first accel register.
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* @temperature: temperature register
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* @int_enable: Interrupt enable register.
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2018-04-20 16:54:00 +00:00
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* @int_status: Interrupt status register.
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2013-02-02 00:26:00 +00:00
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* @pwr_mgmt_1: Controls chip's power state and clock source.
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* @pwr_mgmt_2: Controls power state of individual sensors.
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2016-02-22 21:39:09 +00:00
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* @int_pin_cfg; Controls interrupt pin configuration.
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2016-02-22 21:39:10 +00:00
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* @accl_offset: Controls the accelerometer calibration offset.
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* @gyro_offset: Controls the gyroscope calibration offset.
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2013-02-02 00:26:00 +00:00
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*/
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struct inv_mpu6050_reg_map {
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u8 sample_rate_div;
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u8 lpf;
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2017-05-29 09:59:40 +00:00
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u8 accel_lpf;
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2013-02-02 00:26:00 +00:00
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u8 user_ctrl;
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u8 fifo_en;
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u8 gyro_config;
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u8 accl_config;
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u8 fifo_count_h;
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u8 fifo_r_w;
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u8 raw_gyro;
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u8 raw_accl;
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u8 temperature;
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u8 int_enable;
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2018-04-20 16:54:00 +00:00
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u8 int_status;
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2013-02-02 00:26:00 +00:00
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u8 pwr_mgmt_1;
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u8 pwr_mgmt_2;
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2014-12-05 22:52:09 +00:00
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u8 int_pin_cfg;
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2016-02-22 21:39:10 +00:00
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u8 accl_offset;
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u8 gyro_offset;
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2013-02-02 00:26:00 +00:00
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};
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/*device enum */
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enum inv_devices {
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INV_MPU6050,
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2014-03-19 16:56:00 +00:00
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INV_MPU6500,
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2016-02-12 11:44:45 +00:00
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INV_MPU6000,
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2016-04-20 13:15:13 +00:00
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INV_MPU9150,
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2017-03-26 11:11:00 +00:00
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INV_MPU9250,
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2018-04-02 22:42:00 +00:00
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INV_MPU9255,
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2016-06-30 17:06:34 +00:00
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INV_ICM20608,
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2013-02-02 00:26:00 +00:00
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INV_NUM_PARTS
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};
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/**
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* struct inv_mpu6050_chip_config - Cached chip configuration data.
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* @fsr: Full scale range.
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* @lpf: Digital low pass filter frequency.
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* @accl_fs: accel full scale range.
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* @accl_fifo_enable: enable accel data output
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* @gyro_fifo_enable: enable gyro data output
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* @fifo_rate: FIFO update rate.
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*/
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struct inv_mpu6050_chip_config {
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unsigned int fsr:2;
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unsigned int lpf:3;
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unsigned int accl_fs:2;
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unsigned int accl_fifo_enable:1;
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unsigned int gyro_fifo_enable:1;
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u16 fifo_rate;
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2018-04-30 10:14:11 +00:00
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u8 user_ctrl;
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2013-02-02 00:26:00 +00:00
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};
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/**
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* struct inv_mpu6050_hw - Other important hardware information.
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2016-04-20 13:15:11 +00:00
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* @whoami: Self identification byte from WHO_AM_I register
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2013-02-02 00:26:00 +00:00
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* @name: name of the chip.
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* @reg: register map of the chip.
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* @config: configuration of the chip.
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*/
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struct inv_mpu6050_hw {
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2016-04-20 13:15:11 +00:00
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u8 whoami;
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2013-02-02 00:26:00 +00:00
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u8 *name;
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const struct inv_mpu6050_reg_map *reg;
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const struct inv_mpu6050_chip_config *config;
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};
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/*
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* struct inv_mpu6050_state - Driver state variables.
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2017-06-07 13:41:42 +00:00
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* @lock: Chip access lock.
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2013-02-02 00:26:00 +00:00
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* @trig: IIO trigger.
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* @chip_config: Cached attribute information.
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* @reg: Map of important registers.
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* @hw: Other hardware-specific information.
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* @chip_type: chip type.
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2016-04-20 17:23:45 +00:00
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* @plat_data: platform data (deprecated in favor of @orientation).
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* @orientation: sensor chip orientation relative to main hardware.
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2016-02-12 11:44:44 +00:00
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* @map regmap pointer.
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* @irq interrupt number.
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2018-04-20 16:54:00 +00:00
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* @irq_mask the int_pin_cfg mask to configure interrupt type.
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2013-02-02 00:26:00 +00:00
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*/
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struct inv_mpu6050_state {
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2017-06-07 13:41:42 +00:00
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struct mutex lock;
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2013-02-02 00:26:00 +00:00
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struct iio_trigger *trig;
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struct inv_mpu6050_chip_config chip_config;
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const struct inv_mpu6050_reg_map *reg;
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const struct inv_mpu6050_hw *hw;
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enum inv_devices chip_type;
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2016-04-20 06:40:49 +00:00
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struct i2c_mux_core *muxc;
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iio: imu: inv_mpu6050: Create mux clients for ACPI
This is a follow up patches after adding i2c mux adapter for bypass
mode. Potentially many different types of sensor can be attached to
INVMPU6XXX device, which can be connected to main cpu i2c bus in
bypass mode.
Why do we need this?
The system ACPI table entry will consist of only one device for
INV6XXX, assuming that this driver will handle all connected sensors.
That is not true for the Linux driver. There are bunch of IIO drivers
for each sensors, hence we created a mux on this device. So to load
these additional drivers, we need to create i2c devices for them
in this driver using this mux adapter.
There are multiple options:
1. Use the auto detect feature, this needs a new i2c class for the
adapter as the existing HWMON class is not acceptable. Also the
autodetect has overhead of executing detect method for each
matching class of adapters.
This is a simple implementation. This option was previously submitted
with not a happy feedback.
2. Option is use ACPI magic and parse the configuration data. What
we need to create a i2c device at a minimum is address and a name.
Address can be obtained for secondary device in more or less in a
standard way from using _CRS element. But there is no name. To get
name we need to process proprietary vendor data. Not having name is
not fun, as you have to create device using the device name of
INVN6XXXX, respecting driver duplicate name space restriction.
Also each client driver needs to have this name in the id table.
Since multiple driver can be loaded, the driver should be able to
detect its presence and gracefully exit for the other client driver
to take it over.
So we use two step process:
- Use DMI to id platform and parse propritery data. This is not uncommon
for many x86 platform specific driver. We will get both name and address.
The change created necessary infrastructure to add more properitery vendor
data parsing.
- If DMI match fails, then create device on INV6XXX-client (we can't
create with same name as INV6XXX as it will cause duplicate name and driver
model will reject.) With this each client sensor driver which needs to get
attached via INV6XXXX, need this name in the id table and detect the
physical presence of sensor in probe and exit if not found.
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2015-01-30 22:25:45 +00:00
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struct i2c_client *mux_client;
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2014-12-05 22:52:09 +00:00
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unsigned int powerup_count;
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2013-02-02 00:26:00 +00:00
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struct inv_mpu6050_platform_data plat_data;
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2016-04-20 17:23:45 +00:00
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struct iio_mount_matrix orientation;
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2016-02-12 11:44:43 +00:00
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struct regmap *map;
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2016-02-12 11:44:44 +00:00
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int irq;
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2018-04-20 16:54:00 +00:00
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u8 irq_mask;
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2018-04-30 10:14:10 +00:00
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unsigned skip_samples;
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2013-02-02 00:26:00 +00:00
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};
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/*register and associated bit definition*/
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2016-02-22 21:39:10 +00:00
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#define INV_MPU6050_REG_ACCEL_OFFSET 0x06
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#define INV_MPU6050_REG_GYRO_OFFSET 0x13
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2013-02-02 00:26:00 +00:00
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#define INV_MPU6050_REG_SAMPLE_RATE_DIV 0x19
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#define INV_MPU6050_REG_CONFIG 0x1A
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#define INV_MPU6050_REG_GYRO_CONFIG 0x1B
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2014-05-02 09:34:00 +00:00
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#define INV_MPU6050_REG_ACCEL_CONFIG 0x1C
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2013-02-02 00:26:00 +00:00
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#define INV_MPU6050_REG_FIFO_EN 0x23
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2014-05-02 09:34:00 +00:00
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#define INV_MPU6050_BIT_ACCEL_OUT 0x08
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#define INV_MPU6050_BITS_GYRO_OUT 0x70
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2013-02-02 00:26:00 +00:00
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#define INV_MPU6050_REG_INT_ENABLE 0x38
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2014-05-02 09:34:00 +00:00
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#define INV_MPU6050_BIT_DATA_RDY_EN 0x01
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#define INV_MPU6050_BIT_DMP_INT_EN 0x02
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2013-02-02 00:26:00 +00:00
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#define INV_MPU6050_REG_RAW_ACCEL 0x3B
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#define INV_MPU6050_REG_TEMPERATURE 0x41
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#define INV_MPU6050_REG_RAW_GYRO 0x43
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2018-04-20 16:54:00 +00:00
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#define INV_MPU6050_REG_INT_STATUS 0x3A
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#define INV_MPU6050_BIT_RAW_DATA_RDY_INT 0x01
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2013-02-02 00:26:00 +00:00
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#define INV_MPU6050_REG_USER_CTRL 0x6A
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2014-05-02 09:34:00 +00:00
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#define INV_MPU6050_BIT_FIFO_RST 0x04
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#define INV_MPU6050_BIT_DMP_RST 0x08
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#define INV_MPU6050_BIT_I2C_MST_EN 0x20
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#define INV_MPU6050_BIT_FIFO_EN 0x40
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#define INV_MPU6050_BIT_DMP_EN 0x80
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2016-02-12 11:44:45 +00:00
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#define INV_MPU6050_BIT_I2C_IF_DIS 0x10
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2013-02-02 00:26:00 +00:00
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#define INV_MPU6050_REG_PWR_MGMT_1 0x6B
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2014-05-02 09:34:00 +00:00
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#define INV_MPU6050_BIT_H_RESET 0x80
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#define INV_MPU6050_BIT_SLEEP 0x40
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#define INV_MPU6050_BIT_CLK_MASK 0x7
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2013-02-02 00:26:00 +00:00
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#define INV_MPU6050_REG_PWR_MGMT_2 0x6C
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2014-05-02 09:34:00 +00:00
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#define INV_MPU6050_BIT_PWR_ACCL_STBY 0x38
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#define INV_MPU6050_BIT_PWR_GYRO_STBY 0x07
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2013-02-02 00:26:00 +00:00
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#define INV_MPU6050_REG_FIFO_COUNT_H 0x72
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#define INV_MPU6050_REG_FIFO_R_W 0x74
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#define INV_MPU6050_BYTES_PER_3AXIS_SENSOR 6
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#define INV_MPU6050_FIFO_COUNT_BYTE 2
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#define INV_MPU6050_FIFO_THRESHOLD 500
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2016-02-22 21:39:08 +00:00
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2016-02-22 21:39:10 +00:00
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/* mpu6500 registers */
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2017-05-29 09:59:40 +00:00
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#define INV_MPU6500_REG_ACCEL_CONFIG_2 0x1D
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2016-02-22 21:39:10 +00:00
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#define INV_MPU6500_REG_ACCEL_OFFSET 0x77
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2016-02-22 21:39:08 +00:00
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/* delay time in milliseconds */
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2013-02-02 00:26:00 +00:00
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#define INV_MPU6050_POWER_UP_TIME 100
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#define INV_MPU6050_TEMP_UP_TIME 100
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#define INV_MPU6050_SENSOR_UP_TIME 30
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2016-02-22 21:39:08 +00:00
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/* delay time in microseconds */
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#define INV_MPU6050_REG_UP_TIME_MIN 5000
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#define INV_MPU6050_REG_UP_TIME_MAX 10000
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2013-02-02 00:26:00 +00:00
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#define INV_MPU6050_TEMP_OFFSET 12421
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#define INV_MPU6050_TEMP_SCALE 2941
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#define INV_MPU6050_MAX_GYRO_FS_PARAM 3
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#define INV_MPU6050_MAX_ACCL_FS_PARAM 3
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#define INV_MPU6050_THREE_AXIS 3
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#define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT 3
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#define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT 3
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/* 6 + 6 round up and plus 8 */
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#define INV_MPU6050_OUTPUT_DATA_SIZE 24
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2014-12-05 22:52:09 +00:00
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#define INV_MPU6050_REG_INT_PIN_CFG 0x37
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2018-04-20 16:54:00 +00:00
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#define INV_MPU6050_ACTIVE_HIGH 0x00
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#define INV_MPU6050_ACTIVE_LOW 0x80
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/* enable level triggering */
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#define INV_MPU6050_LATCH_INT_EN 0x20
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2014-12-05 22:52:09 +00:00
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#define INV_MPU6050_BIT_BYPASS_EN 0x2
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2018-04-20 16:54:00 +00:00
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2014-12-05 22:52:09 +00:00
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2013-02-02 00:26:00 +00:00
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/* init parameters */
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#define INV_MPU6050_INIT_FIFO_RATE 50
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2014-05-02 09:34:00 +00:00
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#define INV_MPU6050_MAX_FIFO_RATE 1000
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#define INV_MPU6050_MIN_FIFO_RATE 4
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#define INV_MPU6050_ONE_K_HZ 1000
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2013-02-02 00:26:00 +00:00
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2016-04-20 13:15:11 +00:00
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#define INV_MPU6050_REG_WHOAMI 117
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#define INV_MPU6000_WHOAMI_VALUE 0x68
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#define INV_MPU6050_WHOAMI_VALUE 0x68
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#define INV_MPU6500_WHOAMI_VALUE 0x70
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2016-04-20 13:15:13 +00:00
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#define INV_MPU9150_WHOAMI_VALUE 0x68
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2017-03-26 11:11:00 +00:00
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#define INV_MPU9250_WHOAMI_VALUE 0x71
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2018-04-02 22:42:00 +00:00
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#define INV_MPU9255_WHOAMI_VALUE 0x73
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2016-06-30 17:06:34 +00:00
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#define INV_ICM20608_WHOAMI_VALUE 0xAF
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2016-04-20 13:15:11 +00:00
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2013-02-02 00:26:00 +00:00
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/* scan element definition */
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enum inv_mpu6050_scan {
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INV_MPU6050_SCAN_ACCL_X,
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INV_MPU6050_SCAN_ACCL_Y,
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INV_MPU6050_SCAN_ACCL_Z,
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INV_MPU6050_SCAN_GYRO_X,
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INV_MPU6050_SCAN_GYRO_Y,
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INV_MPU6050_SCAN_GYRO_Z,
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INV_MPU6050_SCAN_TIMESTAMP,
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|
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};
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|
|
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|
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enum inv_mpu6050_filter_e {
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INV_MPU6050_FILTER_256HZ_NOLPF2 = 0,
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|
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INV_MPU6050_FILTER_188HZ,
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|
|
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INV_MPU6050_FILTER_98HZ,
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INV_MPU6050_FILTER_42HZ,
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INV_MPU6050_FILTER_20HZ,
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INV_MPU6050_FILTER_10HZ,
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INV_MPU6050_FILTER_5HZ,
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INV_MPU6050_FILTER_2100HZ_NOLPF,
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|
|
|
NUM_MPU6050_FILTER
|
|
|
|
};
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|
|
|
|
|
|
|
/* IIO attribute address */
|
|
|
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enum INV_MPU6050_IIO_ATTR_ADDR {
|
|
|
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ATTR_GYRO_MATRIX,
|
|
|
|
ATTR_ACCL_MATRIX,
|
|
|
|
};
|
|
|
|
|
|
|
|
enum inv_mpu6050_accl_fs_e {
|
|
|
|
INV_MPU6050_FS_02G = 0,
|
|
|
|
INV_MPU6050_FS_04G,
|
|
|
|
INV_MPU6050_FS_08G,
|
|
|
|
INV_MPU6050_FS_16G,
|
|
|
|
NUM_ACCL_FSR
|
|
|
|
};
|
|
|
|
|
|
|
|
enum inv_mpu6050_fsr_e {
|
|
|
|
INV_MPU6050_FSR_250DPS = 0,
|
|
|
|
INV_MPU6050_FSR_500DPS,
|
|
|
|
INV_MPU6050_FSR_1000DPS,
|
|
|
|
INV_MPU6050_FSR_2000DPS,
|
|
|
|
NUM_MPU6050_FSR
|
|
|
|
};
|
|
|
|
|
|
|
|
enum inv_mpu6050_clock_sel_e {
|
|
|
|
INV_CLK_INTERNAL = 0,
|
|
|
|
INV_CLK_PLL,
|
|
|
|
NUM_CLK
|
|
|
|
};
|
|
|
|
|
|
|
|
irqreturn_t inv_mpu6050_read_fifo(int irq, void *p);
|
2018-04-20 16:54:00 +00:00
|
|
|
int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type);
|
2013-02-02 00:26:00 +00:00
|
|
|
int inv_reset_fifo(struct iio_dev *indio_dev);
|
|
|
|
int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask);
|
|
|
|
int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val);
|
|
|
|
int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on);
|
2016-02-12 11:44:44 +00:00
|
|
|
int inv_mpu_acpi_create_mux_client(struct i2c_client *client);
|
|
|
|
void inv_mpu_acpi_delete_mux_client(struct i2c_client *client);
|
2016-02-12 11:44:45 +00:00
|
|
|
int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
|
2016-02-22 21:39:11 +00:00
|
|
|
int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type);
|
2016-02-12 11:44:44 +00:00
|
|
|
extern const struct dev_pm_ops inv_mpu_pmops;
|