2014-10-08 08:55:02 +00:00
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/*
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* Copyright 2014 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/interrupt.h>
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#include <linux/workqueue.h>
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#include <linux/sched.h>
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#include <linux/wait.h>
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#include <linux/slab.h>
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#include <linux/pid.h>
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#include <asm/cputable.h>
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#include <misc/cxl.h>
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#include "cxl.h"
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2015-01-09 09:34:36 +00:00
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#include "trace.h"
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2014-10-08 08:55:02 +00:00
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/* XXX: This is implementation specific */
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static irqreturn_t handle_psl_slice_error(struct cxl_context *ctx, u64 dsisr, u64 errstat)
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{
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u64 fir1, fir2, fir_slice, serr, afu_debug;
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fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR1);
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fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR2);
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fir_slice = cxl_p1n_read(ctx->afu, CXL_PSL_FIR_SLICE_An);
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serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An);
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afu_debug = cxl_p1n_read(ctx->afu, CXL_AFU_DEBUG_An);
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dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%.16llx\n", errstat);
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dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%.16llx\n", fir1);
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dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%.16llx\n", fir2);
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dev_crit(&ctx->afu->dev, "PSL_SERR_An: 0x%.16llx\n", serr);
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dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%.16llx\n", fir_slice);
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dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%.16llx\n", afu_debug);
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dev_crit(&ctx->afu->dev, "STOPPING CXL TRACE\n");
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cxl_stop_trace(ctx->afu->adapter);
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return cxl_ack_irq(ctx, 0, errstat);
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}
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irqreturn_t cxl_slice_irq_err(int irq, void *data)
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{
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struct cxl_afu *afu = data;
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u64 fir_slice, errstat, serr, afu_debug;
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WARN(irq, "CXL SLICE ERROR interrupt %i\n", irq);
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serr = cxl_p1n_read(afu, CXL_PSL_SERR_An);
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fir_slice = cxl_p1n_read(afu, CXL_PSL_FIR_SLICE_An);
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errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
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afu_debug = cxl_p1n_read(afu, CXL_AFU_DEBUG_An);
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dev_crit(&afu->dev, "PSL_SERR_An: 0x%.16llx\n", serr);
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dev_crit(&afu->dev, "PSL_FIR_SLICE_An: 0x%.16llx\n", fir_slice);
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dev_crit(&afu->dev, "CXL_PSL_ErrStat_An: 0x%.16llx\n", errstat);
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dev_crit(&afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%.16llx\n", afu_debug);
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cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
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return IRQ_HANDLED;
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}
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static irqreturn_t cxl_irq_err(int irq, void *data)
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{
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struct cxl *adapter = data;
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u64 fir1, fir2, err_ivte;
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WARN(1, "CXL ERROR interrupt %i\n", irq);
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err_ivte = cxl_p1_read(adapter, CXL_PSL_ErrIVTE);
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dev_crit(&adapter->dev, "PSL_ErrIVTE: 0x%.16llx\n", err_ivte);
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dev_crit(&adapter->dev, "STOPPING CXL TRACE\n");
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cxl_stop_trace(adapter);
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fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1);
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fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2);
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dev_crit(&adapter->dev, "PSL_FIR1: 0x%.16llx\nPSL_FIR2: 0x%.16llx\n", fir1, fir2);
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return IRQ_HANDLED;
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}
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static irqreturn_t schedule_cxl_fault(struct cxl_context *ctx, u64 dsisr, u64 dar)
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{
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ctx->dsisr = dsisr;
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ctx->dar = dar;
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schedule_work(&ctx->fault_work);
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return IRQ_HANDLED;
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}
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2014-11-14 06:37:50 +00:00
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static irqreturn_t cxl_irq(int irq, void *data, struct cxl_irq_info *irq_info)
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2014-10-08 08:55:02 +00:00
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{
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struct cxl_context *ctx = data;
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u64 dsisr, dar;
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2014-11-14 06:37:50 +00:00
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dsisr = irq_info->dsisr;
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dar = irq_info->dar;
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2014-10-08 08:55:02 +00:00
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2015-01-09 09:34:36 +00:00
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trace_cxl_psl_irq(ctx, irq, dsisr, dar);
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2014-10-08 08:55:02 +00:00
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pr_devel("CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n", irq, ctx->pe, dsisr, dar);
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if (dsisr & CXL_PSL_DSISR_An_DS) {
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/*
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* We don't inherently need to sleep to handle this, but we do
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* need to get a ref to the task's mm, which we can't do from
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* irq context without the potential for a deadlock since it
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* takes the task_lock. An alternate option would be to keep a
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* reference to the task's mm the entire time it has cxl open,
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* but to do that we need to solve the issue where we hold a
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* ref to the mm, but the mm can hold a ref to the fd after an
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* mmap preventing anything from being cleaned up.
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*/
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pr_devel("Scheduling segment miss handling for later pe: %i\n", ctx->pe);
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return schedule_cxl_fault(ctx, dsisr, dar);
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}
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if (dsisr & CXL_PSL_DSISR_An_M)
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pr_devel("CXL interrupt: PTE not found\n");
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if (dsisr & CXL_PSL_DSISR_An_P)
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pr_devel("CXL interrupt: Storage protection violation\n");
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if (dsisr & CXL_PSL_DSISR_An_A)
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pr_devel("CXL interrupt: AFU lock access to write through or cache inhibited storage\n");
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if (dsisr & CXL_PSL_DSISR_An_S)
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pr_devel("CXL interrupt: Access was afu_wr or afu_zero\n");
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if (dsisr & CXL_PSL_DSISR_An_K)
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pr_devel("CXL interrupt: Access not permitted by virtual page class key protection\n");
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if (dsisr & CXL_PSL_DSISR_An_DM) {
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/*
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* In some cases we might be able to handle the fault
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* immediately if hash_page would succeed, but we still need
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* the task's mm, which as above we can't get without a lock
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*/
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pr_devel("Scheduling page fault handling for later pe: %i\n", ctx->pe);
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return schedule_cxl_fault(ctx, dsisr, dar);
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}
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if (dsisr & CXL_PSL_DSISR_An_ST)
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WARN(1, "CXL interrupt: Segment Table PTE not found\n");
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if (dsisr & CXL_PSL_DSISR_An_UR)
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pr_devel("CXL interrupt: AURP PTE not found\n");
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if (dsisr & CXL_PSL_DSISR_An_PE)
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2014-11-14 06:37:50 +00:00
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return handle_psl_slice_error(ctx, dsisr, irq_info->errstat);
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2014-10-08 08:55:02 +00:00
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if (dsisr & CXL_PSL_DSISR_An_AE) {
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2014-11-14 06:37:50 +00:00
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pr_devel("CXL interrupt: AFU Error %.llx\n", irq_info->afu_err);
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2014-10-08 08:55:02 +00:00
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if (ctx->pending_afu_err) {
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/*
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* This shouldn't happen - the PSL treats these errors
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* as fatal and will have reset the AFU, so there's not
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* much point buffering multiple AFU errors.
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* OTOH if we DO ever see a storm of these come in it's
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* probably best that we log them somewhere:
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*/
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dev_err_ratelimited(&ctx->afu->dev, "CXL AFU Error "
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"undelivered to pe %i: %.llx\n",
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2014-11-14 06:37:50 +00:00
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ctx->pe, irq_info->afu_err);
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2014-10-08 08:55:02 +00:00
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} else {
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spin_lock(&ctx->lock);
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2014-11-14 06:37:50 +00:00
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ctx->afu_err = irq_info->afu_err;
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2014-10-08 08:55:02 +00:00
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ctx->pending_afu_err = 1;
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spin_unlock(&ctx->lock);
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wake_up_all(&ctx->wq);
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}
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cxl_ack_irq(ctx, CXL_PSL_TFC_An_A, 0);
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}
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if (dsisr & CXL_PSL_DSISR_An_OC)
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pr_devel("CXL interrupt: OS Context Warning\n");
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WARN(1, "Unhandled CXL PSL IRQ\n");
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return IRQ_HANDLED;
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}
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2014-11-14 06:37:50 +00:00
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static irqreturn_t fail_psl_irq(struct cxl_afu *afu, struct cxl_irq_info *irq_info)
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{
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if (irq_info->dsisr & CXL_PSL_DSISR_TRANS)
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cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
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else
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cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
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return IRQ_HANDLED;
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}
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2014-10-08 08:55:02 +00:00
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static irqreturn_t cxl_irq_multiplexed(int irq, void *data)
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{
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struct cxl_afu *afu = data;
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struct cxl_context *ctx;
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2014-11-14 06:37:50 +00:00
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struct cxl_irq_info irq_info;
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2014-10-08 08:55:02 +00:00
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int ph = cxl_p2n_read(afu, CXL_PSL_PEHandle_An) & 0xffff;
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int ret;
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2014-11-14 06:37:50 +00:00
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if ((ret = cxl_get_irq(afu, &irq_info))) {
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WARN(1, "Unable to get CXL IRQ Info: %i\n", ret);
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return fail_psl_irq(afu, &irq_info);
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}
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2014-10-08 08:55:02 +00:00
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rcu_read_lock();
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ctx = idr_find(&afu->contexts_idr, ph);
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if (ctx) {
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2014-11-14 06:37:50 +00:00
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ret = cxl_irq(irq, ctx, &irq_info);
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2014-10-08 08:55:02 +00:00
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rcu_read_unlock();
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return ret;
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}
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rcu_read_unlock();
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2014-11-14 06:37:50 +00:00
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WARN(1, "Unable to demultiplex CXL PSL IRQ for PE %i DSISR %.16llx DAR"
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" %.16llx\n(Possible AFU HW issue - was a term/remove acked"
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" with outstanding transactions?)\n", ph, irq_info.dsisr,
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irq_info.dar);
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return fail_psl_irq(afu, &irq_info);
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2014-10-08 08:55:02 +00:00
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}
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static irqreturn_t cxl_irq_afu(int irq, void *data)
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{
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struct cxl_context *ctx = data;
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irq_hw_number_t hwirq = irqd_to_hwirq(irq_get_irq_data(irq));
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int irq_off, afu_irq = 1;
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__u16 range;
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int r;
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for (r = 1; r < CXL_IRQ_RANGES; r++) {
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irq_off = hwirq - ctx->irqs.offset[r];
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range = ctx->irqs.range[r];
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if (irq_off >= 0 && irq_off < range) {
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afu_irq += irq_off;
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break;
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}
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afu_irq += range;
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}
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if (unlikely(r >= CXL_IRQ_RANGES)) {
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WARN(1, "Recieved AFU IRQ out of range for pe %i (virq %i hwirq %lx)\n",
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ctx->pe, irq, hwirq);
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return IRQ_HANDLED;
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}
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2015-01-09 09:34:36 +00:00
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trace_cxl_afu_irq(ctx, afu_irq, irq, hwirq);
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2014-10-08 08:55:02 +00:00
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pr_devel("Received AFU interrupt %i for pe: %i (virq %i hwirq %lx)\n",
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afu_irq, ctx->pe, irq, hwirq);
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if (unlikely(!ctx->irq_bitmap)) {
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WARN(1, "Recieved AFU IRQ for context with no IRQ bitmap\n");
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return IRQ_HANDLED;
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}
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spin_lock(&ctx->lock);
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set_bit(afu_irq - 1, ctx->irq_bitmap);
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ctx->pending_irq = true;
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spin_unlock(&ctx->lock);
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wake_up_all(&ctx->wq);
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return IRQ_HANDLED;
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}
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unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq,
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2014-11-14 07:09:28 +00:00
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irq_handler_t handler, void *cookie, const char *name)
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2014-10-08 08:55:02 +00:00
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{
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unsigned int virq;
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int result;
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/* IRQ Domain? */
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virq = irq_create_mapping(NULL, hwirq);
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if (!virq) {
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dev_warn(&adapter->dev, "cxl_map_irq: irq_create_mapping failed\n");
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return 0;
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}
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cxl_setup_irq(adapter, hwirq, virq);
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pr_devel("hwirq %#lx mapped to virq %u\n", hwirq, virq);
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2014-11-14 07:09:28 +00:00
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result = request_irq(virq, handler, 0, name, cookie);
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2014-10-08 08:55:02 +00:00
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if (result) {
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dev_warn(&adapter->dev, "cxl_map_irq: request_irq failed: %i\n", result);
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return 0;
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}
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return virq;
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}
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void cxl_unmap_irq(unsigned int virq, void *cookie)
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{
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free_irq(virq, cookie);
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irq_dispose_mapping(virq);
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}
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static int cxl_register_one_irq(struct cxl *adapter,
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irq_handler_t handler,
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void *cookie,
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irq_hw_number_t *dest_hwirq,
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2014-11-14 07:09:28 +00:00
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unsigned int *dest_virq,
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const char *name)
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2014-10-08 08:55:02 +00:00
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{
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int hwirq, virq;
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if ((hwirq = cxl_alloc_one_irq(adapter)) < 0)
|
|
|
|
return hwirq;
|
|
|
|
|
2014-11-14 07:09:28 +00:00
|
|
|
if (!(virq = cxl_map_irq(adapter, hwirq, handler, cookie, name)))
|
2014-10-08 08:55:02 +00:00
|
|
|
goto err;
|
|
|
|
|
|
|
|
*dest_hwirq = hwirq;
|
|
|
|
*dest_virq = virq;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err:
|
|
|
|
cxl_release_one_irq(adapter, hwirq);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
int cxl_register_psl_err_irq(struct cxl *adapter)
|
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
|
2014-11-14 07:09:28 +00:00
|
|
|
adapter->irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err",
|
|
|
|
dev_name(&adapter->dev));
|
|
|
|
if (!adapter->irq_name)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2014-10-08 08:55:02 +00:00
|
|
|
if ((rc = cxl_register_one_irq(adapter, cxl_irq_err, adapter,
|
|
|
|
&adapter->err_hwirq,
|
2014-11-14 07:09:28 +00:00
|
|
|
&adapter->err_virq,
|
|
|
|
adapter->irq_name))) {
|
|
|
|
kfree(adapter->irq_name);
|
|
|
|
adapter->irq_name = NULL;
|
2014-10-08 08:55:02 +00:00
|
|
|
return rc;
|
2014-11-14 07:09:28 +00:00
|
|
|
}
|
2014-10-08 08:55:02 +00:00
|
|
|
|
|
|
|
cxl_p1_write(adapter, CXL_PSL_ErrIVTE, adapter->err_hwirq & 0xffff);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void cxl_release_psl_err_irq(struct cxl *adapter)
|
|
|
|
{
|
|
|
|
cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000);
|
|
|
|
cxl_unmap_irq(adapter->err_virq, adapter);
|
|
|
|
cxl_release_one_irq(adapter, adapter->err_hwirq);
|
2014-11-14 07:09:28 +00:00
|
|
|
kfree(adapter->irq_name);
|
2014-10-08 08:55:02 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int cxl_register_serr_irq(struct cxl_afu *afu)
|
|
|
|
{
|
|
|
|
u64 serr;
|
|
|
|
int rc;
|
|
|
|
|
2014-11-14 07:09:28 +00:00
|
|
|
afu->err_irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err",
|
|
|
|
dev_name(&afu->dev));
|
|
|
|
if (!afu->err_irq_name)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2014-10-08 08:55:02 +00:00
|
|
|
if ((rc = cxl_register_one_irq(afu->adapter, cxl_slice_irq_err, afu,
|
|
|
|
&afu->serr_hwirq,
|
2014-11-14 07:09:28 +00:00
|
|
|
&afu->serr_virq, afu->err_irq_name))) {
|
|
|
|
kfree(afu->err_irq_name);
|
|
|
|
afu->err_irq_name = NULL;
|
2014-10-08 08:55:02 +00:00
|
|
|
return rc;
|
2014-11-14 07:09:28 +00:00
|
|
|
}
|
2014-10-08 08:55:02 +00:00
|
|
|
|
|
|
|
serr = cxl_p1n_read(afu, CXL_PSL_SERR_An);
|
|
|
|
serr = (serr & 0x00ffffffffff0000ULL) | (afu->serr_hwirq & 0xffff);
|
|
|
|
cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void cxl_release_serr_irq(struct cxl_afu *afu)
|
|
|
|
{
|
|
|
|
cxl_p1n_write(afu, CXL_PSL_SERR_An, 0x0000000000000000);
|
|
|
|
cxl_unmap_irq(afu->serr_virq, afu);
|
|
|
|
cxl_release_one_irq(afu->adapter, afu->serr_hwirq);
|
2014-11-14 07:09:28 +00:00
|
|
|
kfree(afu->err_irq_name);
|
2014-10-08 08:55:02 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int cxl_register_psl_irq(struct cxl_afu *afu)
|
|
|
|
{
|
2014-11-14 07:09:28 +00:00
|
|
|
int rc;
|
|
|
|
|
|
|
|
afu->psl_irq_name = kasprintf(GFP_KERNEL, "cxl-%s",
|
|
|
|
dev_name(&afu->dev));
|
|
|
|
if (!afu->psl_irq_name)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
if ((rc = cxl_register_one_irq(afu->adapter, cxl_irq_multiplexed, afu,
|
|
|
|
&afu->psl_hwirq, &afu->psl_virq,
|
|
|
|
afu->psl_irq_name))) {
|
|
|
|
kfree(afu->psl_irq_name);
|
|
|
|
afu->psl_irq_name = NULL;
|
|
|
|
}
|
|
|
|
return rc;
|
2014-10-08 08:55:02 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void cxl_release_psl_irq(struct cxl_afu *afu)
|
|
|
|
{
|
|
|
|
cxl_unmap_irq(afu->psl_virq, afu);
|
|
|
|
cxl_release_one_irq(afu->adapter, afu->psl_hwirq);
|
2014-11-14 07:09:28 +00:00
|
|
|
kfree(afu->psl_irq_name);
|
|
|
|
}
|
|
|
|
|
|
|
|
void afu_irq_name_free(struct cxl_context *ctx)
|
|
|
|
{
|
|
|
|
struct cxl_irq_name *irq_name, *tmp;
|
|
|
|
|
|
|
|
list_for_each_entry_safe(irq_name, tmp, &ctx->irq_names, list) {
|
|
|
|
kfree(irq_name->name);
|
|
|
|
list_del(&irq_name->list);
|
|
|
|
kfree(irq_name);
|
|
|
|
}
|
2014-10-08 08:55:02 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int afu_register_irqs(struct cxl_context *ctx, u32 count)
|
|
|
|
{
|
|
|
|
irq_hw_number_t hwirq;
|
2014-11-14 07:09:28 +00:00
|
|
|
int rc, r, i, j = 1;
|
|
|
|
struct cxl_irq_name *irq_name;
|
2014-10-08 08:55:02 +00:00
|
|
|
|
|
|
|
if ((rc = cxl_alloc_irq_ranges(&ctx->irqs, ctx->afu->adapter, count)))
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
/* Multiplexed PSL Interrupt */
|
|
|
|
ctx->irqs.offset[0] = ctx->afu->psl_hwirq;
|
|
|
|
ctx->irqs.range[0] = 1;
|
|
|
|
|
|
|
|
ctx->irq_count = count;
|
|
|
|
ctx->irq_bitmap = kcalloc(BITS_TO_LONGS(count),
|
|
|
|
sizeof(*ctx->irq_bitmap), GFP_KERNEL);
|
|
|
|
if (!ctx->irq_bitmap)
|
|
|
|
return -ENOMEM;
|
2014-11-14 07:09:28 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Allocate names first. If any fail, bail out before allocating
|
|
|
|
* actual hardware IRQs.
|
|
|
|
*/
|
|
|
|
INIT_LIST_HEAD(&ctx->irq_names);
|
|
|
|
for (r = 1; r < CXL_IRQ_RANGES; r++) {
|
2015-01-08 22:36:47 +00:00
|
|
|
for (i = 0; i < ctx->irqs.range[r]; i++) {
|
2014-11-14 07:09:28 +00:00
|
|
|
irq_name = kmalloc(sizeof(struct cxl_irq_name),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!irq_name)
|
|
|
|
goto out;
|
|
|
|
irq_name->name = kasprintf(GFP_KERNEL, "cxl-%s-pe%i-%i",
|
|
|
|
dev_name(&ctx->afu->dev),
|
|
|
|
ctx->pe, j);
|
|
|
|
if (!irq_name->name) {
|
|
|
|
kfree(irq_name);
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
/* Add to tail so next look get the correct order */
|
|
|
|
list_add_tail(&irq_name->list, &ctx->irq_names);
|
|
|
|
j++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* We've allocated all memory now, so let's do the irq allocations */
|
|
|
|
irq_name = list_first_entry(&ctx->irq_names, struct cxl_irq_name, list);
|
2014-10-08 08:55:02 +00:00
|
|
|
for (r = 1; r < CXL_IRQ_RANGES; r++) {
|
|
|
|
hwirq = ctx->irqs.offset[r];
|
|
|
|
for (i = 0; i < ctx->irqs.range[r]; hwirq++, i++) {
|
|
|
|
cxl_map_irq(ctx->afu->adapter, hwirq,
|
2014-11-14 07:09:28 +00:00
|
|
|
cxl_irq_afu, ctx, irq_name->name);
|
|
|
|
irq_name = list_next_entry(irq_name, list);
|
2014-10-08 08:55:02 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
2014-11-14 07:09:28 +00:00
|
|
|
|
|
|
|
out:
|
|
|
|
afu_irq_name_free(ctx);
|
|
|
|
return -ENOMEM;
|
2014-10-08 08:55:02 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void afu_release_irqs(struct cxl_context *ctx)
|
|
|
|
{
|
|
|
|
irq_hw_number_t hwirq;
|
|
|
|
unsigned int virq;
|
|
|
|
int r, i;
|
|
|
|
|
|
|
|
for (r = 1; r < CXL_IRQ_RANGES; r++) {
|
|
|
|
hwirq = ctx->irqs.offset[r];
|
|
|
|
for (i = 0; i < ctx->irqs.range[r]; hwirq++, i++) {
|
|
|
|
virq = irq_find_mapping(NULL, hwirq);
|
|
|
|
if (virq)
|
|
|
|
cxl_unmap_irq(virq, ctx);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-11-14 07:09:28 +00:00
|
|
|
afu_irq_name_free(ctx);
|
2014-10-08 08:55:02 +00:00
|
|
|
cxl_release_irq_ranges(&ctx->irqs, ctx->afu->adapter);
|
|
|
|
}
|