2019-04-22 23:39:35 +00:00
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/*
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* Copyright 2012-16 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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drm-misc-next for v5.3:
UAPI Changes:
Cross-subsystem Changes:
- Add code to signal all dma-fences when freed with pending signals.
- Annotate reservation object access in CONFIG_DEBUG_MUTEXES
Core Changes:
- Assorted documentation fixes.
- Use irqsave/restore spinlock to add crc entry.
- Move code around to drm_client, for internal modeset clients.
- Make drm_crtc.h and drm_debugfs.h self-contained.
- Remove drm_fb_helper_connector.
- Add bootsplash to todo.
- Fix lock ordering in pan_display_legacy.
- Support pinning buffers to current location in gem-vram.
- Remove the now unused locking functions from gem-vram.
- Remove the now unused kmap-object argument from vram helpers.
- Stop checking return value of debugfs_create.
- Add atomic encoder enable/disable helpers.
- pass drm_atomic_state to atomic connector check.
- Add atomic support for bridge enable/disable.
- Add self refresh helpers to core.
Driver Changes:
- Add extra delay to make MTP SDM845 work.
- Small fixes to virtio, vkms, sii902x, sii9234, ast, mcde, analogix, rockchip.
- Add zpos and ?BGR8888 support to meson.
- More removals of drm_os_linux and drmP headers for amd, radeon, sti, r128, r128, savage, sis.
- Allow synopsis to unwedge the i2c hdmi bus.
- Add orientation quirks for GPD panels.
- Edid cleanups and fixing handling for edid < 1.2.
- Add runtime pm to stm.
- Handle s/r in dw-hdmi.
- Add hooks for power on/off to dsi for stm.
- Remove virtio dirty tracking code, done in drm core.
- Rework BO handling in ast and mgag200.
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Merge tag 'drm-misc-next-2019-06-14' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
drm-misc-next for v5.3:
UAPI Changes:
Cross-subsystem Changes:
- Add code to signal all dma-fences when freed with pending signals.
- Annotate reservation object access in CONFIG_DEBUG_MUTEXES
Core Changes:
- Assorted documentation fixes.
- Use irqsave/restore spinlock to add crc entry.
- Move code around to drm_client, for internal modeset clients.
- Make drm_crtc.h and drm_debugfs.h self-contained.
- Remove drm_fb_helper_connector.
- Add bootsplash to todo.
- Fix lock ordering in pan_display_legacy.
- Support pinning buffers to current location in gem-vram.
- Remove the now unused locking functions from gem-vram.
- Remove the now unused kmap-object argument from vram helpers.
- Stop checking return value of debugfs_create.
- Add atomic encoder enable/disable helpers.
- pass drm_atomic_state to atomic connector check.
- Add atomic support for bridge enable/disable.
- Add self refresh helpers to core.
Driver Changes:
- Add extra delay to make MTP SDM845 work.
- Small fixes to virtio, vkms, sii902x, sii9234, ast, mcde, analogix, rockchip.
- Add zpos and ?BGR8888 support to meson.
- More removals of drm_os_linux and drmP headers for amd, radeon, sti, r128, r128, savage, sis.
- Allow synopsis to unwedge the i2c hdmi bus.
- Add orientation quirks for GPD panels.
- Edid cleanups and fixing handling for edid < 1.2.
- Add runtime pm to stm.
- Handle s/r in dw-hdmi.
- Add hooks for power on/off to dsi for stm.
- Remove virtio dirty tracking code, done in drm core.
- Rework BO handling in ast and mgag200.
Tiny conflict in drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c,
needed #include <linux/slab.h> to make it compile.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/0e01de30-9797-853c-732f-4a5bd6e61445@linux.intel.com
2019-06-14 09:31:13 +00:00
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#include <linux/slab.h>
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2019-04-22 23:39:35 +00:00
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#include "dal_asic_id.h"
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#include "dc_types.h"
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#include "dccg.h"
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#include "clk_mgr_internal.h"
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2023-11-17 21:37:50 +00:00
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#include "dc_state_priv.h"
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2022-12-19 19:54:31 +00:00
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#include "link.h"
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2019-04-22 23:39:35 +00:00
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2019-05-07 16:47:37 +00:00
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#include "dce100/dce_clk_mgr.h"
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#include "dce110/dce110_clk_mgr.h"
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#include "dce112/dce112_clk_mgr.h"
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#include "dce120/dce120_clk_mgr.h"
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2020-07-11 20:59:07 +00:00
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#include "dce60/dce60_clk_mgr.h"
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2019-05-07 16:47:37 +00:00
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#include "dcn10/rv1_clk_mgr.h"
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#include "dcn10/rv2_clk_mgr.h"
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2019-05-07 19:57:07 +00:00
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#include "dcn20/dcn20_clk_mgr.h"
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2019-07-26 20:43:53 +00:00
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#include "dcn21/rn_clk_mgr.h"
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2021-09-25 07:01:48 +00:00
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#include "dcn201/dcn201_clk_mgr.h"
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2020-05-21 16:32:53 +00:00
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#include "dcn30/dcn30_clk_mgr.h"
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2020-09-29 15:21:58 +00:00
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#include "dcn301/vg_clk_mgr.h"
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2021-05-19 14:47:22 +00:00
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#include "dcn31/dcn31_clk_mgr.h"
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2022-06-28 22:30:47 +00:00
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#include "dcn314/dcn314_clk_mgr.h"
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2022-02-10 20:03:37 +00:00
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#include "dcn315/dcn315_clk_mgr.h"
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2022-01-26 20:44:50 +00:00
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#include "dcn316/dcn316_clk_mgr.h"
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2022-02-21 22:01:06 +00:00
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#include "dcn32/dcn32_clk_mgr.h"
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2023-08-03 03:37:49 +00:00
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#include "dcn35/dcn35_clk_mgr.h"
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2019-05-08 23:06:30 +00:00
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2019-05-08 23:06:30 +00:00
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int clk_mgr_helper_get_active_display_cnt(
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struct dc *dc,
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struct dc_state *context)
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{
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int i, display_count;
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display_count = 0;
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for (i = 0; i < context->stream_count; i++) {
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const struct dc_stream_state *stream = context->streams[i];
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2022-05-02 19:04:31 +00:00
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/* Don't count SubVP phantom pipes as part of active
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* display count
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*/
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2023-11-17 21:37:50 +00:00
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if (dc_state_get_stream_subvp_type(context, stream) == SUBVP_PHANTOM)
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2022-05-02 19:04:31 +00:00
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continue;
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2019-05-08 23:06:30 +00:00
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/*
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* Only notify active stream or virtual stream.
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* Need to notify virtual stream to work around
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* headless case. HPD does not fire when system is in
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* S0i2.
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*/
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if (!stream->dpms_off || stream->signal == SIGNAL_TYPE_VIRTUAL)
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display_count++;
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}
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return display_count;
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}
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2020-02-04 19:26:30 +00:00
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int clk_mgr_helper_get_active_plane_cnt(
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struct dc *dc,
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struct dc_state *context)
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{
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int i, total_plane_count;
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total_plane_count = 0;
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for (i = 0; i < context->stream_count; i++) {
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const struct dc_stream_status stream_status = context->stream_status[i];
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/*
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* Sum up plane_count for all streams ( active and virtual ).
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*/
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total_plane_count += stream_status.plane_count;
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}
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return total_plane_count;
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}
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2019-09-06 22:26:23 +00:00
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void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)
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{
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2021-02-05 19:46:20 +00:00
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struct dc_link *edp_links[MAX_NUM_EDP];
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struct dc_link *edp_link = NULL;
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int edp_num;
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2021-05-17 22:18:25 +00:00
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unsigned int panel_inst;
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2019-09-06 22:26:23 +00:00
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2023-02-06 22:58:52 +00:00
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dc_get_edp_links(dc, edp_links, &edp_num);
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2019-09-06 22:26:23 +00:00
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if (dc->hwss.exit_optimized_pwr_state)
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dc->hwss.exit_optimized_pwr_state(dc, dc->current_state);
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2021-02-05 19:46:20 +00:00
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if (edp_num) {
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2021-05-17 22:18:25 +00:00
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for (panel_inst = 0; panel_inst < edp_num; panel_inst++) {
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2021-09-22 10:17:13 +00:00
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bool allow_active = false;
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2021-05-17 22:18:25 +00:00
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edp_link = edp_links[panel_inst];
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if (!edp_link->psr_settings.psr_feature_enabled)
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continue;
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clk_mgr->psr_allow_active_cache = edp_link->psr_settings.psr_allow_active;
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2023-02-23 22:04:47 +00:00
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dc->link_srv->edp_set_psr_allow_active(edp_link, &allow_active, false, false, NULL);
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2023-06-30 17:58:33 +00:00
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dc->link_srv->edp_set_replay_allow_active(edp_link, &allow_active, false, false, NULL);
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2021-05-17 22:18:25 +00:00
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}
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2019-09-06 22:26:23 +00:00
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}
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}
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void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)
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{
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2021-02-05 19:46:20 +00:00
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struct dc_link *edp_links[MAX_NUM_EDP];
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struct dc_link *edp_link = NULL;
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int edp_num;
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2021-05-17 22:18:25 +00:00
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unsigned int panel_inst;
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2019-09-06 22:26:23 +00:00
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2023-02-06 22:58:52 +00:00
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dc_get_edp_links(dc, edp_links, &edp_num);
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2021-02-05 19:46:20 +00:00
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if (edp_num) {
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2021-05-17 22:18:25 +00:00
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for (panel_inst = 0; panel_inst < edp_num; panel_inst++) {
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edp_link = edp_links[panel_inst];
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if (!edp_link->psr_settings.psr_feature_enabled)
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continue;
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2023-02-23 22:04:47 +00:00
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dc->link_srv->edp_set_psr_allow_active(edp_link,
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2021-09-22 10:17:13 +00:00
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&clk_mgr->psr_allow_active_cache, false, false, NULL);
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2023-06-30 17:58:33 +00:00
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dc->link_srv->edp_set_replay_allow_active(edp_link,
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&clk_mgr->psr_allow_active_cache, false, false, NULL);
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2021-05-17 22:18:25 +00:00
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}
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2021-02-05 19:46:20 +00:00
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}
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2019-09-06 22:26:23 +00:00
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if (dc->hwss.optimize_pwr_state)
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dc->hwss.optimize_pwr_state(dc, dc->current_state);
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}
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2019-05-08 23:06:30 +00:00
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2019-04-22 23:39:35 +00:00
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struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg)
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{
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struct hw_asic_id asic_id = ctx->asic_id;
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switch (asic_id.chip_family) {
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2020-07-11 20:59:07 +00:00
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#if defined(CONFIG_DRM_AMD_DC_SI)
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2021-03-09 20:58:18 +00:00
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case FAMILY_SI: {
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struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
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if (clk_mgr == NULL) {
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BREAK_TO_DEBUGGER();
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return NULL;
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}
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2020-07-11 20:59:07 +00:00
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dce60_clk_mgr_construct(ctx, clk_mgr);
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2021-03-09 20:58:18 +00:00
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dce_clk_mgr_construct(ctx, clk_mgr);
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return &clk_mgr->base;
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}
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2020-07-11 20:59:07 +00:00
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#endif
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2019-04-22 23:39:35 +00:00
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case FAMILY_CI:
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2021-03-09 20:58:18 +00:00
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case FAMILY_KV: {
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struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
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if (clk_mgr == NULL) {
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BREAK_TO_DEBUGGER();
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return NULL;
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}
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2019-04-22 23:39:35 +00:00
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dce_clk_mgr_construct(ctx, clk_mgr);
|
2021-03-09 20:58:18 +00:00
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return &clk_mgr->base;
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}
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case FAMILY_CZ: {
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struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
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if (clk_mgr == NULL) {
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BREAK_TO_DEBUGGER();
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return NULL;
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}
|
2019-04-22 23:39:35 +00:00
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dce110_clk_mgr_construct(ctx, clk_mgr);
|
2021-03-09 20:58:18 +00:00
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return &clk_mgr->base;
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|
}
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|
case FAMILY_VI: {
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|
|
struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
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|
|
|
|
|
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if (clk_mgr == NULL) {
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|
BREAK_TO_DEBUGGER();
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|
|
return NULL;
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|
|
}
|
2019-04-22 23:39:35 +00:00
|
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|
if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
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|
ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
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dce_clk_mgr_construct(ctx, clk_mgr);
|
2021-03-09 20:58:18 +00:00
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return &clk_mgr->base;
|
2019-04-22 23:39:35 +00:00
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}
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|
|
|
if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
|
|
|
|
ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
|
|
|
|
ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
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|
|
|
dce112_clk_mgr_construct(ctx, clk_mgr);
|
2021-03-09 20:58:18 +00:00
|
|
|
return &clk_mgr->base;
|
2019-04-22 23:39:35 +00:00
|
|
|
}
|
|
|
|
if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev)) {
|
|
|
|
dce112_clk_mgr_construct(ctx, clk_mgr);
|
2021-03-09 20:58:18 +00:00
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|
return &clk_mgr->base;
|
|
|
|
}
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|
|
|
return &clk_mgr->base;
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|
|
}
|
|
|
|
case FAMILY_AI: {
|
|
|
|
struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
|
|
|
|
|
|
|
|
if (clk_mgr == NULL) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return NULL;
|
2019-04-22 23:39:35 +00:00
|
|
|
}
|
|
|
|
if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
|
|
|
|
dce121_clk_mgr_construct(ctx, clk_mgr);
|
|
|
|
else
|
|
|
|
dce120_clk_mgr_construct(ctx, clk_mgr);
|
2021-03-09 20:58:18 +00:00
|
|
|
return &clk_mgr->base;
|
|
|
|
}
|
2023-02-14 19:14:49 +00:00
|
|
|
#if defined(CONFIG_DRM_AMD_DC_FP)
|
2021-03-09 20:58:18 +00:00
|
|
|
case FAMILY_RV: {
|
|
|
|
struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
|
|
|
|
|
|
|
|
if (clk_mgr == NULL) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2019-08-08 19:11:37 +00:00
|
|
|
if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) {
|
|
|
|
rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
|
2021-03-09 20:58:18 +00:00
|
|
|
return &clk_mgr->base;
|
2019-08-08 19:11:37 +00:00
|
|
|
}
|
2020-10-08 17:28:41 +00:00
|
|
|
|
|
|
|
if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev)) {
|
|
|
|
rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
|
2021-03-09 20:58:18 +00:00
|
|
|
return &clk_mgr->base;
|
2020-10-08 17:28:41 +00:00
|
|
|
}
|
2019-04-22 23:39:35 +00:00
|
|
|
if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) {
|
|
|
|
rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
|
2021-03-09 20:58:18 +00:00
|
|
|
return &clk_mgr->base;
|
2019-04-22 23:39:35 +00:00
|
|
|
}
|
|
|
|
if (ASICREV_IS_RAVEN(asic_id.hw_internal_rev) ||
|
|
|
|
ASICREV_IS_PICASSO(asic_id.hw_internal_rev)) {
|
|
|
|
rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu);
|
2021-03-09 20:58:18 +00:00
|
|
|
return &clk_mgr->base;
|
2019-04-22 23:39:35 +00:00
|
|
|
}
|
2021-03-09 20:58:18 +00:00
|
|
|
return &clk_mgr->base;
|
|
|
|
}
|
|
|
|
case FAMILY_NV: {
|
|
|
|
struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
|
2019-04-22 23:39:35 +00:00
|
|
|
|
2021-03-09 20:58:18 +00:00
|
|
|
if (clk_mgr == NULL) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return NULL;
|
|
|
|
}
|
2020-05-21 16:32:53 +00:00
|
|
|
if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev)) {
|
|
|
|
dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
|
2021-03-09 20:58:18 +00:00
|
|
|
return &clk_mgr->base;
|
2020-05-21 16:32:53 +00:00
|
|
|
}
|
2020-09-29 18:52:09 +00:00
|
|
|
if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev)) {
|
|
|
|
dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
|
2021-03-09 20:58:18 +00:00
|
|
|
return &clk_mgr->base;
|
2020-09-29 18:52:09 +00:00
|
|
|
}
|
2021-03-15 18:55:24 +00:00
|
|
|
if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev)) {
|
|
|
|
dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
|
|
|
|
return &clk_mgr->base;
|
|
|
|
}
|
2021-09-25 07:01:48 +00:00
|
|
|
if (asic_id.chip_id == DEVICE_ID_NV_13FE) {
|
|
|
|
dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
|
|
|
|
return &clk_mgr->base;
|
|
|
|
}
|
2019-05-07 19:57:07 +00:00
|
|
|
dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
|
2021-03-09 20:58:18 +00:00
|
|
|
return &clk_mgr->base;
|
|
|
|
}
|
2020-09-29 15:21:58 +00:00
|
|
|
case FAMILY_VGH:
|
2021-03-09 20:58:18 +00:00
|
|
|
if (ASICREV_IS_VANGOGH(asic_id.hw_internal_rev)) {
|
|
|
|
struct clk_mgr_vgh *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
|
|
|
|
|
|
|
|
if (clk_mgr == NULL) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return NULL;
|
|
|
|
}
|
2020-09-29 15:21:58 +00:00
|
|
|
vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
|
2021-03-09 20:58:18 +00:00
|
|
|
return &clk_mgr->base.base;
|
|
|
|
}
|
2020-09-29 15:21:58 +00:00
|
|
|
break;
|
2022-06-28 22:30:47 +00:00
|
|
|
|
2022-01-26 20:44:50 +00:00
|
|
|
case FAMILY_YELLOW_CARP: {
|
2021-05-19 14:47:22 +00:00
|
|
|
struct clk_mgr_dcn31 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
|
|
|
|
|
|
|
|
if (clk_mgr == NULL) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return NULL;
|
|
|
|
}
|
2021-10-07 18:54:01 +00:00
|
|
|
|
|
|
|
dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
|
2021-05-19 14:47:22 +00:00
|
|
|
return &clk_mgr->base.base;
|
|
|
|
}
|
2022-02-10 20:03:37 +00:00
|
|
|
break;
|
|
|
|
case AMDGPU_FAMILY_GC_10_3_6: {
|
|
|
|
struct clk_mgr_dcn315 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
|
|
|
|
|
|
|
|
if (clk_mgr == NULL) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
dcn315_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
|
|
|
|
return &clk_mgr->base.base;
|
|
|
|
}
|
|
|
|
break;
|
2022-01-26 20:44:50 +00:00
|
|
|
case AMDGPU_FAMILY_GC_10_3_7: {
|
|
|
|
struct clk_mgr_dcn316 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
|
|
|
|
|
|
|
|
if (clk_mgr == NULL) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
dcn316_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
|
|
|
|
return &clk_mgr->base.base;
|
|
|
|
}
|
2022-02-10 20:03:37 +00:00
|
|
|
break;
|
2022-02-21 22:01:06 +00:00
|
|
|
case AMDGPU_FAMILY_GC_11_0_0: {
|
|
|
|
struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
|
|
|
|
|
|
|
|
if (clk_mgr == NULL) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return NULL;
|
|
|
|
}
|
2021-05-19 14:47:22 +00:00
|
|
|
|
2022-02-21 22:01:06 +00:00
|
|
|
dcn32_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
|
|
|
|
return &clk_mgr->base;
|
|
|
|
}
|
2022-06-28 22:30:47 +00:00
|
|
|
|
2022-08-04 08:44:56 +00:00
|
|
|
case AMDGPU_FAMILY_GC_11_0_1: {
|
2022-06-28 22:30:47 +00:00
|
|
|
struct clk_mgr_dcn314 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
|
|
|
|
|
|
|
|
if (clk_mgr == NULL) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
dcn314_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
|
|
|
|
return &clk_mgr->base.base;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2023-07-27 23:29:43 +00:00
|
|
|
case AMDGPU_FAMILY_GC_11_5_0: {
|
|
|
|
struct clk_mgr_dcn35 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
|
|
|
|
|
|
|
|
if (clk_mgr == NULL) {
|
|
|
|
BREAK_TO_DEBUGGER();
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
dcn35_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
|
|
|
|
return &clk_mgr->base.base;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2023-12-06 19:52:26 +00:00
|
|
|
#endif /* CONFIG_DRM_AMD_DC_FP */
|
2019-04-22 23:39:35 +00:00
|
|
|
default:
|
|
|
|
ASSERT(0); /* Unknown Asic */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2021-03-09 20:58:18 +00:00
|
|
|
return NULL;
|
2019-04-22 23:39:35 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
|
|
|
|
{
|
|
|
|
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
|
2020-05-21 16:32:53 +00:00
|
|
|
|
2023-02-14 19:14:49 +00:00
|
|
|
#ifdef CONFIG_DRM_AMD_DC_FP
|
2020-05-21 16:32:53 +00:00
|
|
|
switch (clk_mgr_base->ctx->asic_id.chip_family) {
|
|
|
|
case FAMILY_NV:
|
|
|
|
if (ASICREV_IS_SIENNA_CICHLID_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {
|
|
|
|
dcn3_clk_mgr_destroy(clk_mgr);
|
2021-11-12 22:59:31 +00:00
|
|
|
} else if (ASICREV_IS_DIMGREY_CAVEFISH_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {
|
2021-03-23 16:59:26 +00:00
|
|
|
dcn3_clk_mgr_destroy(clk_mgr);
|
|
|
|
}
|
2021-03-15 18:55:24 +00:00
|
|
|
if (ASICREV_IS_BEIGE_GOBY_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {
|
|
|
|
dcn3_clk_mgr_destroy(clk_mgr);
|
|
|
|
}
|
2020-09-29 15:21:58 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case FAMILY_VGH:
|
|
|
|
if (ASICREV_IS_VANGOGH(clk_mgr_base->ctx->asic_id.hw_internal_rev))
|
|
|
|
vg_clk_mgr_destroy(clk_mgr);
|
|
|
|
break;
|
|
|
|
|
2021-05-19 14:47:22 +00:00
|
|
|
case FAMILY_YELLOW_CARP:
|
2022-02-10 20:03:37 +00:00
|
|
|
dcn31_clk_mgr_destroy(clk_mgr);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AMDGPU_FAMILY_GC_10_3_6:
|
|
|
|
dcn315_clk_mgr_destroy(clk_mgr);
|
2021-05-19 14:47:22 +00:00
|
|
|
break;
|
|
|
|
|
2022-01-26 20:44:50 +00:00
|
|
|
case AMDGPU_FAMILY_GC_10_3_7:
|
2022-02-10 20:03:37 +00:00
|
|
|
dcn316_clk_mgr_destroy(clk_mgr);
|
2022-01-26 20:44:50 +00:00
|
|
|
break;
|
|
|
|
|
2022-02-21 22:01:06 +00:00
|
|
|
case AMDGPU_FAMILY_GC_11_0_0:
|
|
|
|
dcn32_clk_mgr_destroy(clk_mgr);
|
|
|
|
break;
|
2022-06-28 22:30:47 +00:00
|
|
|
|
2022-08-04 08:44:56 +00:00
|
|
|
case AMDGPU_FAMILY_GC_11_0_1:
|
2022-06-28 22:30:47 +00:00
|
|
|
dcn314_clk_mgr_destroy(clk_mgr);
|
|
|
|
break;
|
|
|
|
|
2023-08-03 03:37:49 +00:00
|
|
|
case AMDGPU_FAMILY_GC_11_5_0:
|
|
|
|
dcn35_clk_mgr_destroy(clk_mgr);
|
|
|
|
break;
|
|
|
|
|
2020-09-29 15:21:58 +00:00
|
|
|
default:
|
|
|
|
break;
|
2020-05-21 16:32:53 +00:00
|
|
|
}
|
2023-02-14 19:14:49 +00:00
|
|
|
#endif /* CONFIG_DRM_AMD_DC_FP */
|
2019-04-22 23:39:35 +00:00
|
|
|
|
|
|
|
kfree(clk_mgr);
|
|
|
|
}
|
2019-05-07 16:47:37 +00:00
|
|
|
|