2022-12-19 19:54:31 +00:00
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/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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/* FILE POLICY AND INTENDED USAGE:
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* This file implements retrieval and configuration of eDP panel features such
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* as PSR and ABM and it also manages specs defined eDP panel power sequences.
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*/
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#include "link_edp_panel_control.h"
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#include "link_dpcd.h"
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#include "link_dp_capability.h"
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#include "dm_helpers.h"
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#include "dal_asic_id.h"
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2023-07-04 07:31:43 +00:00
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#include "link_dp_phy.h"
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2022-12-19 19:54:31 +00:00
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#include "dce/dmub_psr.h"
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2023-05-12 18:23:11 +00:00
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#include "dc/dc_dmub_srv.h"
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#include "dce/dmub_replay.h"
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2022-12-19 19:54:31 +00:00
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#include "abm.h"
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2023-09-20 17:38:11 +00:00
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#define DC_LOGGER \
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link->ctx->logger
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2022-12-19 19:54:31 +00:00
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#define DC_LOGGER_INIT(logger)
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2023-05-12 18:23:11 +00:00
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#define DP_SINK_PR_ENABLE_AND_CONFIGURATION 0x37B
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2023-03-17 08:17:01 +00:00
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/* Travis */
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static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
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/* Nutmeg */
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static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
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2022-12-19 19:54:31 +00:00
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void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
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{
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union dpcd_edp_config edp_config_set;
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bool panel_mode_edp = false;
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2023-07-14 16:59:06 +00:00
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enum dc_status result;
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2022-12-19 19:54:31 +00:00
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memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
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2023-07-14 16:59:06 +00:00
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switch (panel_mode) {
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case DP_PANEL_MODE_EDP:
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case DP_PANEL_MODE_SPECIAL:
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panel_mode_edp = true;
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break;
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2022-12-19 19:54:31 +00:00
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2023-07-14 16:59:06 +00:00
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default:
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break;
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}
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/*set edp panel mode in receiver*/
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result = core_link_read_dpcd(
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link,
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DP_EDP_CONFIGURATION_SET,
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&edp_config_set.raw,
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sizeof(edp_config_set.raw));
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2022-12-19 19:54:31 +00:00
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2023-07-14 16:59:06 +00:00
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if (result == DC_OK &&
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edp_config_set.bits.PANEL_MODE_EDP
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!= panel_mode_edp) {
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2022-12-19 19:54:31 +00:00
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2023-07-14 16:59:06 +00:00
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edp_config_set.bits.PANEL_MODE_EDP =
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panel_mode_edp;
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result = core_link_write_dpcd(
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2022-12-19 19:54:31 +00:00
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link,
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DP_EDP_CONFIGURATION_SET,
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&edp_config_set.raw,
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sizeof(edp_config_set.raw));
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2023-07-14 16:59:06 +00:00
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ASSERT(result == DC_OK);
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2022-12-19 19:54:31 +00:00
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}
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2023-07-14 16:59:06 +00:00
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2023-03-30 15:35:08 +00:00
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link->panel_mode = panel_mode;
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2022-12-19 19:54:31 +00:00
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DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
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"eDP panel mode enabled: %d \n",
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link->link_index,
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link->dpcd_caps.panel_mode_edp,
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panel_mode_edp);
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}
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enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
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{
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/* We need to explicitly check that connector
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* is not DP. Some Travis_VGA get reported
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* by video bios as DP.
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*/
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if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
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switch (link->dpcd_caps.branch_dev_id) {
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case DP_BRANCH_DEVICE_ID_0022B9:
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/* alternate scrambler reset is required for Travis
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* for the case when external chip does not
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* provide sink device id, alternate scrambler
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* scheme will be overriden later by querying
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* Encoder features
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*/
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if (strncmp(
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link->dpcd_caps.branch_dev_name,
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DP_VGA_LVDS_CONVERTER_ID_2,
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sizeof(
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link->dpcd_caps.
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branch_dev_name)) == 0) {
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return DP_PANEL_MODE_SPECIAL;
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}
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break;
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case DP_BRANCH_DEVICE_ID_00001A:
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/* alternate scrambler reset is required for Travis
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* for the case when external chip does not provide
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* sink device id, alternate scrambler scheme will
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* be overriden later by querying Encoder feature
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*/
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if (strncmp(link->dpcd_caps.branch_dev_name,
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DP_VGA_LVDS_CONVERTER_ID_3,
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sizeof(
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link->dpcd_caps.
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branch_dev_name)) == 0) {
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return DP_PANEL_MODE_SPECIAL;
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}
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break;
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default:
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break;
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}
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}
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if (link->dpcd_caps.panel_mode_edp &&
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(link->connector_signal == SIGNAL_TYPE_EDP ||
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(link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
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link->is_internal_display))) {
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return DP_PANEL_MODE_EDP;
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}
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return DP_PANEL_MODE_DEFAULT;
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}
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2023-02-15 17:50:59 +00:00
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bool edp_set_backlight_level_nits(struct dc_link *link,
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2022-12-19 19:54:31 +00:00
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bool isHDR,
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uint32_t backlight_millinits,
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uint32_t transition_time_in_ms)
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{
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struct dpcd_source_backlight_set dpcd_backlight_set;
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uint8_t backlight_control = isHDR ? 1 : 0;
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if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
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link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
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return false;
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// OLEDs have no PWM, they can only use AUX
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if (link->dpcd_sink_ext_caps.bits.oled == 1)
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backlight_control = 1;
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*(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
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*(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
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2023-03-16 20:29:06 +00:00
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if (!link->dpcd_caps.panel_luminance_control) {
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if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
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2022-12-19 19:54:31 +00:00
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(uint8_t *)(&dpcd_backlight_set),
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sizeof(dpcd_backlight_set)) != DC_OK)
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2023-03-16 20:29:06 +00:00
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return false;
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2022-12-19 19:54:31 +00:00
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2023-03-16 20:29:06 +00:00
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if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
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2022-12-19 19:54:31 +00:00
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&backlight_control, 1) != DC_OK)
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2023-03-16 20:29:06 +00:00
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return false;
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} else {
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2023-09-29 15:20:46 +00:00
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uint8_t backlight_enable = 0;
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2023-03-16 20:29:06 +00:00
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struct target_luminance_value *target_luminance = NULL;
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//if target luminance value is greater than 24 bits, clip the value to 24 bits
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if (backlight_millinits > 0xFFFFFF)
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backlight_millinits = 0xFFFFFF;
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target_luminance = (struct target_luminance_value *)&backlight_millinits;
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2023-09-29 15:20:46 +00:00
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core_link_read_dpcd(link, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
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&backlight_enable, sizeof(uint8_t));
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backlight_enable |= DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE;
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2023-03-16 20:29:06 +00:00
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if (core_link_write_dpcd(link, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
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&backlight_enable,
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sizeof(backlight_enable)) != DC_OK)
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return false;
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if (core_link_write_dpcd(link, DP_EDP_PANEL_TARGET_LUMINANCE_VALUE,
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(uint8_t *)(target_luminance),
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sizeof(struct target_luminance_value)) != DC_OK)
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return false;
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}
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2022-12-19 19:54:31 +00:00
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return true;
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}
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2023-02-15 17:50:59 +00:00
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bool edp_get_backlight_level_nits(struct dc_link *link,
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2022-12-19 19:54:31 +00:00
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uint32_t *backlight_millinits_avg,
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uint32_t *backlight_millinits_peak)
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{
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union dpcd_source_backlight_get dpcd_backlight_get;
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memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
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if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
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link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
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return false;
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if (!core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
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dpcd_backlight_get.raw,
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sizeof(union dpcd_source_backlight_get)))
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return false;
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*backlight_millinits_avg =
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dpcd_backlight_get.bytes.backlight_millinits_avg;
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*backlight_millinits_peak =
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dpcd_backlight_get.bytes.backlight_millinits_peak;
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/* On non-supported panels dpcd_read usually succeeds with 0 returned */
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if (*backlight_millinits_avg == 0 ||
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*backlight_millinits_avg > *backlight_millinits_peak)
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return false;
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return true;
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}
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2023-02-23 22:04:47 +00:00
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bool edp_backlight_enable_aux(struct dc_link *link, bool enable)
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2022-12-19 19:54:31 +00:00
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{
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uint8_t backlight_enable = enable ? 1 : 0;
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if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
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link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
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return false;
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if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
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&backlight_enable, 1) != DC_OK)
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return false;
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return true;
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}
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// we read default from 0x320 because we expect BIOS wrote it there
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// regular get_backlight_nit reads from panel set at 0x326
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static bool read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
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{
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if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
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link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
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return false;
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2023-07-10 18:01:35 +00:00
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if (!link->dpcd_caps.panel_luminance_control) {
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if (!core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
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(uint8_t *)backlight_millinits,
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sizeof(uint32_t)))
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return false;
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} else {
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//setting to 0 as a precaution, since target_luminance_value is 3 bytes
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memset(backlight_millinits, 0, sizeof(uint32_t));
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if (!core_link_read_dpcd(link, DP_EDP_PANEL_TARGET_LUMINANCE_VALUE,
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(uint8_t *)backlight_millinits,
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sizeof(struct target_luminance_value)))
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return false;
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}
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2022-12-19 19:54:31 +00:00
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return true;
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}
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bool set_default_brightness_aux(struct dc_link *link)
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{
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uint32_t default_backlight;
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if (link && link->dpcd_sink_ext_caps.bits.oled == 1) {
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if (!read_default_bl_aux(link, &default_backlight))
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default_backlight = 150000;
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2023-12-28 06:51:33 +00:00
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// if > 5000, it might be wrong readback. 0 nits is a valid default value for OLED panel.
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2023-12-06 18:08:26 +00:00
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if (default_backlight < 1000 || default_backlight > 5000000)
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2023-11-03 04:08:42 +00:00
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default_backlight = 150000;
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2022-12-19 19:54:31 +00:00
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2023-02-16 21:22:01 +00:00
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return edp_set_backlight_level_nits(link, true,
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2022-12-19 19:54:31 +00:00
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default_backlight, 0);
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}
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return false;
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}
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2023-09-08 06:45:00 +00:00
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bool edp_is_ilr_optimization_enabled(struct dc_link *link)
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{
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if (link->dpcd_caps.edp_supported_link_rates_count == 0 || !link->panel_config.ilr.optimize_edp_link_rate)
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return false;
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return true;
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}
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enum dc_link_rate get_max_link_rate_from_ilr_table(struct dc_link *link)
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{
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enum dc_link_rate link_rate = link->reported_link_cap.link_rate;
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for (int i = 0; i < link->dpcd_caps.edp_supported_link_rates_count; i++) {
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if (link_rate < link->dpcd_caps.edp_supported_link_rates[i])
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link_rate = link->dpcd_caps.edp_supported_link_rates[i];
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}
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|
return link_rate;
|
|
|
|
}
|
2023-06-27 18:36:49 +00:00
|
|
|
|
2023-02-23 22:04:47 +00:00
|
|
|
bool edp_is_ilr_optimization_required(struct dc_link *link,
|
2022-12-19 19:54:31 +00:00
|
|
|
struct dc_crtc_timing *crtc_timing)
|
|
|
|
{
|
|
|
|
struct dc_link_settings link_setting;
|
|
|
|
uint8_t link_bw_set;
|
|
|
|
uint8_t link_rate_set;
|
|
|
|
uint32_t req_bw;
|
|
|
|
union lane_count_set lane_count_set = {0};
|
|
|
|
|
|
|
|
ASSERT(link || crtc_timing); // invalid input
|
|
|
|
|
2023-09-08 06:45:00 +00:00
|
|
|
if (!edp_is_ilr_optimization_enabled(link))
|
2022-12-19 19:54:31 +00:00
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
|
|
// Read DPCD 00100h to find if standard link rates are set
|
|
|
|
core_link_read_dpcd(link, DP_LINK_BW_SET,
|
|
|
|
&link_bw_set, sizeof(link_bw_set));
|
|
|
|
|
|
|
|
if (link_bw_set) {
|
|
|
|
DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS used link_bw_set\n");
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Read DPCD 00115h to find the edp link rate set used
|
|
|
|
core_link_read_dpcd(link, DP_LINK_RATE_SET,
|
|
|
|
&link_rate_set, sizeof(link_rate_set));
|
|
|
|
|
|
|
|
// Read DPCD 00101h to find out the number of lanes currently set
|
|
|
|
core_link_read_dpcd(link, DP_LANE_COUNT_SET,
|
|
|
|
&lane_count_set.raw, sizeof(lane_count_set));
|
|
|
|
|
2023-06-17 02:35:46 +00:00
|
|
|
req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing, dc_link_get_highest_encoding_format(link));
|
2022-12-19 19:54:31 +00:00
|
|
|
|
|
|
|
if (!crtc_timing->flags.DSC)
|
2023-02-16 21:22:01 +00:00
|
|
|
edp_decide_link_settings(link, &link_setting, req_bw);
|
2022-12-19 19:54:31 +00:00
|
|
|
else
|
|
|
|
decide_edp_link_settings_with_dsc(link, &link_setting, req_bw, LINK_RATE_UNKNOWN);
|
|
|
|
|
|
|
|
if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate ||
|
|
|
|
lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) {
|
|
|
|
DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS link_rate_set not optimal\n");
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
DC_LOG_EVENT_LINK_TRAINING("eDP ILR: No optimization required, VBIOS set optimal link_rate_set\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2023-02-15 17:50:59 +00:00
|
|
|
void edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd)
|
2022-12-19 19:54:31 +00:00
|
|
|
{
|
|
|
|
if (link->connector_signal != SIGNAL_TYPE_EDP)
|
|
|
|
return;
|
|
|
|
|
|
|
|
link->dc->hwss.edp_power_control(link, true);
|
|
|
|
if (wait_for_hpd)
|
|
|
|
link->dc->hwss.edp_wait_for_hpd_ready(link, true);
|
|
|
|
if (link->dc->hwss.edp_backlight_control)
|
|
|
|
link->dc->hwss.edp_backlight_control(link, true);
|
|
|
|
}
|
|
|
|
|
2023-07-04 07:31:43 +00:00
|
|
|
void edp_set_panel_power(struct dc_link *link, bool powerOn)
|
|
|
|
{
|
|
|
|
if (powerOn) {
|
|
|
|
// 1. panel VDD on
|
|
|
|
if (!link->dc->config.edp_no_power_sequencing)
|
|
|
|
link->dc->hwss.edp_power_control(link, true);
|
|
|
|
link->dc->hwss.edp_wait_for_hpd_ready(link, true);
|
|
|
|
|
|
|
|
// 2. panel BL on
|
|
|
|
if (link->dc->hwss.edp_backlight_control)
|
|
|
|
link->dc->hwss.edp_backlight_control(link, true);
|
|
|
|
|
|
|
|
// 3. Rx power on
|
|
|
|
dpcd_write_rx_power_ctrl(link, true);
|
|
|
|
} else {
|
|
|
|
// 3. Rx power off
|
|
|
|
dpcd_write_rx_power_ctrl(link, false);
|
|
|
|
|
|
|
|
// 2. panel BL off
|
|
|
|
if (link->dc->hwss.edp_backlight_control)
|
|
|
|
link->dc->hwss.edp_backlight_control(link, false);
|
|
|
|
|
|
|
|
// 1. panel VDD off
|
|
|
|
if (!link->dc->config.edp_no_power_sequencing)
|
|
|
|
link->dc->hwss.edp_power_control(link, false);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2023-02-15 17:50:59 +00:00
|
|
|
bool edp_wait_for_t12(struct dc_link *link)
|
2022-12-19 19:54:31 +00:00
|
|
|
{
|
|
|
|
if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
|
|
|
|
link->dc->hwss.edp_wait_for_T12(link);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2023-02-23 22:04:47 +00:00
|
|
|
void edp_add_delay_for_T9(struct dc_link *link)
|
2022-12-19 19:54:31 +00:00
|
|
|
{
|
|
|
|
if (link && link->panel_config.pps.extra_delay_backlight_off > 0)
|
2023-02-03 22:46:05 +00:00
|
|
|
fsleep(link->panel_config.pps.extra_delay_backlight_off * 1000);
|
2022-12-19 19:54:31 +00:00
|
|
|
}
|
|
|
|
|
2023-02-23 22:04:47 +00:00
|
|
|
bool edp_receiver_ready_T9(struct dc_link *link)
|
2022-12-19 19:54:31 +00:00
|
|
|
{
|
|
|
|
unsigned int tries = 0;
|
|
|
|
unsigned char sinkstatus = 0;
|
|
|
|
unsigned char edpRev = 0;
|
|
|
|
enum dc_status result = DC_OK;
|
|
|
|
|
|
|
|
result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
|
|
|
|
|
|
|
|
/* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
|
|
|
|
if (result == DC_OK && edpRev >= DP_EDP_12) {
|
|
|
|
do {
|
|
|
|
sinkstatus = 1;
|
|
|
|
result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
|
|
|
|
if (sinkstatus == 0)
|
|
|
|
break;
|
|
|
|
if (result != DC_OK)
|
|
|
|
break;
|
|
|
|
udelay(100); //MAx T9
|
|
|
|
} while (++tries < 50);
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
2023-02-23 22:04:47 +00:00
|
|
|
bool edp_receiver_ready_T7(struct dc_link *link)
|
2022-12-19 19:54:31 +00:00
|
|
|
{
|
|
|
|
unsigned char sinkstatus = 0;
|
|
|
|
unsigned char edpRev = 0;
|
|
|
|
enum dc_status result = DC_OK;
|
|
|
|
|
|
|
|
/* use absolute time stamp to constrain max T7*/
|
|
|
|
unsigned long long enter_timestamp = 0;
|
|
|
|
unsigned long long finish_timestamp = 0;
|
|
|
|
unsigned long long time_taken_in_ns = 0;
|
|
|
|
|
|
|
|
result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
|
|
|
|
|
|
|
|
if (result == DC_OK && edpRev >= DP_EDP_12) {
|
|
|
|
/* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
|
|
|
|
enter_timestamp = dm_get_timestamp(link->ctx);
|
|
|
|
do {
|
|
|
|
sinkstatus = 0;
|
|
|
|
result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
|
|
|
|
if (sinkstatus == 1)
|
|
|
|
break;
|
|
|
|
if (result != DC_OK)
|
|
|
|
break;
|
|
|
|
udelay(25);
|
|
|
|
finish_timestamp = dm_get_timestamp(link->ctx);
|
|
|
|
time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp, enter_timestamp);
|
|
|
|
} while (time_taken_in_ns < 50 * 1000000); //MAx T7 is 50ms
|
|
|
|
}
|
|
|
|
|
|
|
|
if (link && link->panel_config.pps.extra_t7_ms > 0)
|
2023-02-03 22:46:05 +00:00
|
|
|
fsleep(link->panel_config.pps.extra_t7_ms * 1000);
|
2022-12-19 19:54:31 +00:00
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
2023-02-23 22:04:47 +00:00
|
|
|
bool edp_power_alpm_dpcd_enable(struct dc_link *link, bool enable)
|
2022-12-19 19:54:31 +00:00
|
|
|
{
|
|
|
|
bool ret = false;
|
|
|
|
union dpcd_alpm_configuration alpm_config;
|
|
|
|
|
|
|
|
if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
|
|
|
|
memset(&alpm_config, 0, sizeof(alpm_config));
|
|
|
|
|
|
|
|
alpm_config.bits.ENABLE = (enable ? true : false);
|
|
|
|
ret = dm_helpers_dp_write_dpcd(link->ctx, link,
|
|
|
|
DP_RECEIVER_ALPM_CONFIG, &alpm_config.raw,
|
|
|
|
sizeof(alpm_config.raw));
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
struct dc *dc = link->ctx->dc;
|
|
|
|
struct pipe_ctx *pipe_ctx = NULL;
|
|
|
|
|
|
|
|
for (i = 0; i < MAX_PIPES; i++) {
|
|
|
|
if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
|
|
|
|
if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
|
|
|
|
pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return pipe_ctx;
|
|
|
|
}
|
|
|
|
|
2023-02-15 17:50:59 +00:00
|
|
|
bool edp_set_backlight_level(const struct dc_link *link,
|
2022-12-19 19:54:31 +00:00
|
|
|
uint32_t backlight_pwm_u16_16,
|
|
|
|
uint32_t frame_ramp)
|
|
|
|
{
|
|
|
|
struct dc *dc = link->ctx->dc;
|
|
|
|
|
|
|
|
DC_LOGGER_INIT(link->ctx->logger);
|
|
|
|
DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
|
|
|
|
backlight_pwm_u16_16, backlight_pwm_u16_16);
|
|
|
|
|
|
|
|
if (dc_is_embedded_signal(link->connector_signal)) {
|
|
|
|
struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
|
|
|
|
|
2023-11-16 08:19:25 +00:00
|
|
|
if (link->panel_cntl)
|
|
|
|
link->panel_cntl->stored_backlight_registers.USER_LEVEL = backlight_pwm_u16_16;
|
|
|
|
|
2022-12-19 19:54:31 +00:00
|
|
|
if (pipe_ctx) {
|
|
|
|
/* Disable brightness ramping when the display is blanked
|
|
|
|
* as it can hang the DMCU
|
|
|
|
*/
|
|
|
|
if (pipe_ctx->plane_state == NULL)
|
|
|
|
frame_ramp = 0;
|
|
|
|
} else {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
dc->hwss.set_backlight_level(
|
|
|
|
pipe_ctx,
|
|
|
|
backlight_pwm_u16_16,
|
|
|
|
frame_ramp);
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2023-02-15 17:50:59 +00:00
|
|
|
bool edp_set_psr_allow_active(struct dc_link *link, const bool *allow_active,
|
2022-12-19 19:54:31 +00:00
|
|
|
bool wait, bool force_static, const unsigned int *power_opts)
|
|
|
|
{
|
|
|
|
struct dc *dc = link->ctx->dc;
|
|
|
|
struct dmcu *dmcu = dc->res_pool->dmcu;
|
|
|
|
struct dmub_psr *psr = dc->res_pool->psr;
|
|
|
|
unsigned int panel_inst;
|
|
|
|
|
|
|
|
if (psr == NULL && force_static)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if ((allow_active != NULL) && (*allow_active == true) && (link->type == dc_connection_none)) {
|
|
|
|
// Don't enter PSR if panel is not connected
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set power optimization flag */
|
|
|
|
if (power_opts && link->psr_settings.psr_power_opt != *power_opts) {
|
|
|
|
link->psr_settings.psr_power_opt = *power_opts;
|
|
|
|
|
|
|
|
if (psr != NULL && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt)
|
|
|
|
psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, panel_inst);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (psr != NULL && link->psr_settings.psr_feature_enabled &&
|
|
|
|
force_static && psr->funcs->psr_force_static)
|
|
|
|
psr->funcs->psr_force_static(psr, panel_inst);
|
|
|
|
|
|
|
|
/* Enable or Disable PSR */
|
|
|
|
if (allow_active && link->psr_settings.psr_allow_active != *allow_active) {
|
|
|
|
link->psr_settings.psr_allow_active = *allow_active;
|
|
|
|
|
|
|
|
if (!link->psr_settings.psr_allow_active)
|
|
|
|
dc_z10_restore(dc);
|
|
|
|
|
|
|
|
if (psr != NULL && link->psr_settings.psr_feature_enabled) {
|
|
|
|
psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);
|
|
|
|
} else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&
|
|
|
|
link->psr_settings.psr_feature_enabled)
|
|
|
|
dmcu->funcs->set_psr_enable(dmcu, link->psr_settings.psr_allow_active, wait);
|
|
|
|
else
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2023-02-15 17:50:59 +00:00
|
|
|
bool edp_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
|
2022-12-19 19:54:31 +00:00
|
|
|
{
|
|
|
|
struct dc *dc = link->ctx->dc;
|
|
|
|
struct dmcu *dmcu = dc->res_pool->dmcu;
|
|
|
|
struct dmub_psr *psr = dc->res_pool->psr;
|
|
|
|
unsigned int panel_inst;
|
|
|
|
|
|
|
|
if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (psr != NULL && link->psr_settings.psr_feature_enabled)
|
|
|
|
psr->funcs->psr_get_state(psr, state, panel_inst);
|
|
|
|
else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
|
|
|
|
dmcu->funcs->get_psr_state(dmcu, state);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline enum physical_phy_id
|
|
|
|
transmitter_to_phy_id(struct dc_link *link)
|
|
|
|
{
|
|
|
|
struct dc_context *dc_ctx = link->ctx;
|
|
|
|
enum transmitter transmitter_value = link->link_enc->transmitter;
|
|
|
|
|
|
|
|
switch (transmitter_value) {
|
|
|
|
case TRANSMITTER_UNIPHY_A:
|
|
|
|
return PHYLD_0;
|
|
|
|
case TRANSMITTER_UNIPHY_B:
|
|
|
|
return PHYLD_1;
|
|
|
|
case TRANSMITTER_UNIPHY_C:
|
|
|
|
return PHYLD_2;
|
|
|
|
case TRANSMITTER_UNIPHY_D:
|
|
|
|
return PHYLD_3;
|
|
|
|
case TRANSMITTER_UNIPHY_E:
|
|
|
|
return PHYLD_4;
|
|
|
|
case TRANSMITTER_UNIPHY_F:
|
|
|
|
return PHYLD_5;
|
|
|
|
case TRANSMITTER_NUTMEG_CRT:
|
|
|
|
return PHYLD_6;
|
|
|
|
case TRANSMITTER_TRAVIS_CRT:
|
|
|
|
return PHYLD_7;
|
|
|
|
case TRANSMITTER_TRAVIS_LCD:
|
|
|
|
return PHYLD_8;
|
|
|
|
case TRANSMITTER_UNIPHY_G:
|
|
|
|
return PHYLD_9;
|
|
|
|
case TRANSMITTER_COUNT:
|
|
|
|
return PHYLD_COUNT;
|
|
|
|
case TRANSMITTER_UNKNOWN:
|
|
|
|
return PHYLD_UNKNOWN;
|
|
|
|
default:
|
|
|
|
DC_ERROR("Unknown transmitter value %d\n", transmitter_value);
|
|
|
|
return PHYLD_UNKNOWN;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2023-02-15 17:50:59 +00:00
|
|
|
bool edp_setup_psr(struct dc_link *link,
|
2022-12-19 19:54:31 +00:00
|
|
|
const struct dc_stream_state *stream, struct psr_config *psr_config,
|
|
|
|
struct psr_context *psr_context)
|
|
|
|
{
|
|
|
|
struct dc *dc;
|
|
|
|
struct dmcu *dmcu;
|
|
|
|
struct dmub_psr *psr;
|
|
|
|
int i;
|
|
|
|
unsigned int panel_inst;
|
|
|
|
/* updateSinkPsrDpcdConfig*/
|
|
|
|
union dpcd_psr_configuration psr_configuration;
|
|
|
|
union dpcd_sink_active_vtotal_control_mode vtotal_control = {0};
|
|
|
|
|
|
|
|
psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
|
|
|
|
|
|
|
|
if (!link)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
dc = link->ctx->dc;
|
|
|
|
dmcu = dc->res_pool->dmcu;
|
|
|
|
psr = dc->res_pool->psr;
|
|
|
|
|
|
|
|
if (!dmcu && !psr)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
|
|
memset(&psr_configuration, 0, sizeof(psr_configuration));
|
|
|
|
|
|
|
|
psr_configuration.bits.ENABLE = 1;
|
|
|
|
psr_configuration.bits.CRC_VERIFICATION = 1;
|
|
|
|
psr_configuration.bits.FRAME_CAPTURE_INDICATION =
|
|
|
|
psr_config->psr_frame_capture_indication_req;
|
|
|
|
|
|
|
|
/* Check for PSR v2*/
|
|
|
|
if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
|
|
|
|
/* For PSR v2 selective update.
|
|
|
|
* Indicates whether sink should start capturing
|
|
|
|
* immediately following active scan line,
|
|
|
|
* or starting with the 2nd active scan line.
|
|
|
|
*/
|
|
|
|
psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
|
|
|
|
/*For PSR v2, determines whether Sink should generate
|
|
|
|
* IRQ_HPD when CRC mismatch is detected.
|
|
|
|
*/
|
|
|
|
psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR = 1;
|
|
|
|
/* For PSR v2, set the bit when the Source device will
|
|
|
|
* be enabling PSR2 operation.
|
|
|
|
*/
|
|
|
|
psr_configuration.bits.ENABLE_PSR2 = 1;
|
|
|
|
/* For PSR v2, the Sink device must be able to receive
|
|
|
|
* SU region updates early in the frame time.
|
|
|
|
*/
|
|
|
|
psr_configuration.bits.EARLY_TRANSPORT_ENABLE = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
dm_helpers_dp_write_dpcd(
|
|
|
|
link->ctx,
|
|
|
|
link,
|
|
|
|
368,
|
|
|
|
&psr_configuration.raw,
|
|
|
|
sizeof(psr_configuration.raw));
|
|
|
|
|
|
|
|
if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
|
2023-02-23 22:04:47 +00:00
|
|
|
edp_power_alpm_dpcd_enable(link, true);
|
2022-12-19 19:54:31 +00:00
|
|
|
psr_context->su_granularity_required =
|
|
|
|
psr_config->su_granularity_required;
|
|
|
|
psr_context->su_y_granularity =
|
|
|
|
psr_config->su_y_granularity;
|
|
|
|
psr_context->line_time_in_us = psr_config->line_time_in_us;
|
|
|
|
|
|
|
|
/* linux must be able to expose AMD Source DPCD definition
|
|
|
|
* in order to support FreeSync PSR
|
|
|
|
*/
|
|
|
|
if (link->psr_settings.psr_vtotal_control_support) {
|
|
|
|
psr_context->rate_control_caps = psr_config->rate_control_caps;
|
|
|
|
vtotal_control.bits.ENABLE = true;
|
|
|
|
core_link_write_dpcd(link, DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE,
|
|
|
|
&vtotal_control.raw, sizeof(vtotal_control.raw));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
|
|
|
|
psr_context->transmitterId = link->link_enc->transmitter;
|
|
|
|
psr_context->engineId = link->link_enc->preferred_engine;
|
|
|
|
|
|
|
|
for (i = 0; i < MAX_PIPES; i++) {
|
|
|
|
if (dc->current_state->res_ctx.pipe_ctx[i].stream
|
|
|
|
== stream) {
|
|
|
|
/* dmcu -1 for all controller id values,
|
|
|
|
* therefore +1 here
|
|
|
|
*/
|
|
|
|
psr_context->controllerId =
|
|
|
|
dc->current_state->res_ctx.
|
|
|
|
pipe_ctx[i].stream_res.tg->inst + 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Hardcoded for now. Can be Pcie or Uniphy (or Unknown)*/
|
|
|
|
psr_context->phyType = PHY_TYPE_UNIPHY;
|
|
|
|
/*PhyId is associated with the transmitter id*/
|
|
|
|
psr_context->smuPhyId = transmitter_to_phy_id(link);
|
|
|
|
|
|
|
|
psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
|
|
|
|
psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
|
|
|
|
timing.pix_clk_100hz * 100),
|
|
|
|
stream->timing.v_total),
|
|
|
|
stream->timing.h_total);
|
|
|
|
|
|
|
|
psr_context->psrSupportedDisplayConfig = true;
|
|
|
|
psr_context->psrExitLinkTrainingRequired =
|
|
|
|
psr_config->psr_exit_link_training_required;
|
|
|
|
psr_context->sdpTransmitLineNumDeadline =
|
|
|
|
psr_config->psr_sdp_transmit_line_num_deadline;
|
|
|
|
psr_context->psrFrameCaptureIndicationReq =
|
|
|
|
psr_config->psr_frame_capture_indication_req;
|
|
|
|
|
|
|
|
psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
|
|
|
|
|
|
|
|
psr_context->numberOfControllers =
|
|
|
|
link->dc->res_pool->timing_generator_count;
|
|
|
|
|
|
|
|
psr_context->rfb_update_auto_en = true;
|
|
|
|
|
|
|
|
/* 2 frames before enter PSR. */
|
|
|
|
psr_context->timehyst_frames = 2;
|
|
|
|
/* half a frame
|
|
|
|
* (units in 100 lines, i.e. a value of 1 represents 100 lines)
|
|
|
|
*/
|
|
|
|
psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
|
|
|
|
psr_context->aux_repeats = 10;
|
|
|
|
|
|
|
|
psr_context->psr_level.u32all = 0;
|
|
|
|
|
|
|
|
/*skip power down the single pipe since it blocks the cstate*/
|
|
|
|
if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
|
|
|
|
switch (link->ctx->asic_id.chip_family) {
|
|
|
|
case FAMILY_YELLOW_CARP:
|
|
|
|
case AMDGPU_FAMILY_GC_10_3_6:
|
|
|
|
case AMDGPU_FAMILY_GC_11_0_1:
|
|
|
|
if (dc->debug.disable_z10 || dc->debug.psr_skip_crtc_disable)
|
|
|
|
psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* SMU will perform additional powerdown sequence.
|
|
|
|
* For unsupported ASICs, set psr_level flag to skip PSR
|
|
|
|
* static screen notification to SMU.
|
|
|
|
* (Always set for DAL2, did not check ASIC)
|
|
|
|
*/
|
|
|
|
psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
|
|
|
|
psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
|
|
|
|
|
|
|
|
/* Complete PSR entry before aborting to prevent intermittent
|
|
|
|
* freezes on certain eDPs
|
|
|
|
*/
|
|
|
|
psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
|
|
|
|
|
|
|
|
/* Disable ALPM first for compatible non-ALPM panel now */
|
|
|
|
psr_context->psr_level.bits.DISABLE_ALPM = 0;
|
|
|
|
psr_context->psr_level.bits.ALPM_DEFAULT_PD_MODE = 1;
|
|
|
|
|
|
|
|
/* Controls additional delay after remote frame capture before
|
|
|
|
* continuing power down, default = 0
|
|
|
|
*/
|
|
|
|
psr_context->frame_delay = 0;
|
|
|
|
|
2023-01-10 08:53:55 +00:00
|
|
|
psr_context->dsc_slice_height = psr_config->dsc_slice_height;
|
|
|
|
|
2022-12-19 19:54:31 +00:00
|
|
|
if (psr) {
|
|
|
|
link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
|
|
|
|
link, psr_context, panel_inst);
|
|
|
|
link->psr_settings.psr_power_opt = 0;
|
|
|
|
link->psr_settings.psr_allow_active = 0;
|
|
|
|
} else {
|
|
|
|
link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* psr_enabled == 0 indicates setup_psr did not succeed, but this
|
|
|
|
* should not happen since firmware should be running at this point
|
|
|
|
*/
|
|
|
|
if (link->psr_settings.psr_feature_enabled == 0)
|
|
|
|
ASSERT(0);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2023-02-23 22:04:47 +00:00
|
|
|
void edp_get_psr_residency(const struct dc_link *link, uint32_t *residency)
|
2022-12-19 19:54:31 +00:00
|
|
|
{
|
|
|
|
struct dc *dc = link->ctx->dc;
|
|
|
|
struct dmub_psr *psr = dc->res_pool->psr;
|
|
|
|
unsigned int panel_inst;
|
|
|
|
|
|
|
|
if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
|
|
|
|
return;
|
|
|
|
|
|
|
|
// PSR residency measurements only supported on DMCUB
|
|
|
|
if (psr != NULL && link->psr_settings.psr_feature_enabled)
|
|
|
|
psr->funcs->psr_get_residency(psr, residency, panel_inst);
|
|
|
|
else
|
|
|
|
*residency = 0;
|
|
|
|
}
|
2023-02-23 22:04:47 +00:00
|
|
|
bool edp_set_sink_vtotal_in_psr_active(const struct dc_link *link, uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
|
2022-12-19 19:54:31 +00:00
|
|
|
{
|
|
|
|
struct dc *dc = link->ctx->dc;
|
|
|
|
struct dmub_psr *psr = dc->res_pool->psr;
|
|
|
|
|
|
|
|
if (psr == NULL || !link->psr_settings.psr_feature_enabled || !link->psr_settings.psr_vtotal_control_support)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
psr->funcs->psr_set_sink_vtotal_in_psr_active(psr, psr_vtotal_idle, psr_vtotal_su);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2023-05-12 18:23:11 +00:00
|
|
|
bool edp_set_replay_allow_active(struct dc_link *link, const bool *allow_active,
|
|
|
|
bool wait, bool force_static, const unsigned int *power_opts)
|
|
|
|
{
|
|
|
|
struct dc *dc = link->ctx->dc;
|
|
|
|
struct dmub_replay *replay = dc->res_pool->replay;
|
|
|
|
unsigned int panel_inst;
|
|
|
|
|
|
|
|
if (replay == NULL && force_static)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
/* Set power optimization flag */
|
|
|
|
if (power_opts && link->replay_settings.replay_power_opt_active != *power_opts) {
|
2024-02-15 13:08:16 +00:00
|
|
|
if (replay != NULL && link->replay_settings.replay_feature_enabled &&
|
|
|
|
replay->funcs->replay_set_power_opt) {
|
2023-05-12 18:23:11 +00:00
|
|
|
replay->funcs->replay_set_power_opt(replay, *power_opts, panel_inst);
|
|
|
|
link->replay_settings.replay_power_opt_active = *power_opts;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Activate or deactivate Replay */
|
|
|
|
if (allow_active && link->replay_settings.replay_allow_active != *allow_active) {
|
|
|
|
// TODO: Handle mux change case if force_static is set
|
|
|
|
// If force_static is set, just change the replay_allow_active state directly
|
|
|
|
if (replay != NULL && link->replay_settings.replay_feature_enabled)
|
|
|
|
replay->funcs->replay_enable(replay, *allow_active, wait, panel_inst);
|
|
|
|
link->replay_settings.replay_allow_active = *allow_active;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool edp_get_replay_state(const struct dc_link *link, uint64_t *state)
|
|
|
|
{
|
|
|
|
struct dc *dc = link->ctx->dc;
|
|
|
|
struct dmub_replay *replay = dc->res_pool->replay;
|
|
|
|
unsigned int panel_inst;
|
|
|
|
enum replay_state pr_state = REPLAY_STATE_0;
|
|
|
|
|
|
|
|
if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (replay != NULL && link->replay_settings.replay_feature_enabled)
|
|
|
|
replay->funcs->replay_get_state(replay, &pr_state, panel_inst);
|
|
|
|
*state = pr_state;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream)
|
|
|
|
{
|
|
|
|
/* To-do: Setup Replay */
|
2024-01-08 15:50:28 +00:00
|
|
|
struct dc *dc;
|
|
|
|
struct dmub_replay *replay;
|
2023-05-12 18:23:11 +00:00
|
|
|
int i;
|
|
|
|
unsigned int panel_inst;
|
|
|
|
struct replay_context replay_context = { 0 };
|
|
|
|
unsigned int lineTimeInNs = 0;
|
|
|
|
|
|
|
|
|
|
|
|
union replay_enable_and_configuration replay_config;
|
|
|
|
|
|
|
|
union dpcd_alpm_configuration alpm_config;
|
|
|
|
|
|
|
|
replay_context.controllerId = CONTROLLER_ID_UNDEFINED;
|
|
|
|
|
|
|
|
if (!link)
|
|
|
|
return false;
|
|
|
|
|
2024-01-08 15:50:28 +00:00
|
|
|
dc = link->ctx->dc;
|
|
|
|
|
|
|
|
replay = dc->res_pool->replay;
|
|
|
|
|
2023-05-12 18:23:11 +00:00
|
|
|
if (!replay)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
replay_context.aux_inst = link->ddc->ddc_pin->hw_info.ddc_channel;
|
|
|
|
replay_context.digbe_inst = link->link_enc->transmitter;
|
|
|
|
replay_context.digfe_inst = link->link_enc->preferred_engine;
|
|
|
|
|
|
|
|
for (i = 0; i < MAX_PIPES; i++) {
|
|
|
|
if (dc->current_state->res_ctx.pipe_ctx[i].stream
|
|
|
|
== stream) {
|
|
|
|
/* dmcu -1 for all controller id values,
|
|
|
|
* therefore +1 here
|
|
|
|
*/
|
|
|
|
replay_context.controllerId =
|
|
|
|
dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
lineTimeInNs =
|
|
|
|
((stream->timing.h_total * 1000000) /
|
|
|
|
(stream->timing.pix_clk_100hz / 10)) + 1;
|
|
|
|
|
|
|
|
replay_context.line_time_in_ns = lineTimeInNs;
|
|
|
|
|
2024-01-08 15:50:28 +00:00
|
|
|
link->replay_settings.replay_feature_enabled =
|
2023-05-12 18:23:11 +00:00
|
|
|
replay->funcs->replay_copy_settings(replay, link, &replay_context, panel_inst);
|
|
|
|
if (link->replay_settings.replay_feature_enabled) {
|
|
|
|
|
|
|
|
replay_config.bits.FREESYNC_PANEL_REPLAY_MODE = 1;
|
|
|
|
replay_config.bits.TIMING_DESYNC_ERROR_VERIFICATION =
|
|
|
|
link->replay_settings.config.replay_timing_sync_supported;
|
|
|
|
replay_config.bits.STATE_TRANSITION_ERROR_DETECTION = 1;
|
|
|
|
dm_helpers_dp_write_dpcd(link->ctx, link,
|
|
|
|
DP_SINK_PR_ENABLE_AND_CONFIGURATION,
|
|
|
|
(uint8_t *)&(replay_config.raw), sizeof(uint8_t));
|
|
|
|
|
|
|
|
memset(&alpm_config, 0, sizeof(alpm_config));
|
|
|
|
alpm_config.bits.ENABLE = 1;
|
|
|
|
dm_helpers_dp_write_dpcd(
|
|
|
|
link->ctx,
|
|
|
|
link,
|
|
|
|
DP_RECEIVER_ALPM_CONFIG,
|
|
|
|
&alpm_config.raw,
|
|
|
|
sizeof(alpm_config.raw));
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2023-10-27 03:00:36 +00:00
|
|
|
/*
|
|
|
|
* This is general Interface for Replay to set an 32 bit variable to dmub
|
|
|
|
* replay_FW_Message_type: Indicates which instruction or variable pass to DMUB
|
|
|
|
* cmd_data: Value of the config.
|
|
|
|
*/
|
|
|
|
bool edp_send_replay_cmd(struct dc_link *link,
|
|
|
|
enum replay_FW_Message_type msg,
|
2023-11-07 07:00:03 +00:00
|
|
|
union dmub_replay_cmd_set *cmd_data)
|
2023-10-27 03:00:36 +00:00
|
|
|
{
|
|
|
|
struct dc *dc = link->ctx->dc;
|
|
|
|
struct dmub_replay *replay = dc->res_pool->replay;
|
|
|
|
unsigned int panel_inst;
|
|
|
|
|
|
|
|
if (!replay)
|
|
|
|
return false;
|
|
|
|
|
2023-11-08 03:31:50 +00:00
|
|
|
DC_LOGGER_INIT(link->ctx->logger);
|
|
|
|
|
|
|
|
if (dc_get_edp_link_panel_inst(dc, link, &panel_inst))
|
|
|
|
cmd_data->panel_inst = panel_inst;
|
|
|
|
else {
|
|
|
|
DC_LOG_DC("%s(): get edp panel inst fail ", __func__);
|
2023-10-27 03:00:36 +00:00
|
|
|
return false;
|
2023-11-08 03:31:50 +00:00
|
|
|
}
|
2023-10-27 03:00:36 +00:00
|
|
|
|
2023-11-08 03:31:50 +00:00
|
|
|
replay->funcs->replay_send_cmd(replay, msg, cmd_data);
|
2023-10-27 03:00:36 +00:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2023-05-12 18:23:11 +00:00
|
|
|
bool edp_set_coasting_vtotal(struct dc_link *link, uint16_t coasting_vtotal)
|
|
|
|
{
|
|
|
|
struct dc *dc = link->ctx->dc;
|
|
|
|
struct dmub_replay *replay = dc->res_pool->replay;
|
|
|
|
unsigned int panel_inst;
|
|
|
|
|
|
|
|
if (!replay)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (coasting_vtotal && link->replay_settings.coasting_vtotal != coasting_vtotal) {
|
|
|
|
replay->funcs->replay_set_coasting_vtotal(replay, coasting_vtotal, panel_inst);
|
|
|
|
link->replay_settings.coasting_vtotal = coasting_vtotal;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool edp_replay_residency(const struct dc_link *link,
|
|
|
|
unsigned int *residency, const bool is_start, const bool is_alpm)
|
|
|
|
{
|
|
|
|
struct dc *dc = link->ctx->dc;
|
|
|
|
struct dmub_replay *replay = dc->res_pool->replay;
|
|
|
|
unsigned int panel_inst;
|
|
|
|
|
|
|
|
if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (replay != NULL && link->replay_settings.replay_feature_enabled)
|
|
|
|
replay->funcs->replay_residency(replay, panel_inst, residency, is_start, is_alpm);
|
|
|
|
else
|
|
|
|
*residency = 0;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2023-12-01 06:15:45 +00:00
|
|
|
bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link,
|
|
|
|
const unsigned int *power_opts, uint16_t coasting_vtotal)
|
|
|
|
{
|
|
|
|
struct dc *dc = link->ctx->dc;
|
|
|
|
struct dmub_replay *replay = dc->res_pool->replay;
|
|
|
|
unsigned int panel_inst;
|
|
|
|
|
|
|
|
if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
/* Only both power and coasting vtotal changed, this func could return true */
|
|
|
|
if (power_opts && link->replay_settings.replay_power_opt_active != *power_opts &&
|
|
|
|
coasting_vtotal && link->replay_settings.coasting_vtotal != coasting_vtotal) {
|
|
|
|
if (link->replay_settings.replay_feature_enabled &&
|
|
|
|
replay->funcs->replay_set_power_opt_and_coasting_vtotal) {
|
|
|
|
replay->funcs->replay_set_power_opt_and_coasting_vtotal(replay,
|
|
|
|
*power_opts, panel_inst, coasting_vtotal);
|
|
|
|
link->replay_settings.replay_power_opt_active = *power_opts;
|
|
|
|
link->replay_settings.coasting_vtotal = coasting_vtotal;
|
|
|
|
} else
|
|
|
|
return false;
|
|
|
|
} else
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2022-12-19 19:54:31 +00:00
|
|
|
static struct abm *get_abm_from_stream_res(const struct dc_link *link)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
struct dc *dc = link->ctx->dc;
|
|
|
|
struct abm *abm = NULL;
|
|
|
|
|
|
|
|
for (i = 0; i < MAX_PIPES; i++) {
|
|
|
|
struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
|
|
|
|
struct dc_stream_state *stream = pipe_ctx.stream;
|
|
|
|
|
|
|
|
if (stream && stream->link == link) {
|
|
|
|
abm = pipe_ctx.stream_res.abm;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return abm;
|
|
|
|
}
|
|
|
|
|
2023-02-15 17:50:59 +00:00
|
|
|
int edp_get_backlight_level(const struct dc_link *link)
|
2022-12-19 19:54:31 +00:00
|
|
|
{
|
|
|
|
struct abm *abm = get_abm_from_stream_res(link);
|
|
|
|
struct panel_cntl *panel_cntl = link->panel_cntl;
|
|
|
|
struct dc *dc = link->ctx->dc;
|
|
|
|
struct dmcu *dmcu = dc->res_pool->dmcu;
|
|
|
|
bool fw_set_brightness = true;
|
|
|
|
|
|
|
|
if (dmcu)
|
|
|
|
fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
|
|
|
|
|
|
|
|
if (!fw_set_brightness && panel_cntl->funcs->get_current_backlight)
|
|
|
|
return panel_cntl->funcs->get_current_backlight(panel_cntl);
|
|
|
|
else if (abm != NULL && abm->funcs->get_current_backlight != NULL)
|
|
|
|
return (int) abm->funcs->get_current_backlight(abm);
|
|
|
|
else
|
|
|
|
return DC_ERROR_UNEXPECTED;
|
|
|
|
}
|
|
|
|
|
2023-02-15 17:50:59 +00:00
|
|
|
int edp_get_target_backlight_pwm(const struct dc_link *link)
|
2022-12-19 19:54:31 +00:00
|
|
|
{
|
|
|
|
struct abm *abm = get_abm_from_stream_res(link);
|
|
|
|
|
|
|
|
if (abm == NULL || abm->funcs->get_target_backlight == NULL)
|
|
|
|
return DC_ERROR_UNEXPECTED;
|
|
|
|
|
|
|
|
return (int) abm->funcs->get_target_backlight(abm);
|
|
|
|
}
|