2022-02-21 21:03:58 +00:00
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/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "../dmub_srv.h"
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#include "dmub_reg.h"
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#include "dmub_dcn32.h"
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2023-08-08 20:25:59 +00:00
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#include "dc/dc_types.h"
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2023-08-10 15:50:52 +00:00
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#include "dc_hw_types.h"
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2022-02-21 21:03:58 +00:00
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#include "dcn/dcn_3_2_0_offset.h"
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#include "dcn/dcn_3_2_0_sh_mask.h"
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2023-08-08 20:25:59 +00:00
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#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
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2022-02-21 21:03:58 +00:00
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#define CTX dmub
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#define REGS dmub->regs_dcn32
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2023-08-08 20:25:59 +00:00
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#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
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2022-02-21 21:03:58 +00:00
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2023-08-08 20:25:59 +00:00
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void dmub_srv_dcn32_regs_init(struct dmub_srv *dmub, struct dc_context *ctx)
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{
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struct dmub_srv_dcn32_regs *regs = dmub->regs_dcn32;
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#define REG_STRUCT regs
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#define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg);
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DMUB_DCN32_REGS()
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DMCUB_INTERNAL_REGS()
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2022-02-21 21:03:58 +00:00
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#undef DMUB_SR
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2023-08-08 20:25:59 +00:00
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#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);
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DMUB_DCN32_FIELDS()
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2022-02-21 21:03:58 +00:00
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#undef DMUB_SF
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2023-08-08 20:25:59 +00:00
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#define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field);
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DMUB_DCN32_FIELDS()
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2022-02-21 21:03:58 +00:00
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#undef DMUB_SF
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2023-08-08 20:25:59 +00:00
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#undef REG_STRUCT
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}
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2022-02-21 21:03:58 +00:00
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static void dmub_dcn32_get_fb_base_offset(struct dmub_srv *dmub,
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uint64_t *fb_base,
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uint64_t *fb_offset)
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{
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uint32_t tmp;
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if (dmub->fb_base || dmub->fb_offset) {
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*fb_base = dmub->fb_base;
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*fb_offset = dmub->fb_offset;
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return;
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}
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REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
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*fb_base = (uint64_t)tmp << 24;
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REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
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*fb_offset = (uint64_t)tmp << 24;
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}
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static inline void dmub_dcn32_translate_addr(const union dmub_addr *addr_in,
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uint64_t fb_base,
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uint64_t fb_offset,
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union dmub_addr *addr_out)
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{
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addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
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}
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void dmub_dcn32_reset(struct dmub_srv *dmub)
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{
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union dmub_gpint_data_register cmd;
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const uint32_t timeout = 30;
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uint32_t in_reset, scratch, i;
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REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
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if (in_reset == 0) {
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cmd.bits.status = 1;
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cmd.bits.command_code = DMUB_GPINT__STOP_FW;
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cmd.bits.param = 0;
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dmub->hw_funcs.set_gpint(dmub, cmd);
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/**
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* Timeout covers both the ACK and the wait
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* for remaining work to finish.
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*
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* This is mostly bound by the PHY disable sequence.
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* Each register check will be greater than 1us, so
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* don't bother using udelay.
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*/
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for (i = 0; i < timeout; ++i) {
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if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
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break;
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}
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for (i = 0; i < timeout; ++i) {
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scratch = dmub->hw_funcs.get_gpint_response(dmub);
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if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
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break;
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}
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/* Force reset in case we timed out, DMCUB is likely hung. */
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}
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REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);
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REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
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REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
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REG_WRITE(DMCUB_INBOX1_RPTR, 0);
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REG_WRITE(DMCUB_INBOX1_WPTR, 0);
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REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
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REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
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2022-05-13 01:16:42 +00:00
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REG_WRITE(DMCUB_OUTBOX0_RPTR, 0);
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REG_WRITE(DMCUB_OUTBOX0_WPTR, 0);
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2022-02-21 21:03:58 +00:00
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REG_WRITE(DMCUB_SCRATCH0, 0);
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2022-02-23 15:23:25 +00:00
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/* Clear the GPINT command manually so we don't reset again. */
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cmd.all = 0;
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dmub->hw_funcs.set_gpint(dmub, cmd);
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2022-02-21 21:03:58 +00:00
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}
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void dmub_dcn32_reset_release(struct dmub_srv *dmub)
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{
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REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
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REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
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REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
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REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);
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}
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void dmub_dcn32_backdoor_load(struct dmub_srv *dmub,
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const struct dmub_window *cw0,
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const struct dmub_window *cw1)
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{
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union dmub_addr offset;
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uint64_t fb_base, fb_offset;
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dmub_dcn32_get_fb_base_offset(dmub, &fb_base, &fb_offset);
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REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
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dmub_dcn32_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
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REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
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REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
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REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
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REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
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DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
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DMCUB_REGION3_CW0_ENABLE, 1);
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dmub_dcn32_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
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REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
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REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
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REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
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REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
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DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
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DMCUB_REGION3_CW1_ENABLE, 1);
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REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
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0x20);
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}
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void dmub_dcn32_backdoor_load_zfb_mode(struct dmub_srv *dmub,
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const struct dmub_window *cw0,
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const struct dmub_window *cw1)
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{
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union dmub_addr offset;
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REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
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offset = cw0->offset;
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REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
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REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
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REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
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REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
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DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
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DMCUB_REGION3_CW0_ENABLE, 1);
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offset = cw1->offset;
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REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
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REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
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REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
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REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
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DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
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DMCUB_REGION3_CW1_ENABLE, 1);
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REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
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0x20);
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}
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void dmub_dcn32_setup_windows(struct dmub_srv *dmub,
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const struct dmub_window *cw2,
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const struct dmub_window *cw3,
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const struct dmub_window *cw4,
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const struct dmub_window *cw5,
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2024-01-30 20:24:56 +00:00
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const struct dmub_window *cw6,
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const struct dmub_window *region6)
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2022-02-21 21:03:58 +00:00
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{
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union dmub_addr offset;
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offset = cw3->offset;
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REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
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REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
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REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
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REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
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DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
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DMCUB_REGION3_CW3_ENABLE, 1);
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offset = cw4->offset;
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REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
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REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
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REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
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REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
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DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
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DMCUB_REGION3_CW4_ENABLE, 1);
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offset = cw5->offset;
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REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
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REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
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REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
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REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
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DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
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DMCUB_REGION3_CW5_ENABLE, 1);
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REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
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REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
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REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
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DMCUB_REGION5_TOP_ADDRESS,
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cw5->region.top - cw5->region.base - 1,
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DMCUB_REGION5_ENABLE, 1);
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offset = cw6->offset;
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REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
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REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
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REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
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REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
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DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
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DMCUB_REGION3_CW6_ENABLE, 1);
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}
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void dmub_dcn32_setup_mailbox(struct dmub_srv *dmub,
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const struct dmub_region *inbox1)
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{
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REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
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REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
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}
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2023-04-10 15:23:37 +00:00
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uint32_t dmub_dcn32_get_inbox1_wptr(struct dmub_srv *dmub)
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{
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return REG_READ(DMCUB_INBOX1_WPTR);
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}
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2022-02-21 21:03:58 +00:00
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uint32_t dmub_dcn32_get_inbox1_rptr(struct dmub_srv *dmub)
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{
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return REG_READ(DMCUB_INBOX1_RPTR);
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}
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void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
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{
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REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
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}
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void dmub_dcn32_setup_out_mailbox(struct dmub_srv *dmub,
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const struct dmub_region *outbox1)
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{
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REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
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REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
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}
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uint32_t dmub_dcn32_get_outbox1_wptr(struct dmub_srv *dmub)
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{
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/**
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* outbox1 wptr register is accessed without locks (dal & dc)
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* and to be called only by dmub_srv_stat_get_notification()
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*/
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return REG_READ(DMCUB_OUTBOX1_WPTR);
|
|
|
|
}
|
|
|
|
|
|
|
|
void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
|
|
|
|
{
|
|
|
|
/**
|
|
|
|
* outbox1 rptr register is accessed without locks (dal & dc)
|
|
|
|
* and to be called only by dmub_srv_stat_get_notification()
|
|
|
|
*/
|
|
|
|
REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool dmub_dcn32_is_hw_init(struct dmub_srv *dmub)
|
|
|
|
{
|
2022-04-14 20:57:17 +00:00
|
|
|
union dmub_fw_boot_status status;
|
2022-02-21 21:03:58 +00:00
|
|
|
uint32_t is_hw_init;
|
|
|
|
|
2022-04-14 20:57:17 +00:00
|
|
|
status.all = REG_READ(DMCUB_SCRATCH0);
|
2022-02-21 21:03:58 +00:00
|
|
|
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init);
|
|
|
|
|
2022-04-14 20:57:17 +00:00
|
|
|
return is_hw_init != 0 && status.bits.dal_fw;
|
2022-02-21 21:03:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
bool dmub_dcn32_is_supported(struct dmub_srv *dmub)
|
|
|
|
{
|
|
|
|
uint32_t supported = 0;
|
|
|
|
|
|
|
|
REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
|
|
|
|
|
|
|
|
return supported;
|
|
|
|
}
|
|
|
|
|
|
|
|
void dmub_dcn32_set_gpint(struct dmub_srv *dmub,
|
|
|
|
union dmub_gpint_data_register reg)
|
|
|
|
{
|
|
|
|
REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool dmub_dcn32_is_gpint_acked(struct dmub_srv *dmub,
|
|
|
|
union dmub_gpint_data_register reg)
|
|
|
|
{
|
|
|
|
union dmub_gpint_data_register test;
|
|
|
|
|
|
|
|
reg.bits.status = 0;
|
|
|
|
test.all = REG_READ(DMCUB_GPINT_DATAIN1);
|
|
|
|
|
|
|
|
return test.all == reg.all;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t dmub_dcn32_get_gpint_response(struct dmub_srv *dmub)
|
|
|
|
{
|
|
|
|
return REG_READ(DMCUB_SCRATCH7);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t dmub_dcn32_get_gpint_dataout(struct dmub_srv *dmub)
|
|
|
|
{
|
|
|
|
uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);
|
|
|
|
|
|
|
|
REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0);
|
|
|
|
|
|
|
|
REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
|
|
|
|
REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1);
|
|
|
|
REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0);
|
|
|
|
|
|
|
|
REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1);
|
|
|
|
|
|
|
|
return dataout;
|
|
|
|
}
|
|
|
|
|
|
|
|
union dmub_fw_boot_status dmub_dcn32_get_fw_boot_status(struct dmub_srv *dmub)
|
|
|
|
{
|
|
|
|
union dmub_fw_boot_status status;
|
|
|
|
|
|
|
|
status.all = REG_READ(DMCUB_SCRATCH0);
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
void dmub_dcn32_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
|
|
|
|
{
|
|
|
|
union dmub_fw_boot_options boot_options = {0};
|
|
|
|
|
|
|
|
boot_options.bits.z10_disable = params->disable_z10;
|
|
|
|
|
|
|
|
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
|
|
|
|
}
|
|
|
|
|
|
|
|
void dmub_dcn32_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
|
|
|
|
{
|
|
|
|
union dmub_fw_boot_options boot_options;
|
|
|
|
boot_options.all = REG_READ(DMCUB_SCRATCH14);
|
|
|
|
boot_options.bits.skip_phy_init_panel_sequence = skip;
|
|
|
|
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
|
|
|
|
}
|
|
|
|
|
|
|
|
void dmub_dcn32_setup_outbox0(struct dmub_srv *dmub,
|
|
|
|
const struct dmub_region *outbox0)
|
|
|
|
{
|
|
|
|
REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
|
|
|
|
|
|
|
|
REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t dmub_dcn32_get_outbox0_wptr(struct dmub_srv *dmub)
|
|
|
|
{
|
|
|
|
return REG_READ(DMCUB_OUTBOX0_WPTR);
|
|
|
|
}
|
|
|
|
|
|
|
|
void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
|
|
|
|
{
|
|
|
|
REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub)
|
|
|
|
{
|
|
|
|
return REG_READ(DMCUB_TIMER_CURRENT);
|
|
|
|
}
|
|
|
|
|
|
|
|
void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
|
|
|
|
{
|
|
|
|
uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;
|
|
|
|
uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;
|
|
|
|
|
|
|
|
if (!dmub || !diag_data)
|
|
|
|
return;
|
|
|
|
|
|
|
|
memset(diag_data, 0, sizeof(*diag_data));
|
|
|
|
|
|
|
|
diag_data->dmcub_version = dmub->fw_version;
|
|
|
|
|
|
|
|
diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0);
|
|
|
|
diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1);
|
|
|
|
diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2);
|
|
|
|
diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3);
|
|
|
|
diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4);
|
|
|
|
diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5);
|
|
|
|
diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6);
|
|
|
|
diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7);
|
|
|
|
diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8);
|
|
|
|
diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9);
|
|
|
|
diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10);
|
|
|
|
diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11);
|
|
|
|
diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12);
|
|
|
|
diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13);
|
|
|
|
diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14);
|
|
|
|
diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15);
|
2023-04-10 18:15:14 +00:00
|
|
|
diag_data->scratch[16] = REG_READ(DMCUB_SCRATCH16);
|
2022-02-21 21:03:58 +00:00
|
|
|
|
|
|
|
diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
|
|
|
|
diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
|
|
|
|
diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
|
|
|
|
|
|
|
|
diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
|
|
|
|
diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
|
|
|
|
diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
|
|
|
|
|
|
|
|
diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
|
|
|
|
diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
|
|
|
|
diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
|
|
|
|
|
|
|
|
REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
|
|
|
|
diag_data->is_dmcub_enabled = is_dmub_enabled;
|
|
|
|
|
|
|
|
REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
|
|
|
|
diag_data->is_dmcub_soft_reset = is_soft_reset;
|
|
|
|
|
|
|
|
REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
|
|
|
|
diag_data->is_dmcub_secure_reset = is_sec_reset;
|
|
|
|
|
|
|
|
REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
|
|
|
|
diag_data->is_traceport_en = is_traceport_enabled;
|
|
|
|
|
|
|
|
REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
|
|
|
|
diag_data->is_cw0_enabled = is_cw0_enabled;
|
|
|
|
|
|
|
|
REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
|
|
|
|
diag_data->is_cw6_enabled = is_cw6_enabled;
|
2023-04-10 18:15:14 +00:00
|
|
|
|
|
|
|
diag_data->gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);
|
2022-02-21 21:03:58 +00:00
|
|
|
}
|
|
|
|
void dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv *dmub)
|
|
|
|
{
|
|
|
|
/* DMCUB_REGION3_TMR_AXI_SPACE values:
|
|
|
|
* 0b011 (0x3) - FB physical address
|
|
|
|
* 0b100 (0x4) - GPU virtual address
|
|
|
|
*
|
|
|
|
* Default value is 0x3 (FB Physical address for TMR). When programming
|
|
|
|
* DMUB to be in system memory, change to 0x4. The system memory allocated
|
|
|
|
* is accessible by both GPU and CPU, so we use GPU virtual address.
|
|
|
|
*/
|
|
|
|
REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4);
|
|
|
|
}
|
|
|
|
|
|
|
|
void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)
|
|
|
|
{
|
|
|
|
REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all);
|
|
|
|
}
|
|
|
|
|
|
|
|
void dmub_dcn32_clear_inbox0_ack_register(struct dmub_srv *dmub)
|
|
|
|
{
|
|
|
|
REG_WRITE(DMCUB_SCRATCH17, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub)
|
|
|
|
{
|
|
|
|
return REG_READ(DMCUB_SCRATCH17);
|
|
|
|
}
|
2023-08-10 15:50:52 +00:00
|
|
|
|
|
|
|
void dmub_dcn32_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index)
|
|
|
|
{
|
|
|
|
uint32_t index = 0;
|
|
|
|
|
|
|
|
if (subvp_index == 0) {
|
|
|
|
index = REG_READ(DMCUB_SCRATCH15);
|
|
|
|
if (index) {
|
|
|
|
REG_WRITE(DMCUB_SCRATCH9, addr->grph.addr.low_part);
|
|
|
|
REG_WRITE(DMCUB_SCRATCH11, addr->grph.meta_addr.low_part);
|
|
|
|
} else {
|
|
|
|
REG_WRITE(DMCUB_SCRATCH12, addr->grph.addr.low_part);
|
|
|
|
REG_WRITE(DMCUB_SCRATCH13, addr->grph.meta_addr.low_part);
|
|
|
|
}
|
|
|
|
REG_WRITE(DMCUB_SCRATCH15, !index);
|
|
|
|
} else if (subvp_index == 1) {
|
|
|
|
index = REG_READ(DMCUB_SCRATCH23);
|
|
|
|
if (index) {
|
|
|
|
REG_WRITE(DMCUB_SCRATCH18, addr->grph.addr.low_part);
|
|
|
|
REG_WRITE(DMCUB_SCRATCH19, addr->grph.meta_addr.low_part);
|
|
|
|
} else {
|
|
|
|
REG_WRITE(DMCUB_SCRATCH20, addr->grph.addr.low_part);
|
|
|
|
REG_WRITE(DMCUB_SCRATCH22, addr->grph.meta_addr.low_part);
|
|
|
|
}
|
|
|
|
REG_WRITE(DMCUB_SCRATCH23, !index);
|
|
|
|
} else {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|