2019-06-04 08:11:33 +00:00
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// SPDX-License-Identifier: GPL-2.0-only
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2017-08-28 16:59:20 +00:00
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/*
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* GPIO based serio bus driver for bit banging the PS/2 protocol
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*
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* Author: Danilo Krummrich <danilokrummrich@dk-develop.de>
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*/
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#include <linux/gpio/consumer.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/serio.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/workqueue.h>
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#include <linux/completion.h>
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#include <linux/mutex.h>
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#include <linux/preempt.h>
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#include <linux/property.h>
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#include <linux/of.h>
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#include <linux/jiffies.h>
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#include <linux/delay.h>
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2022-02-15 22:39:12 +00:00
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#include <linux/timekeeping.h>
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2017-08-28 16:59:20 +00:00
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#define DRIVER_NAME "ps2-gpio"
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#define PS2_MODE_RX 0
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#define PS2_MODE_TX 1
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#define PS2_START_BIT 0
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#define PS2_DATA_BIT0 1
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#define PS2_DATA_BIT1 2
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#define PS2_DATA_BIT2 3
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#define PS2_DATA_BIT3 4
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#define PS2_DATA_BIT4 5
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#define PS2_DATA_BIT5 6
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#define PS2_DATA_BIT6 7
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#define PS2_DATA_BIT7 8
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#define PS2_PARITY_BIT 9
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#define PS2_STOP_BIT 10
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2022-02-15 22:44:26 +00:00
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#define PS2_ACK_BIT 11
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2017-08-28 16:59:20 +00:00
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#define PS2_DEV_RET_ACK 0xfa
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#define PS2_DEV_RET_NACK 0xfe
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#define PS2_CMD_RESEND 0xfe
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2022-02-15 22:39:12 +00:00
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/*
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* The PS2 protocol specifies a clock frequency between 10kHz and 16.7kHz,
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* therefore the maximal interrupt interval should be 100us and the minimum
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* interrupt interval should be ~60us. Let's allow +/- 20us for frequency
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* deviations and interrupt latency.
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*
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* The data line must be samples after ~30us to 50us after the falling edge,
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* since the device updates the data line at the rising edge.
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*
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* ___ ______ ______ ______ ___
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* \ / \ / \ / \ /
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* \ / \ / \ / \ /
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* \______/ \______/ \______/ \______/
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*
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* |-----------------| |--------|
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* 60us/100us 30us/50us
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*/
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#define PS2_CLK_FREQ_MIN_HZ 10000
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#define PS2_CLK_FREQ_MAX_HZ 16700
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#define PS2_CLK_MIN_INTERVAL_US ((1000 * 1000) / PS2_CLK_FREQ_MAX_HZ)
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#define PS2_CLK_MAX_INTERVAL_US ((1000 * 1000) / PS2_CLK_FREQ_MIN_HZ)
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#define PS2_IRQ_MIN_INTERVAL_US (PS2_CLK_MIN_INTERVAL_US - 20)
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#define PS2_IRQ_MAX_INTERVAL_US (PS2_CLK_MAX_INTERVAL_US + 20)
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2017-08-28 16:59:20 +00:00
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struct ps2_gpio_data {
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struct device *dev;
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struct serio *serio;
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unsigned char mode;
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struct gpio_desc *gpio_clk;
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struct gpio_desc *gpio_data;
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bool write_enable;
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int irq;
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2022-02-15 22:39:12 +00:00
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ktime_t t_irq_now;
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ktime_t t_irq_last;
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2022-02-15 21:49:13 +00:00
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struct {
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unsigned char cnt;
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unsigned char byte;
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} rx;
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struct {
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unsigned char cnt;
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unsigned char byte;
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2022-02-15 22:39:12 +00:00
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ktime_t t_xfer_start;
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ktime_t t_xfer_end;
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2022-02-15 21:49:13 +00:00
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struct completion complete;
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struct mutex mutex;
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struct delayed_work work;
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} tx;
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2017-08-28 16:59:20 +00:00
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};
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static int ps2_gpio_open(struct serio *serio)
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{
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struct ps2_gpio_data *drvdata = serio->port_data;
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2022-02-15 22:39:12 +00:00
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drvdata->t_irq_last = 0;
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drvdata->tx.t_xfer_end = 0;
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2017-08-28 16:59:20 +00:00
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enable_irq(drvdata->irq);
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return 0;
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}
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static void ps2_gpio_close(struct serio *serio)
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{
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struct ps2_gpio_data *drvdata = serio->port_data;
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2022-02-15 21:49:13 +00:00
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flush_delayed_work(&drvdata->tx.work);
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2017-08-28 16:59:20 +00:00
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disable_irq(drvdata->irq);
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}
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static int __ps2_gpio_write(struct serio *serio, unsigned char val)
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{
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struct ps2_gpio_data *drvdata = serio->port_data;
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disable_irq_nosync(drvdata->irq);
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gpiod_direction_output(drvdata->gpio_clk, 0);
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drvdata->mode = PS2_MODE_TX;
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2022-02-15 21:49:13 +00:00
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drvdata->tx.byte = val;
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2017-08-28 16:59:20 +00:00
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2022-02-15 21:49:13 +00:00
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schedule_delayed_work(&drvdata->tx.work, usecs_to_jiffies(200));
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2017-08-28 16:59:20 +00:00
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return 0;
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}
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static int ps2_gpio_write(struct serio *serio, unsigned char val)
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{
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struct ps2_gpio_data *drvdata = serio->port_data;
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int ret = 0;
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if (in_task()) {
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2022-02-15 21:49:13 +00:00
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mutex_lock(&drvdata->tx.mutex);
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2017-08-28 16:59:20 +00:00
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__ps2_gpio_write(serio, val);
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2022-02-15 21:49:13 +00:00
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if (!wait_for_completion_timeout(&drvdata->tx.complete,
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2017-08-28 16:59:20 +00:00
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msecs_to_jiffies(10000)))
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ret = SERIO_TIMEOUT;
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2022-02-15 21:49:13 +00:00
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mutex_unlock(&drvdata->tx.mutex);
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2017-08-28 16:59:20 +00:00
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} else {
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__ps2_gpio_write(serio, val);
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}
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return ret;
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}
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static void ps2_gpio_tx_work_fn(struct work_struct *work)
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{
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struct delayed_work *dwork = to_delayed_work(work);
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struct ps2_gpio_data *drvdata = container_of(dwork,
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2022-02-15 21:49:13 +00:00
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struct ps2_gpio_data,
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tx.work);
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2017-08-28 16:59:20 +00:00
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2022-02-15 22:39:12 +00:00
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drvdata->tx.t_xfer_start = ktime_get();
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2017-08-28 16:59:20 +00:00
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enable_irq(drvdata->irq);
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gpiod_direction_output(drvdata->gpio_data, 0);
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gpiod_direction_input(drvdata->gpio_clk);
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}
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static irqreturn_t ps2_gpio_irq_rx(struct ps2_gpio_data *drvdata)
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{
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unsigned char byte, cnt;
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int data;
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int rxflags = 0;
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2022-02-15 22:39:12 +00:00
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s64 us_delta;
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2017-08-28 16:59:20 +00:00
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2022-02-15 21:49:13 +00:00
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byte = drvdata->rx.byte;
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cnt = drvdata->rx.cnt;
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2017-08-28 16:59:20 +00:00
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2022-02-15 22:39:12 +00:00
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drvdata->t_irq_now = ktime_get();
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/*
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* We need to consider spurious interrupts happening right after
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* a TX xfer finished.
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*/
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us_delta = ktime_us_delta(drvdata->t_irq_now, drvdata->tx.t_xfer_end);
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if (unlikely(us_delta < PS2_IRQ_MIN_INTERVAL_US))
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goto end;
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2017-08-28 16:59:20 +00:00
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2022-02-15 22:39:12 +00:00
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us_delta = ktime_us_delta(drvdata->t_irq_now, drvdata->t_irq_last);
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if (us_delta > PS2_IRQ_MAX_INTERVAL_US && cnt) {
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2017-08-28 16:59:20 +00:00
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dev_err(drvdata->dev,
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"RX: timeout, probably we missed an interrupt\n");
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goto err;
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2022-02-15 22:39:12 +00:00
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} else if (unlikely(us_delta < PS2_IRQ_MIN_INTERVAL_US)) {
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/* Ignore spurious IRQs. */
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goto end;
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2017-08-28 16:59:20 +00:00
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}
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2022-02-15 22:39:12 +00:00
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drvdata->t_irq_last = drvdata->t_irq_now;
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2017-08-28 16:59:20 +00:00
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data = gpiod_get_value(drvdata->gpio_data);
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if (unlikely(data < 0)) {
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dev_err(drvdata->dev, "RX: failed to get data gpio val: %d\n",
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data);
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goto err;
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}
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switch (cnt) {
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case PS2_START_BIT:
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/* start bit should be low */
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if (unlikely(data)) {
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dev_err(drvdata->dev, "RX: start bit should be low\n");
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goto err;
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}
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break;
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case PS2_DATA_BIT0:
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case PS2_DATA_BIT1:
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case PS2_DATA_BIT2:
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case PS2_DATA_BIT3:
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case PS2_DATA_BIT4:
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case PS2_DATA_BIT5:
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case PS2_DATA_BIT6:
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case PS2_DATA_BIT7:
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/* processing data bits */
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if (data)
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byte |= (data << (cnt - 1));
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break;
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case PS2_PARITY_BIT:
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/* check odd parity */
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if (!((hweight8(byte) & 1) ^ data)) {
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rxflags |= SERIO_PARITY;
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dev_warn(drvdata->dev, "RX: parity error\n");
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if (!drvdata->write_enable)
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goto err;
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}
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2022-02-15 22:45:43 +00:00
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break;
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case PS2_STOP_BIT:
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/* stop bit should be high */
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if (unlikely(!data)) {
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dev_err(drvdata->dev, "RX: stop bit should be high\n");
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goto err;
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}
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2017-08-28 16:59:20 +00:00
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2022-02-15 22:39:12 +00:00
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/*
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* Do not send spurious ACK's and NACK's when write fn is
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2017-08-28 16:59:20 +00:00
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* not provided.
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*/
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if (!drvdata->write_enable) {
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if (byte == PS2_DEV_RET_NACK)
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goto err;
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else if (byte == PS2_DEV_RET_ACK)
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break;
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}
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serio_interrupt(drvdata->serio, byte, rxflags);
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dev_dbg(drvdata->dev, "RX: sending byte 0x%x\n", byte);
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2022-02-15 22:45:43 +00:00
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2017-08-28 16:59:20 +00:00
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cnt = byte = 0;
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2022-02-15 22:39:12 +00:00
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2017-08-28 16:59:20 +00:00
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goto end; /* success */
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default:
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dev_err(drvdata->dev, "RX: got out of sync with the device\n");
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goto err;
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}
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cnt++;
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goto end; /* success */
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err:
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cnt = byte = 0;
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__ps2_gpio_write(drvdata->serio, PS2_CMD_RESEND);
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end:
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2022-02-15 21:49:13 +00:00
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drvdata->rx.cnt = cnt;
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drvdata->rx.byte = byte;
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2017-08-28 16:59:20 +00:00
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return IRQ_HANDLED;
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}
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static irqreturn_t ps2_gpio_irq_tx(struct ps2_gpio_data *drvdata)
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{
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unsigned char byte, cnt;
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int data;
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2022-02-15 22:39:12 +00:00
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s64 us_delta;
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2017-08-28 16:59:20 +00:00
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2022-02-15 21:49:13 +00:00
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cnt = drvdata->tx.cnt;
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byte = drvdata->tx.byte;
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2017-08-28 16:59:20 +00:00
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2022-02-15 22:39:12 +00:00
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drvdata->t_irq_now = ktime_get();
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/*
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* There might be pending IRQs since we disabled IRQs in
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* __ps2_gpio_write(). We can expect at least one clock period until
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* the device generates the first falling edge after releasing the
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* clock line.
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*/
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us_delta = ktime_us_delta(drvdata->t_irq_now,
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drvdata->tx.t_xfer_start);
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if (unlikely(us_delta < PS2_CLK_MIN_INTERVAL_US))
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goto end;
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2017-08-28 16:59:20 +00:00
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2022-02-15 22:39:12 +00:00
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us_delta = ktime_us_delta(drvdata->t_irq_now, drvdata->t_irq_last);
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if (us_delta > PS2_IRQ_MAX_INTERVAL_US && cnt > 1) {
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2017-08-28 16:59:20 +00:00
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dev_err(drvdata->dev,
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"TX: timeout, probably we missed an interrupt\n");
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goto err;
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2022-02-15 22:39:12 +00:00
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} else if (unlikely(us_delta < PS2_IRQ_MIN_INTERVAL_US)) {
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/* Ignore spurious IRQs. */
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goto end;
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2017-08-28 16:59:20 +00:00
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}
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2022-02-15 22:39:12 +00:00
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drvdata->t_irq_last = drvdata->t_irq_now;
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2017-08-28 16:59:20 +00:00
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switch (cnt) {
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case PS2_START_BIT:
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/* should never happen */
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dev_err(drvdata->dev,
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"TX: start bit should have been sent already\n");
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goto err;
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case PS2_DATA_BIT0:
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case PS2_DATA_BIT1:
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case PS2_DATA_BIT2:
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case PS2_DATA_BIT3:
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case PS2_DATA_BIT4:
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case PS2_DATA_BIT5:
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case PS2_DATA_BIT6:
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case PS2_DATA_BIT7:
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data = byte & BIT(cnt - 1);
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gpiod_set_value(drvdata->gpio_data, data);
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break;
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case PS2_PARITY_BIT:
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/* do odd parity */
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data = !(hweight8(byte) & 1);
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|
|
gpiod_set_value(drvdata->gpio_data, data);
|
|
|
|
break;
|
|
|
|
case PS2_STOP_BIT:
|
|
|
|
/* release data line to generate stop bit */
|
|
|
|
gpiod_direction_input(drvdata->gpio_data);
|
|
|
|
break;
|
|
|
|
case PS2_ACK_BIT:
|
|
|
|
data = gpiod_get_value(drvdata->gpio_data);
|
|
|
|
if (data) {
|
|
|
|
dev_warn(drvdata->dev, "TX: received NACK, retry\n");
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
2022-02-15 22:39:12 +00:00
|
|
|
drvdata->tx.t_xfer_end = ktime_get();
|
2017-08-28 16:59:20 +00:00
|
|
|
drvdata->mode = PS2_MODE_RX;
|
2022-02-15 21:49:13 +00:00
|
|
|
complete(&drvdata->tx.complete);
|
2017-08-28 16:59:20 +00:00
|
|
|
|
|
|
|
cnt = 1;
|
|
|
|
goto end; /* success */
|
|
|
|
default:
|
2022-02-15 22:39:12 +00:00
|
|
|
/*
|
|
|
|
* Probably we missed the stop bit. Therefore we release data
|
2017-08-28 16:59:20 +00:00
|
|
|
* line and try again.
|
|
|
|
*/
|
|
|
|
gpiod_direction_input(drvdata->gpio_data);
|
|
|
|
dev_err(drvdata->dev, "TX: got out of sync with the device\n");
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
cnt++;
|
|
|
|
goto end; /* success */
|
|
|
|
|
|
|
|
err:
|
|
|
|
cnt = 1;
|
|
|
|
gpiod_direction_input(drvdata->gpio_data);
|
2022-02-15 21:49:13 +00:00
|
|
|
__ps2_gpio_write(drvdata->serio, drvdata->tx.byte);
|
2017-08-28 16:59:20 +00:00
|
|
|
end:
|
2022-02-15 21:49:13 +00:00
|
|
|
drvdata->tx.cnt = cnt;
|
2017-08-28 16:59:20 +00:00
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t ps2_gpio_irq(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct ps2_gpio_data *drvdata = dev_id;
|
|
|
|
|
|
|
|
return drvdata->mode ? ps2_gpio_irq_tx(drvdata) :
|
|
|
|
ps2_gpio_irq_rx(drvdata);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ps2_gpio_get_props(struct device *dev,
|
|
|
|
struct ps2_gpio_data *drvdata)
|
|
|
|
{
|
2022-02-15 22:55:44 +00:00
|
|
|
enum gpiod_flags gflags;
|
|
|
|
|
|
|
|
/* Enforce open drain, since this is required by the PS/2 bus. */
|
|
|
|
gflags = GPIOD_IN | GPIOD_FLAGS_BIT_OPEN_DRAIN;
|
|
|
|
|
|
|
|
drvdata->gpio_data = devm_gpiod_get(dev, "data", gflags);
|
2017-08-28 16:59:20 +00:00
|
|
|
if (IS_ERR(drvdata->gpio_data)) {
|
|
|
|
dev_err(dev, "failed to request data gpio: %ld",
|
|
|
|
PTR_ERR(drvdata->gpio_data));
|
|
|
|
return PTR_ERR(drvdata->gpio_data);
|
|
|
|
}
|
|
|
|
|
2022-02-15 22:55:44 +00:00
|
|
|
drvdata->gpio_clk = devm_gpiod_get(dev, "clk", gflags);
|
2017-08-28 16:59:20 +00:00
|
|
|
if (IS_ERR(drvdata->gpio_clk)) {
|
|
|
|
dev_err(dev, "failed to request clock gpio: %ld",
|
|
|
|
PTR_ERR(drvdata->gpio_clk));
|
|
|
|
return PTR_ERR(drvdata->gpio_clk);
|
|
|
|
}
|
|
|
|
|
|
|
|
drvdata->write_enable = device_property_read_bool(dev,
|
|
|
|
"write-enable");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ps2_gpio_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct ps2_gpio_data *drvdata;
|
|
|
|
struct serio *serio;
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
int error;
|
|
|
|
|
|
|
|
drvdata = devm_kzalloc(dev, sizeof(struct ps2_gpio_data), GFP_KERNEL);
|
|
|
|
serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
|
|
|
|
if (!drvdata || !serio) {
|
|
|
|
error = -ENOMEM;
|
|
|
|
goto err_free_serio;
|
|
|
|
}
|
|
|
|
|
|
|
|
error = ps2_gpio_get_props(dev, drvdata);
|
|
|
|
if (error)
|
|
|
|
goto err_free_serio;
|
|
|
|
|
|
|
|
if (gpiod_cansleep(drvdata->gpio_data) ||
|
|
|
|
gpiod_cansleep(drvdata->gpio_clk)) {
|
|
|
|
dev_err(dev, "GPIO data or clk are connected via slow bus\n");
|
|
|
|
error = -EINVAL;
|
2017-10-23 23:40:42 +00:00
|
|
|
goto err_free_serio;
|
2017-08-28 16:59:20 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
drvdata->irq = platform_get_irq(pdev, 0);
|
|
|
|
if (drvdata->irq < 0) {
|
|
|
|
error = drvdata->irq;
|
|
|
|
goto err_free_serio;
|
|
|
|
}
|
|
|
|
|
|
|
|
error = devm_request_irq(dev, drvdata->irq, ps2_gpio_irq,
|
|
|
|
IRQF_NO_THREAD, DRIVER_NAME, drvdata);
|
|
|
|
if (error) {
|
|
|
|
dev_err(dev, "failed to request irq %d: %d\n",
|
|
|
|
drvdata->irq, error);
|
|
|
|
goto err_free_serio;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Keep irq disabled until serio->open is called. */
|
|
|
|
disable_irq(drvdata->irq);
|
|
|
|
|
|
|
|
serio->id.type = SERIO_8042;
|
|
|
|
serio->open = ps2_gpio_open;
|
|
|
|
serio->close = ps2_gpio_close;
|
2022-02-15 22:39:12 +00:00
|
|
|
/*
|
|
|
|
* Write can be enabled in platform/dt data, but possibly it will not
|
2017-08-28 16:59:20 +00:00
|
|
|
* work because of the tough timings.
|
|
|
|
*/
|
|
|
|
serio->write = drvdata->write_enable ? ps2_gpio_write : NULL;
|
|
|
|
serio->port_data = drvdata;
|
|
|
|
serio->dev.parent = dev;
|
2022-08-18 22:05:06 +00:00
|
|
|
strscpy(serio->name, dev_name(dev), sizeof(serio->name));
|
|
|
|
strscpy(serio->phys, dev_name(dev), sizeof(serio->phys));
|
2017-08-28 16:59:20 +00:00
|
|
|
|
|
|
|
drvdata->serio = serio;
|
|
|
|
drvdata->dev = dev;
|
|
|
|
drvdata->mode = PS2_MODE_RX;
|
|
|
|
|
2022-02-15 22:39:12 +00:00
|
|
|
/*
|
|
|
|
* Tx count always starts at 1, as the start bit is sent implicitly by
|
2017-08-28 16:59:20 +00:00
|
|
|
* host-to-device communication initialization.
|
|
|
|
*/
|
2022-02-15 21:49:13 +00:00
|
|
|
drvdata->tx.cnt = 1;
|
2017-08-28 16:59:20 +00:00
|
|
|
|
2022-02-15 21:49:13 +00:00
|
|
|
INIT_DELAYED_WORK(&drvdata->tx.work, ps2_gpio_tx_work_fn);
|
|
|
|
init_completion(&drvdata->tx.complete);
|
|
|
|
mutex_init(&drvdata->tx.mutex);
|
2017-08-28 16:59:20 +00:00
|
|
|
|
|
|
|
serio_register_port(serio);
|
|
|
|
platform_set_drvdata(pdev, drvdata);
|
|
|
|
|
|
|
|
return 0; /* success */
|
|
|
|
|
|
|
|
err_free_serio:
|
|
|
|
kfree(serio);
|
|
|
|
return error;
|
|
|
|
}
|
|
|
|
|
2023-09-20 12:58:16 +00:00
|
|
|
static void ps2_gpio_remove(struct platform_device *pdev)
|
2017-08-28 16:59:20 +00:00
|
|
|
{
|
|
|
|
struct ps2_gpio_data *drvdata = platform_get_drvdata(pdev);
|
|
|
|
|
|
|
|
serio_unregister_port(drvdata->serio);
|
|
|
|
}
|
|
|
|
|
|
|
|
#if defined(CONFIG_OF)
|
|
|
|
static const struct of_device_id ps2_gpio_match[] = {
|
|
|
|
{ .compatible = "ps2-gpio", },
|
|
|
|
{ },
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, ps2_gpio_match);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static struct platform_driver ps2_gpio_driver = {
|
|
|
|
.probe = ps2_gpio_probe,
|
2023-09-20 12:58:16 +00:00
|
|
|
.remove_new = ps2_gpio_remove,
|
2017-08-28 16:59:20 +00:00
|
|
|
.driver = {
|
|
|
|
.name = DRIVER_NAME,
|
|
|
|
.of_match_table = of_match_ptr(ps2_gpio_match),
|
|
|
|
},
|
|
|
|
};
|
|
|
|
module_platform_driver(ps2_gpio_driver);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Danilo Krummrich <danilokrummrich@dk-develop.de>");
|
|
|
|
MODULE_DESCRIPTION("GPIO PS2 driver");
|
|
|
|
MODULE_LICENSE("GPL v2");
|