greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
/*
|
2015-12-16 10:59:18 +00:00
|
|
|
* Arche Platform driver to enable Unipro link.
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
*
|
|
|
|
* Copyright 2014-2015 Google Inc.
|
|
|
|
* Copyright 2014-2015 Linaro Ltd.
|
|
|
|
*
|
|
|
|
* Released under the GPLv2 only.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/module.h>
|
|
|
|
#include <linux/init.h>
|
|
|
|
#include <linux/interrupt.h>
|
|
|
|
#include <linux/irq.h>
|
|
|
|
#include <linux/sched.h>
|
|
|
|
#include <linux/pm.h>
|
|
|
|
#include <linux/delay.h>
|
|
|
|
#include <linux/platform_device.h>
|
|
|
|
#include <linux/gpio.h>
|
2015-12-16 10:59:17 +00:00
|
|
|
#include <linux/clk.h>
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
#include <linux/of_platform.h>
|
|
|
|
#include <linux/of_gpio.h>
|
|
|
|
#include <linux/of_irq.h>
|
|
|
|
#include <linux/spinlock.h>
|
|
|
|
#include <linux/regulator/consumer.h>
|
|
|
|
#include <linux/pinctrl/consumer.h>
|
|
|
|
|
2015-12-16 10:59:18 +00:00
|
|
|
struct arche_platform_drvdata {
|
2015-12-16 10:59:17 +00:00
|
|
|
/* Control GPIO signals to and from AP <=> SVC */
|
|
|
|
int svc_reset_gpio;
|
|
|
|
bool is_reset_act_hi;
|
|
|
|
int svc_sysboot_gpio;
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
|
2015-12-16 10:59:17 +00:00
|
|
|
unsigned int svc_refclk_req;
|
|
|
|
struct clk *svc_ref_clk;
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
|
|
|
|
struct pinctrl *pinctrl;
|
|
|
|
struct pinctrl_state *pin_default;
|
|
|
|
|
2015-12-16 10:59:17 +00:00
|
|
|
int num_apbs;
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
};
|
|
|
|
|
2015-12-16 10:59:17 +00:00
|
|
|
static inline void svc_reset_onoff(unsigned int gpio, bool onoff)
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
{
|
2015-12-16 10:59:17 +00:00
|
|
|
gpio_set_value(gpio, onoff);
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
}
|
|
|
|
|
2015-12-16 10:59:18 +00:00
|
|
|
static void arche_platform_cleanup(struct arche_platform_drvdata *arche_pdata)
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
{
|
|
|
|
/* As part of exit, put APB back in reset state */
|
2015-12-16 10:59:18 +00:00
|
|
|
if (gpio_is_valid(arche_pdata->svc_reset_gpio))
|
|
|
|
svc_reset_onoff(arche_pdata->svc_reset_gpio,
|
|
|
|
arche_pdata->is_reset_act_hi);
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
}
|
|
|
|
|
2015-12-16 10:59:18 +00:00
|
|
|
static int arche_platform_probe(struct platform_device *pdev)
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
{
|
2015-12-16 10:59:18 +00:00
|
|
|
struct arche_platform_drvdata *arche_pdata;
|
2015-12-16 10:59:17 +00:00
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct device_node *np = dev->of_node;
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
int ret;
|
|
|
|
|
2015-12-16 10:59:18 +00:00
|
|
|
arche_pdata = devm_kzalloc(&pdev->dev, sizeof(*arche_pdata), GFP_KERNEL);
|
|
|
|
if (!arche_pdata)
|
2015-12-16 10:59:17 +00:00
|
|
|
return -ENOMEM;
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
|
2015-12-16 10:59:17 +00:00
|
|
|
/* setup svc reset gpio */
|
2015-12-16 10:59:18 +00:00
|
|
|
arche_pdata->is_reset_act_hi = of_property_read_bool(np,
|
|
|
|
"svc,reset-active-high");
|
|
|
|
arche_pdata->svc_reset_gpio = of_get_named_gpio(np, "svc,reset-gpio", 0);
|
|
|
|
if (arche_pdata->svc_reset_gpio < 0) {
|
2015-12-16 10:59:17 +00:00
|
|
|
dev_err(dev, "failed to get reset-gpio\n");
|
2015-12-16 10:59:18 +00:00
|
|
|
return -ENODEV;
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
}
|
2015-12-16 10:59:18 +00:00
|
|
|
ret = devm_gpio_request(dev, arche_pdata->svc_reset_gpio, "svc-reset");
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
if (ret) {
|
2015-12-16 10:59:17 +00:00
|
|
|
dev_err(dev, "failed to request svc-reset gpio:%d\n", ret);
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
return ret;
|
|
|
|
}
|
2015-12-16 10:59:18 +00:00
|
|
|
ret = gpio_direction_output(arche_pdata->svc_reset_gpio,
|
|
|
|
arche_pdata->is_reset_act_hi);
|
2015-12-16 10:59:17 +00:00
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "failed to set svc-reset gpio dir:%d\n", ret);
|
|
|
|
return ret;
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
}
|
|
|
|
|
2015-12-16 10:59:18 +00:00
|
|
|
arche_pdata->svc_sysboot_gpio = of_get_named_gpio(np,
|
|
|
|
"svc,sysboot-gpio", 0);
|
|
|
|
if (arche_pdata->svc_sysboot_gpio < 0) {
|
2015-12-16 10:59:17 +00:00
|
|
|
dev_err(dev, "failed to get sysboot gpio\n");
|
2015-12-16 10:59:18 +00:00
|
|
|
return -ENODEV;
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
}
|
2015-12-16 10:59:18 +00:00
|
|
|
ret = devm_gpio_request(dev, arche_pdata->svc_sysboot_gpio, "sysboot0");
|
2015-12-16 10:59:17 +00:00
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "failed to request sysboot0 gpio:%d\n", ret);
|
|
|
|
return ret;
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
}
|
2015-12-16 10:59:18 +00:00
|
|
|
ret = gpio_direction_output(arche_pdata->svc_sysboot_gpio, 0);
|
2015-12-16 10:59:17 +00:00
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "failed to set svc-reset gpio dir:%d\n", ret);
|
|
|
|
return ret;
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
}
|
|
|
|
|
2015-12-16 10:59:17 +00:00
|
|
|
/* setup the clock request gpio first */
|
2015-12-16 10:59:18 +00:00
|
|
|
arche_pdata->svc_refclk_req = of_get_named_gpio(np,
|
|
|
|
"svc,refclk-req-gpio", 0);
|
|
|
|
if (arche_pdata->svc_refclk_req < 0) {
|
2015-12-16 10:59:17 +00:00
|
|
|
dev_err(dev, "failed to get svc clock-req gpio\n");
|
|
|
|
return -ENODEV;
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
}
|
2015-12-16 10:59:18 +00:00
|
|
|
ret = devm_gpio_request(dev, arche_pdata->svc_refclk_req, "svc-clk-req");
|
2015-12-16 10:59:17 +00:00
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "failed to request svc-clk-req gpio: %d\n", ret);
|
|
|
|
return ret;
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
}
|
2015-12-16 10:59:18 +00:00
|
|
|
ret = gpio_direction_input(arche_pdata->svc_refclk_req);
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
if (ret) {
|
2015-12-16 10:59:17 +00:00
|
|
|
dev_err(dev, "failed to set svc-clk-req gpio dir :%d\n", ret);
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-12-16 10:59:17 +00:00
|
|
|
/* setup refclk2 to follow the pin */
|
2015-12-16 10:59:18 +00:00
|
|
|
arche_pdata->svc_ref_clk = devm_clk_get(dev, "svc_ref_clk");
|
|
|
|
if (IS_ERR(arche_pdata->svc_ref_clk)) {
|
|
|
|
ret = PTR_ERR(arche_pdata->svc_ref_clk);
|
2015-12-16 10:59:17 +00:00
|
|
|
dev_err(dev, "failed to get svc_ref_clk: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
2015-12-16 10:59:18 +00:00
|
|
|
ret = clk_prepare_enable(arche_pdata->svc_ref_clk);
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
if (ret) {
|
2015-12-16 10:59:17 +00:00
|
|
|
dev_err(dev, "failed to enable svc_ref_clk: %d\n", ret);
|
|
|
|
return ret;
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
}
|
|
|
|
|
2015-12-16 10:59:18 +00:00
|
|
|
platform_set_drvdata(pdev, arche_pdata);
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
|
2015-12-16 10:59:17 +00:00
|
|
|
/* bring SVC out of reset */
|
2015-12-16 10:59:18 +00:00
|
|
|
svc_reset_onoff(arche_pdata->svc_reset_gpio,
|
|
|
|
!arche_pdata->is_reset_act_hi);
|
|
|
|
|
|
|
|
arche_pdata->num_apbs = of_get_child_count(np);
|
|
|
|
dev_dbg(dev, "Number of APB's available - %d\n", arche_pdata->num_apbs);
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
|
2015-12-16 10:59:17 +00:00
|
|
|
/* probe all childs here */
|
|
|
|
ret = of_platform_populate(np, NULL, NULL, dev);
|
|
|
|
if (ret)
|
|
|
|
dev_err(dev, "no child node found\n");
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
|
2015-12-16 10:59:17 +00:00
|
|
|
dev_info(dev, "Device registered successfully\n");
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-12-16 10:59:18 +00:00
|
|
|
static int arche_platform_remove(struct platform_device *pdev)
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
{
|
2015-12-16 10:59:18 +00:00
|
|
|
struct arche_platform_drvdata *arche_pdata = platform_get_drvdata(pdev);
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
|
2015-12-16 10:59:18 +00:00
|
|
|
if (arche_pdata)
|
|
|
|
arche_platform_cleanup(arche_pdata);
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-12-16 10:59:18 +00:00
|
|
|
static int arche_platform_suspend(struct device *dev)
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
{
|
|
|
|
/*
|
|
|
|
* If timing profile premits, we may shutdown bridge
|
|
|
|
* completely
|
|
|
|
*
|
|
|
|
* TODO: sequence ??
|
|
|
|
*
|
|
|
|
* Also, need to make sure we meet precondition for unipro suspend
|
|
|
|
* Precondition: Definition ???
|
|
|
|
*/
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-12-16 10:59:18 +00:00
|
|
|
static int arche_platform_resume(struct device *dev)
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
{
|
|
|
|
/*
|
|
|
|
* Atleast for ES2 we have to meet the delay requirement between
|
|
|
|
* unipro switch and AP bridge init, depending on whether bridge is in
|
|
|
|
* OFF state or standby state.
|
|
|
|
*
|
|
|
|
* Based on whether bridge is in standby or OFF state we may have to
|
|
|
|
* assert multiple signals. Please refer to WDM spec, for more info.
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-12-16 10:59:18 +00:00
|
|
|
static SIMPLE_DEV_PM_OPS(arche_platform_pm_ops,
|
|
|
|
arche_platform_suspend,
|
|
|
|
arche_platform_resume);
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
|
2015-12-16 10:59:18 +00:00
|
|
|
static struct of_device_id arche_platform_of_match[] = {
|
|
|
|
{ .compatible = "google,arche-platform", }, /* Use PID/VID of SVC device */
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
{ },
|
|
|
|
};
|
2015-12-16 10:59:18 +00:00
|
|
|
MODULE_DEVICE_TABLE(of, arche_platform_of_match);
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
|
2015-12-16 10:59:18 +00:00
|
|
|
static struct platform_driver arche_platform_device_driver = {
|
|
|
|
.probe = arche_platform_probe,
|
|
|
|
.remove = arche_platform_remove,
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
.driver = {
|
2015-12-16 10:59:18 +00:00
|
|
|
.name = "arche-platform-ctrl",
|
|
|
|
.pm = &arche_platform_pm_ops,
|
|
|
|
.of_match_table = of_match_ptr(arche_platform_of_match),
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2015-12-16 10:59:18 +00:00
|
|
|
module_platform_driver(arche_platform_device_driver);
|
greybus: platform: Add platform driver for DB3 AP bridge
With DB3, we now have AP as a master as far as AP bridges are concerned.
SVC will talk only to AP and AP will control bridges; unlike other
module interfaces.
So AP supposed to manage/control bridges in all power states including
power on reset.
During power on reset AP should follow below sequence -
Sequence (treated as a Cold Boot)
Stage-1
=======
AP:
- Power On (Power up from PMIC to AP)
- AP start booting
Since power to AP bridges are controlled through gpio, power is gated
to APB1 & 2
No ref_clk to APB available (under SVC's control)
- AP configures USB hub to enable HSIC interface to APB
- As part of platform driver probe, AP follow below sequence
- Set the pinctrl in default state
- Hold APBs in reset by pulling down reset pin
- Enable power to APB by enabling regulator and switches
- De-assert (set 'low') 'boot_ret' signal
- AP will assert (set 'high') the wake_detect signal, triggering
connect/detect event to the SVC
- AP waits for wake pulse from SVC
SVC:
- Power On (power up from PMIC to SVC)
- SVC starts booting
- SVC will de-assert reset signal to unipro switch
- Switch starts booting
- SVC confirms switch boot status using SPI (or something)
- SVC waits for 300 msec (ES2 known issue)
- SVC waits for detect/connect event from AP
Stage-2
=======
SVC:
- ON connect/detect event, SVC send back wake pulse (cold boot)
to AP over wake_detect pin, if SVC boot is completed.
AP:
- On wake pulse from SVC (for cold boot), AP de-asserts (set high')
reset signal to APB 1 and/or 2
- Bridges starts booting
- Eventually Unipro linkup occurs
Testing:
- Build tested against Helium kernel
- Due to unavailability of MSM and DB3 platform, only minimal testing
has been done.
- Code has been modified for validation on Helium + SDB platform.
Mostly dts changes for gpio numbers
And debug messages to check gpio values
- On Helium + SDB platform, with addition of debug messages validated
the sequence.
TODO list:
- Currently _only_ supports power on sequence (cold boot).
Both warm and cold boot support. Cold and Warm boot is
differentiated based on pulse width of wake_detect signal
>=5 msec = Cold boot else Warm boot
- No support for Power management
So the "power-down", "power-off", "wake_in" and "wake_out"
signals are not explored/implemented.
- Support for Work thread
repetitive wake signal if no response from peer
May required for PM support, as we have delays in the sequences
- pinctrl states, specially to make sure we enable right pullup or pulldown
when we set wake_detect pin to input
- Convert gpio list into an array, and associated xxx-gpio-name property
Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
2015-10-21 11:20:20 +00:00
|
|
|
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_AUTHOR("Vaibhav Hiremath <vaibhav.hiremath@linaro.org>");
|
2015-12-16 10:59:18 +00:00
|
|
|
MODULE_DESCRIPTION("Arche Platform Driver");
|