2018-05-16 08:04:29 +00:00
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// SPDX-License-Identifier: GPL-2.0
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2014-05-19 16:43:28 +00:00
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/*
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* Copyright (c) 2014 Marvell Technology Group Ltd.
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*
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* Alexandre Belloni <alexandre.belloni@free-electrons.com>
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/berlin2q.h>
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#include "berlin2-div.h"
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#include "berlin2-pll.h"
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#include "common.h"
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#define REG_PINMUX0 0x0018
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#define REG_PINMUX5 0x002c
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#define REG_SYSPLLCTL0 0x0030
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#define REG_SYSPLLCTL4 0x0040
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#define REG_CLKENABLE 0x00e8
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#define REG_CLKSELECT0 0x00ec
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#define REG_CLKSELECT1 0x00f0
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#define REG_CLKSELECT2 0x00f4
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#define REG_CLKSWITCH0 0x00f8
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#define REG_CLKSWITCH1 0x00fc
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#define REG_SW_GENERIC0 0x0110
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#define REG_SW_GENERIC3 0x011c
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#define REG_SDIO0XIN_CLKCTL 0x0158
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#define REG_SDIO1XIN_CLKCTL 0x015c
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2015-10-15 18:55:55 +00:00
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#define MAX_CLKS 28
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2016-08-16 22:40:52 +00:00
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static struct clk_hw_onecell_data *clk_data;
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2014-05-19 16:43:28 +00:00
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static DEFINE_SPINLOCK(lock);
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static void __iomem *gbase;
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static void __iomem *cpupll_base;
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enum {
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REFCLK,
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SYSPLL, CPUPLL,
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AVPLL_B1, AVPLL_B2, AVPLL_B3, AVPLL_B4,
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AVPLL_B5, AVPLL_B6, AVPLL_B7, AVPLL_B8,
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};
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static const char *clk_names[] = {
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[REFCLK] = "refclk",
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[SYSPLL] = "syspll",
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[CPUPLL] = "cpupll",
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[AVPLL_B1] = "avpll_b1",
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[AVPLL_B2] = "avpll_b2",
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[AVPLL_B3] = "avpll_b3",
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[AVPLL_B4] = "avpll_b4",
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[AVPLL_B5] = "avpll_b5",
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[AVPLL_B6] = "avpll_b6",
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[AVPLL_B7] = "avpll_b7",
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[AVPLL_B8] = "avpll_b8",
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};
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static const struct berlin2_pll_map bg2q_pll_map __initconst = {
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.vcodiv = {1, 0, 2, 0, 3, 4, 0, 6, 8},
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.mult = 1,
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.fbdiv_shift = 7,
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.rfdiv_shift = 2,
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.divsel_shift = 9,
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};
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static const u8 default_parent_ids[] = {
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SYSPLL, AVPLL_B4, AVPLL_B5, AVPLL_B6, AVPLL_B7, SYSPLL
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};
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static const struct berlin2_div_data bg2q_divs[] __initconst = {
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{
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.name = "sys",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 0),
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BERLIN2_PLL_SELECT(REG_CLKSELECT0, 0),
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BERLIN2_DIV_SELECT(REG_CLKSELECT0, 3),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 3),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 4),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 5),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = CLK_IGNORE_UNUSED,
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},
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{
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.name = "drmfigo",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 17),
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BERLIN2_PLL_SELECT(REG_CLKSELECT0, 6),
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BERLIN2_DIV_SELECT(REG_CLKSELECT0, 9),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 6),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 7),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 8),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "cfg",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 1),
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BERLIN2_PLL_SELECT(REG_CLKSELECT0, 12),
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BERLIN2_DIV_SELECT(REG_CLKSELECT0, 15),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 9),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 10),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 11),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "gfx2d",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 4),
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BERLIN2_PLL_SELECT(REG_CLKSELECT0, 18),
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BERLIN2_DIV_SELECT(REG_CLKSELECT0, 21),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 12),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 13),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 14),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "zsp",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 6),
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BERLIN2_PLL_SELECT(REG_CLKSELECT0, 24),
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BERLIN2_DIV_SELECT(REG_CLKSELECT0, 27),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 15),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 16),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 17),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "perif",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 7),
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BERLIN2_PLL_SELECT(REG_CLKSELECT1, 0),
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BERLIN2_DIV_SELECT(REG_CLKSELECT1, 3),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 18),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 19),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 20),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = CLK_IGNORE_UNUSED,
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},
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{
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.name = "pcube",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 2),
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BERLIN2_PLL_SELECT(REG_CLKSELECT1, 6),
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BERLIN2_DIV_SELECT(REG_CLKSELECT1, 9),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 21),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 22),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 23),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "vscope",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 3),
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BERLIN2_PLL_SELECT(REG_CLKSELECT1, 12),
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BERLIN2_DIV_SELECT(REG_CLKSELECT1, 15),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 24),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 25),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 26),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "nfc_ecc",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 19),
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BERLIN2_PLL_SELECT(REG_CLKSELECT1, 18),
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BERLIN2_DIV_SELECT(REG_CLKSELECT1, 21),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 27),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 28),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 29),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "vpp",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 21),
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BERLIN2_PLL_SELECT(REG_CLKSELECT1, 24),
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BERLIN2_DIV_SELECT(REG_CLKSELECT1, 27),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 30),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 31),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 0),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "app",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_DIV_GATE(REG_CLKENABLE, 20),
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BERLIN2_PLL_SELECT(REG_CLKSELECT2, 0),
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BERLIN2_DIV_SELECT(REG_CLKSELECT2, 3),
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BERLIN2_PLL_SWITCH(REG_CLKSWITCH1, 1),
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BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 2),
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BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 3),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "sdio0xin",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_SINGLE_DIV(REG_SDIO0XIN_CLKCTL),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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{
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.name = "sdio1xin",
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.parent_ids = default_parent_ids,
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.num_parents = ARRAY_SIZE(default_parent_ids),
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.map = {
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BERLIN2_SINGLE_DIV(REG_SDIO1XIN_CLKCTL),
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},
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.div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
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.flags = 0,
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},
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};
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static const struct berlin2_gate_data bg2q_gates[] __initconst = {
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{ "gfx2daxi", "perif", 5 },
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{ "geth0", "perif", 8 },
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{ "sata", "perif", 9 },
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{ "ahbapb", "perif", 10, CLK_IGNORE_UNUSED },
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{ "usb0", "perif", 11 },
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{ "usb1", "perif", 12 },
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{ "usb2", "perif", 13 },
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{ "usb3", "perif", 14 },
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{ "pbridge", "perif", 15, CLK_IGNORE_UNUSED },
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2015-10-20 11:16:46 +00:00
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{ "sdio", "perif", 16 },
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2014-05-19 16:43:28 +00:00
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{ "nfc", "perif", 18 },
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{ "pcie", "perif", 22 },
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};
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static void __init berlin2q_clock_setup(struct device_node *np)
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{
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2015-05-15 23:40:15 +00:00
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struct device_node *parent_np = of_get_parent(np);
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2014-05-19 16:43:28 +00:00
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const char *parent_names[9];
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struct clk *clk;
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2016-08-16 22:40:52 +00:00
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struct clk_hw **hws;
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int n, ret;
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treewide: Use struct_size() for kmalloc()-family
One of the more common cases of allocation size calculations is finding
the size of a structure that has a zero-sized array at the end, along
with memory for some number of elements for that array. For example:
struct foo {
int stuff;
void *entry[];
};
instance = kmalloc(sizeof(struct foo) + sizeof(void *) * count, GFP_KERNEL);
Instead of leaving these open-coded and prone to type mistakes, we can
now use the new struct_size() helper:
instance = kmalloc(struct_size(instance, entry, count), GFP_KERNEL);
This patch makes the changes for kmalloc()-family (and kvmalloc()-family)
uses. It was done via automatic conversion with manual review for the
"CHECKME" non-standard cases noted below, using the following Coccinelle
script:
// pkey_cache = kmalloc(sizeof *pkey_cache + tprops->pkey_tbl_len *
// sizeof *pkey_cache->table, GFP_KERNEL);
@@
identifier alloc =~ "kmalloc|kzalloc|kvmalloc|kvzalloc";
expression GFP;
identifier VAR, ELEMENT;
expression COUNT;
@@
- alloc(sizeof(*VAR) + COUNT * sizeof(*VAR->ELEMENT), GFP)
+ alloc(struct_size(VAR, ELEMENT, COUNT), GFP)
// mr = kzalloc(sizeof(*mr) + m * sizeof(mr->map[0]), GFP_KERNEL);
@@
identifier alloc =~ "kmalloc|kzalloc|kvmalloc|kvzalloc";
expression GFP;
identifier VAR, ELEMENT;
expression COUNT;
@@
- alloc(sizeof(*VAR) + COUNT * sizeof(VAR->ELEMENT[0]), GFP)
+ alloc(struct_size(VAR, ELEMENT, COUNT), GFP)
// Same pattern, but can't trivially locate the trailing element name,
// or variable name.
@@
identifier alloc =~ "kmalloc|kzalloc|kvmalloc|kvzalloc";
expression GFP;
expression SOMETHING, COUNT, ELEMENT;
@@
- alloc(sizeof(SOMETHING) + COUNT * sizeof(ELEMENT), GFP)
+ alloc(CHECKME_struct_size(&SOMETHING, ELEMENT, COUNT), GFP)
Signed-off-by: Kees Cook <keescook@chromium.org>
2018-05-08 20:45:50 +00:00
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clk_data = kzalloc(struct_size(clk_data, hws, MAX_CLKS), GFP_KERNEL);
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2016-08-16 22:40:52 +00:00
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if (!clk_data)
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return;
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clk_data->num = MAX_CLKS;
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hws = clk_data->hws;
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2014-05-19 16:43:28 +00:00
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2015-05-15 23:50:34 +00:00
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|
gbase = of_iomap(parent_np, 0);
|
2014-05-19 16:43:28 +00:00
|
|
|
if (!gbase) {
|
2017-07-18 21:42:52 +00:00
|
|
|
pr_err("%pOF: Unable to map global base\n", np);
|
2014-05-19 16:43:28 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* BG2Q CPU PLL is not part of global registers */
|
2015-05-15 23:50:34 +00:00
|
|
|
cpupll_base = of_iomap(parent_np, 1);
|
2014-05-19 16:43:28 +00:00
|
|
|
if (!cpupll_base) {
|
2017-07-18 21:42:52 +00:00
|
|
|
pr_err("%pOF: Unable to map cpupll base\n", np);
|
2014-05-19 16:43:28 +00:00
|
|
|
iounmap(gbase);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* overwrite default clock names with DT provided ones */
|
|
|
|
clk = of_clk_get_by_name(np, clk_names[REFCLK]);
|
|
|
|
if (!IS_ERR(clk)) {
|
|
|
|
clk_names[REFCLK] = __clk_get_name(clk);
|
|
|
|
clk_put(clk);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* simple register PLLs */
|
2016-08-16 22:40:52 +00:00
|
|
|
ret = berlin2_pll_register(&bg2q_pll_map, gbase + REG_SYSPLLCTL0,
|
2014-05-19 16:43:28 +00:00
|
|
|
clk_names[SYSPLL], clk_names[REFCLK], 0);
|
2016-08-16 22:40:52 +00:00
|
|
|
if (ret)
|
2014-05-19 16:43:28 +00:00
|
|
|
goto bg2q_fail;
|
|
|
|
|
2016-08-16 22:40:52 +00:00
|
|
|
ret = berlin2_pll_register(&bg2q_pll_map, cpupll_base,
|
2014-05-19 16:43:28 +00:00
|
|
|
clk_names[CPUPLL], clk_names[REFCLK], 0);
|
2016-08-16 22:40:52 +00:00
|
|
|
if (ret)
|
2014-05-19 16:43:28 +00:00
|
|
|
goto bg2q_fail;
|
|
|
|
|
|
|
|
/* TODO: add BG2Q AVPLL */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* TODO: add reference clock bypass switches:
|
|
|
|
* memPLLSWBypass, cpuPLLSWBypass, and sysPLLSWBypass
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* clock divider cells */
|
|
|
|
for (n = 0; n < ARRAY_SIZE(bg2q_divs); n++) {
|
|
|
|
const struct berlin2_div_data *dd = &bg2q_divs[n];
|
|
|
|
int k;
|
|
|
|
|
|
|
|
for (k = 0; k < dd->num_parents; k++)
|
|
|
|
parent_names[k] = clk_names[dd->parent_ids[k]];
|
|
|
|
|
2016-08-16 22:40:52 +00:00
|
|
|
hws[CLKID_SYS + n] = berlin2_div_register(&dd->map, gbase,
|
2014-05-19 16:43:28 +00:00
|
|
|
dd->name, dd->div_flags, parent_names,
|
|
|
|
dd->num_parents, dd->flags, &lock);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* clock gate cells */
|
|
|
|
for (n = 0; n < ARRAY_SIZE(bg2q_gates); n++) {
|
|
|
|
const struct berlin2_gate_data *gd = &bg2q_gates[n];
|
|
|
|
|
2016-08-16 22:40:52 +00:00
|
|
|
hws[CLKID_GFX2DAXI + n] = clk_hw_register_gate(NULL, gd->name,
|
2014-05-19 16:43:28 +00:00
|
|
|
gd->parent_name, gd->flags, gbase + REG_CLKENABLE,
|
|
|
|
gd->bit_idx, 0, &lock);
|
|
|
|
}
|
|
|
|
|
2015-10-15 18:55:55 +00:00
|
|
|
/* cpuclk divider is fixed to 1 */
|
2016-08-16 22:40:52 +00:00
|
|
|
hws[CLKID_CPU] =
|
|
|
|
clk_hw_register_fixed_factor(NULL, "cpu", clk_names[CPUPLL],
|
2015-10-15 18:55:55 +00:00
|
|
|
0, 1, 1);
|
|
|
|
/* twdclk is derived from cpu/3 */
|
2016-08-16 22:40:52 +00:00
|
|
|
hws[CLKID_TWD] =
|
|
|
|
clk_hw_register_fixed_factor(NULL, "twd", "cpu", 0, 1, 3);
|
2014-05-19 16:43:28 +00:00
|
|
|
|
|
|
|
/* check for errors on leaf clocks */
|
|
|
|
for (n = 0; n < MAX_CLKS; n++) {
|
2016-08-16 22:40:52 +00:00
|
|
|
if (!IS_ERR(hws[n]))
|
2014-05-19 16:43:28 +00:00
|
|
|
continue;
|
|
|
|
|
2017-07-18 21:42:52 +00:00
|
|
|
pr_err("%pOF: Unable to register leaf clock %d\n", np, n);
|
2014-05-19 16:43:28 +00:00
|
|
|
goto bg2q_fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* register clk-provider */
|
2016-11-16 19:02:00 +00:00
|
|
|
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
|
2014-05-19 16:43:28 +00:00
|
|
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
bg2q_fail:
|
|
|
|
iounmap(cpupll_base);
|
|
|
|
iounmap(gbase);
|
|
|
|
}
|
2015-05-15 23:40:15 +00:00
|
|
|
CLK_OF_DECLARE(berlin2q_clk, "marvell,berlin2q-clk",
|
|
|
|
berlin2q_clock_setup);
|