2011-03-03 02:34:47 +00:00
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/*
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2011-06-06 14:57:03 +00:00
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* Per core/cpu state
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*
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* Used to coordinate shared registers between HT threads or
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* among events on a single PMU.
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2011-03-03 02:34:47 +00:00
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*/
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2011-08-30 23:41:05 +00:00
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2012-05-22 02:50:07 +00:00
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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2011-08-30 23:41:05 +00:00
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#include <linux/stddef.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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2011-05-26 16:22:53 +00:00
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#include <linux/export.h>
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2011-08-30 23:41:05 +00:00
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2013-06-18 00:36:48 +00:00
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#include <asm/cpufeature.h>
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2011-08-30 23:41:05 +00:00
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#include <asm/hardirq.h>
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#include <asm/apic.h>
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#include "perf_event.h"
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2011-03-03 02:34:47 +00:00
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2010-02-26 11:05:05 +00:00
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/*
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2010-02-01 14:36:30 +00:00
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* Intel PerfMon, used on Core and later.
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2010-02-26 11:05:05 +00:00
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*/
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2011-04-27 09:51:41 +00:00
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static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
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2010-02-26 11:05:05 +00:00
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{
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2012-07-06 09:59:46 +00:00
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[PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
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[PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
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[PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
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[PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
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[PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
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[PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
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[PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
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2010-02-26 11:05:05 +00:00
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};
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2011-04-27 10:02:04 +00:00
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static struct event_constraint intel_core_event_constraints[] __read_mostly =
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2010-02-26 11:05:05 +00:00
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{
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INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
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INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
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INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
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INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
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INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
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INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
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EVENT_CONSTRAINT_END
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};
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2011-04-27 10:02:04 +00:00
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static struct event_constraint intel_core2_event_constraints[] __read_mostly =
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2010-02-26 11:05:05 +00:00
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{
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2010-02-01 14:36:30 +00:00
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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2011-12-10 23:28:51 +00:00
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FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
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2010-02-26 11:05:05 +00:00
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INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
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INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
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INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
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INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
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INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
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INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
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INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
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INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
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2010-02-01 14:36:30 +00:00
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INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
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2010-02-26 11:05:05 +00:00
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INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
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EVENT_CONSTRAINT_END
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};
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2011-04-27 10:02:04 +00:00
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static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
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2010-02-26 11:05:05 +00:00
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{
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2010-02-01 14:36:30 +00:00
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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2011-12-10 23:28:51 +00:00
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FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
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2010-02-26 11:05:05 +00:00
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INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
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INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
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INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
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INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
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INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
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INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
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INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
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INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
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EVENT_CONSTRAINT_END
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};
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2011-04-27 10:02:04 +00:00
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static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
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2011-03-03 02:34:47 +00:00
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{
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2013-07-18 09:02:23 +00:00
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/* must define OFFCORE_RSP_X first, see intel_fixup_er() */
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INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
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2013-01-24 15:10:32 +00:00
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INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
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2011-03-03 02:34:47 +00:00
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EVENT_EXTRA_END
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};
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2011-04-27 10:02:04 +00:00
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static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
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2010-02-26 11:05:05 +00:00
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{
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2010-02-01 14:36:30 +00:00
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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2011-12-10 23:28:51 +00:00
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FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
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2010-02-26 11:05:05 +00:00
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INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
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INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
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INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
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2010-06-10 11:25:01 +00:00
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INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
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2010-02-26 11:05:05 +00:00
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EVENT_CONSTRAINT_END
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};
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2011-04-27 10:02:04 +00:00
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static struct event_constraint intel_snb_event_constraints[] __read_mostly =
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2011-03-02 13:27:04 +00:00
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{
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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2011-12-10 23:28:51 +00:00
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FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
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2013-03-17 13:49:57 +00:00
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INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
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INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
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INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
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INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
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2011-03-02 13:27:04 +00:00
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INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
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INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
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INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
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2013-03-08 23:22:48 +00:00
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INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
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INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
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2011-03-02 13:27:04 +00:00
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EVENT_CONSTRAINT_END
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};
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2013-02-20 10:15:12 +00:00
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static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
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{
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
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INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
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INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
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INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
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2013-09-11 15:22:22 +00:00
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INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
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2013-02-20 10:15:12 +00:00
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INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
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INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
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INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
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INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
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INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
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INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
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2013-05-03 12:11:23 +00:00
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/*
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* Errata BV98 -- MEM_*_RETIRED events can leak between counters of SMT
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* siblings; disable these events because they can corrupt unrelated
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* counters.
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*/
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INTEL_EVENT_CONSTRAINT(0xd0, 0x0), /* MEM_UOPS_RETIRED.* */
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INTEL_EVENT_CONSTRAINT(0xd1, 0x0), /* MEM_LOAD_UOPS_RETIRED.* */
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INTEL_EVENT_CONSTRAINT(0xd2, 0x0), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
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INTEL_EVENT_CONSTRAINT(0xd3, 0x0), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
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2013-02-20 10:15:12 +00:00
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EVENT_CONSTRAINT_END
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};
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2011-04-27 10:02:04 +00:00
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static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
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2011-03-03 02:34:47 +00:00
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{
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2013-07-18 09:02:23 +00:00
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/* must define OFFCORE_RSP_X first, see intel_fixup_er() */
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INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
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INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
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2013-01-24 15:10:32 +00:00
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INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
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2011-03-03 02:34:47 +00:00
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EVENT_EXTRA_END
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};
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2011-06-29 15:42:36 +00:00
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static struct event_constraint intel_v1_event_constraints[] __read_mostly =
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{
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EVENT_CONSTRAINT_END
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};
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2011-04-27 10:02:04 +00:00
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static struct event_constraint intel_gen_event_constraints[] __read_mostly =
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2010-02-26 11:05:05 +00:00
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{
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2010-02-01 14:36:30 +00:00
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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2011-12-10 23:28:51 +00:00
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FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
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2010-02-26 11:05:05 +00:00
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EVENT_CONSTRAINT_END
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};
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2013-07-18 09:02:24 +00:00
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static struct event_constraint intel_slm_event_constraints[] __read_mostly =
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{
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
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EVENT_CONSTRAINT_END
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};
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2011-06-06 14:57:12 +00:00
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static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
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2013-07-18 09:02:23 +00:00
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/* must define OFFCORE_RSP_X first, see intel_fixup_er() */
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INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
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INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
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2013-01-24 15:10:32 +00:00
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INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
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2013-04-16 11:51:43 +00:00
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EVENT_EXTRA_END
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};
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static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
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2013-07-18 09:02:23 +00:00
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/* must define OFFCORE_RSP_X first, see intel_fixup_er() */
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INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
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INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
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2013-06-07 21:22:10 +00:00
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INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
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2011-06-06 14:57:12 +00:00
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EVENT_EXTRA_END
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};
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2013-09-12 17:17:00 +00:00
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EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
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EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
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EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
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2013-01-24 15:10:32 +00:00
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struct attribute *nhm_events_attrs[] = {
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EVENT_PTR(mem_ld_nhm),
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NULL,
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};
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struct attribute *snb_events_attrs[] = {
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EVENT_PTR(mem_ld_snb),
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2013-01-24 15:10:34 +00:00
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EVENT_PTR(mem_st_snb),
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2013-01-24 15:10:32 +00:00
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NULL,
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};
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2013-06-18 00:36:48 +00:00
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static struct event_constraint intel_hsw_event_constraints[] = {
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FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
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INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.* */
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INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
|
|
|
|
|
INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
|
|
|
|
|
/* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
|
|
|
|
|
INTEL_EVENT_CONSTRAINT(0x08a3, 0x4),
|
|
|
|
|
/* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
|
|
|
|
|
INTEL_EVENT_CONSTRAINT(0x0ca3, 0x4),
|
|
|
|
|
/* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
|
|
|
|
|
INTEL_EVENT_CONSTRAINT(0x04a3, 0xf),
|
|
|
|
|
EVENT_CONSTRAINT_END
|
|
|
|
|
};
|
|
|
|
|
|
2015-02-18 02:18:05 +00:00
|
|
|
struct event_constraint intel_bdw_event_constraints[] = {
|
|
|
|
|
FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
|
|
|
|
|
FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
|
|
|
|
|
FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
|
|
|
|
|
INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
|
|
|
|
|
INTEL_EVENT_CONSTRAINT(0xa3, 0x4), /* CYCLE_ACTIVITY.* */
|
|
|
|
|
EVENT_CONSTRAINT_END
|
|
|
|
|
};
|
|
|
|
|
|
2010-02-26 11:05:05 +00:00
|
|
|
static u64 intel_pmu_event_map(int hw_event)
|
|
|
|
|
{
|
|
|
|
|
return intel_perfmon_event_map[hw_event];
|
|
|
|
|
}
|
|
|
|
|
|
2012-07-17 09:27:55 +00:00
|
|
|
#define SNB_DMND_DATA_RD (1ULL << 0)
|
|
|
|
|
#define SNB_DMND_RFO (1ULL << 1)
|
|
|
|
|
#define SNB_DMND_IFETCH (1ULL << 2)
|
|
|
|
|
#define SNB_DMND_WB (1ULL << 3)
|
|
|
|
|
#define SNB_PF_DATA_RD (1ULL << 4)
|
|
|
|
|
#define SNB_PF_RFO (1ULL << 5)
|
|
|
|
|
#define SNB_PF_IFETCH (1ULL << 6)
|
|
|
|
|
#define SNB_LLC_DATA_RD (1ULL << 7)
|
|
|
|
|
#define SNB_LLC_RFO (1ULL << 8)
|
|
|
|
|
#define SNB_LLC_IFETCH (1ULL << 9)
|
|
|
|
|
#define SNB_BUS_LOCKS (1ULL << 10)
|
|
|
|
|
#define SNB_STRM_ST (1ULL << 11)
|
|
|
|
|
#define SNB_OTHER (1ULL << 15)
|
|
|
|
|
#define SNB_RESP_ANY (1ULL << 16)
|
|
|
|
|
#define SNB_NO_SUPP (1ULL << 17)
|
|
|
|
|
#define SNB_LLC_HITM (1ULL << 18)
|
|
|
|
|
#define SNB_LLC_HITE (1ULL << 19)
|
|
|
|
|
#define SNB_LLC_HITS (1ULL << 20)
|
|
|
|
|
#define SNB_LLC_HITF (1ULL << 21)
|
|
|
|
|
#define SNB_LOCAL (1ULL << 22)
|
|
|
|
|
#define SNB_REMOTE (0xffULL << 23)
|
|
|
|
|
#define SNB_SNP_NONE (1ULL << 31)
|
|
|
|
|
#define SNB_SNP_NOT_NEEDED (1ULL << 32)
|
|
|
|
|
#define SNB_SNP_MISS (1ULL << 33)
|
|
|
|
|
#define SNB_NO_FWD (1ULL << 34)
|
|
|
|
|
#define SNB_SNP_FWD (1ULL << 35)
|
|
|
|
|
#define SNB_HITM (1ULL << 36)
|
|
|
|
|
#define SNB_NON_DRAM (1ULL << 37)
|
|
|
|
|
|
|
|
|
|
#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
|
|
|
|
|
#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
|
|
|
|
|
#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
|
|
|
|
|
|
|
|
|
|
#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
|
|
|
|
|
SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
|
|
|
|
|
SNB_HITM)
|
|
|
|
|
|
|
|
|
|
#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
|
|
|
|
|
#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
|
|
|
|
|
|
|
|
|
|
#define SNB_L3_ACCESS SNB_RESP_ANY
|
|
|
|
|
#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
|
|
|
|
|
|
|
|
|
|
static __initconst const u64 snb_hw_cache_extra_regs
|
|
|
|
|
[PERF_COUNT_HW_CACHE_MAX]
|
|
|
|
|
[PERF_COUNT_HW_CACHE_OP_MAX]
|
|
|
|
|
[PERF_COUNT_HW_CACHE_RESULT_MAX] =
|
|
|
|
|
{
|
|
|
|
|
[ C(LL ) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
|
|
|
|
|
[ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
|
|
|
|
|
[ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
|
|
|
|
|
[ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(NODE) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
|
|
|
|
|
[ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
|
|
|
|
|
[ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
|
|
|
|
|
[ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
};
|
|
|
|
|
|
2011-03-02 13:27:04 +00:00
|
|
|
static __initconst const u64 snb_hw_cache_event_ids
|
|
|
|
|
[PERF_COUNT_HW_CACHE_MAX]
|
|
|
|
|
[PERF_COUNT_HW_CACHE_OP_MAX]
|
|
|
|
|
[PERF_COUNT_HW_CACHE_RESULT_MAX] =
|
|
|
|
|
{
|
|
|
|
|
[ C(L1D) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x0,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(L1I ) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x0,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x0,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(LL ) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
2011-04-22 22:57:42 +00:00
|
|
|
/* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
|
2011-03-02 13:27:04 +00:00
|
|
|
[ C(RESULT_ACCESS) ] = 0x01b7,
|
2011-04-22 22:57:42 +00:00
|
|
|
/* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x01b7,
|
2011-03-02 13:27:04 +00:00
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
2011-04-22 22:57:42 +00:00
|
|
|
/* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
|
2011-03-02 13:27:04 +00:00
|
|
|
[ C(RESULT_ACCESS) ] = 0x01b7,
|
2011-04-22 22:57:42 +00:00
|
|
|
/* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x01b7,
|
2011-03-02 13:27:04 +00:00
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
2011-04-22 22:57:42 +00:00
|
|
|
/* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
|
2011-03-02 13:27:04 +00:00
|
|
|
[ C(RESULT_ACCESS) ] = 0x01b7,
|
2011-04-22 22:57:42 +00:00
|
|
|
/* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x01b7,
|
2011-03-02 13:27:04 +00:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(DTLB) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x0,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(ITLB) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(BPU ) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
},
|
2011-04-22 21:37:06 +00:00
|
|
|
[ C(NODE) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
2012-07-17 09:27:55 +00:00
|
|
|
[ C(RESULT_ACCESS) ] = 0x01b7,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x01b7,
|
2011-04-22 21:37:06 +00:00
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
2012-07-17 09:27:55 +00:00
|
|
|
[ C(RESULT_ACCESS) ] = 0x01b7,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x01b7,
|
2011-04-22 21:37:06 +00:00
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
2012-07-17 09:27:55 +00:00
|
|
|
[ C(RESULT_ACCESS) ] = 0x01b7,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x01b7,
|
2011-04-22 21:37:06 +00:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
|
2011-03-02 13:27:04 +00:00
|
|
|
};
|
|
|
|
|
|
2015-02-18 02:18:04 +00:00
|
|
|
/*
|
|
|
|
|
* Notes on the events:
|
|
|
|
|
* - data reads do not include code reads (comparable to earlier tables)
|
|
|
|
|
* - data counts include speculative execution (except L1 write, dtlb, bpu)
|
|
|
|
|
* - remote node access includes remote memory, remote cache, remote mmio.
|
|
|
|
|
* - prefetches are not included in the counts because they are not
|
|
|
|
|
* reliably counted.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define HSW_DEMAND_DATA_RD BIT_ULL(0)
|
|
|
|
|
#define HSW_DEMAND_RFO BIT_ULL(1)
|
|
|
|
|
#define HSW_ANY_RESPONSE BIT_ULL(16)
|
|
|
|
|
#define HSW_SUPPLIER_NONE BIT_ULL(17)
|
|
|
|
|
#define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
|
|
|
|
|
#define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
|
|
|
|
|
#define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
|
|
|
|
|
#define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
|
|
|
|
|
#define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
|
|
|
|
|
HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
|
|
|
|
|
HSW_L3_MISS_REMOTE_HOP2P)
|
|
|
|
|
#define HSW_SNOOP_NONE BIT_ULL(31)
|
|
|
|
|
#define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
|
|
|
|
|
#define HSW_SNOOP_MISS BIT_ULL(33)
|
|
|
|
|
#define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
|
|
|
|
|
#define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
|
|
|
|
|
#define HSW_SNOOP_HITM BIT_ULL(36)
|
|
|
|
|
#define HSW_SNOOP_NON_DRAM BIT_ULL(37)
|
|
|
|
|
#define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
|
|
|
|
|
HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
|
|
|
|
|
HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
|
|
|
|
|
HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
|
|
|
|
|
#define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
|
|
|
|
|
#define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
|
|
|
|
|
#define HSW_DEMAND_WRITE HSW_DEMAND_RFO
|
|
|
|
|
#define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
|
|
|
|
|
HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
|
|
|
|
|
#define HSW_LLC_ACCESS HSW_ANY_RESPONSE
|
|
|
|
|
|
2015-02-18 02:18:05 +00:00
|
|
|
#define BDW_L3_MISS_LOCAL BIT(26)
|
|
|
|
|
#define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
|
|
|
|
|
HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
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HSW_L3_MISS_REMOTE_HOP2P)
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2015-02-18 02:18:04 +00:00
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static __initconst const u64 hsw_hw_cache_event_ids
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] =
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{
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[ C(L1D ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
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[ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
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[ C(RESULT_MISS) ] = 0x0,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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[ C(L1I ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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[ C(LL ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
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[ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
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[ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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[ C(DTLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
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[ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
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[ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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[ C(ITLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
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[ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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[ C(BPU ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
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[ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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[ C(NODE) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
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[ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
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[ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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};
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static __initconst const u64 hsw_hw_cache_extra_regs
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] =
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{
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[ C(LL ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
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HSW_LLC_ACCESS,
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[ C(RESULT_MISS) ] = HSW_DEMAND_READ|
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HSW_L3_MISS|HSW_ANY_SNOOP,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
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HSW_LLC_ACCESS,
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[ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
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HSW_L3_MISS|HSW_ANY_SNOOP,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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[ C(NODE) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
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HSW_L3_MISS_LOCAL_DRAM|
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HSW_SNOOP_DRAM,
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[ C(RESULT_MISS) ] = HSW_DEMAND_READ|
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HSW_L3_MISS_REMOTE|
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HSW_SNOOP_DRAM,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
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HSW_L3_MISS_LOCAL_DRAM|
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HSW_SNOOP_DRAM,
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[ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
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HSW_L3_MISS_REMOTE|
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HSW_SNOOP_DRAM,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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};
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2010-03-29 11:09:53 +00:00
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static __initconst const u64 westmere_hw_cache_event_ids
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2010-02-26 11:05:05 +00:00
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] =
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{
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[ C(L1D) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
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[ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
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[ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
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[ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
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},
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},
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[ C(L1I ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
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[ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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[ C(LL ) ] = {
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[ C(OP_READ) ] = {
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2011-04-22 22:57:42 +00:00
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/* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
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2011-03-03 02:34:48 +00:00
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[ C(RESULT_ACCESS) ] = 0x01b7,
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2011-04-22 22:57:42 +00:00
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/* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
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[ C(RESULT_MISS) ] = 0x01b7,
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2010-02-26 11:05:05 +00:00
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},
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2011-03-03 02:34:48 +00:00
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/*
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* Use RFO, not WRITEBACK, because a write miss would typically occur
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* on RFO.
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*/
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2010-02-26 11:05:05 +00:00
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[ C(OP_WRITE) ] = {
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2011-04-22 22:57:42 +00:00
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/* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
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[ C(RESULT_ACCESS) ] = 0x01b7,
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/* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
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2011-03-03 02:34:48 +00:00
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[ C(RESULT_MISS) ] = 0x01b7,
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2010-02-26 11:05:05 +00:00
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},
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[ C(OP_PREFETCH) ] = {
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2011-04-22 22:57:42 +00:00
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/* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
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2011-03-03 02:34:48 +00:00
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[ C(RESULT_ACCESS) ] = 0x01b7,
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2011-04-22 22:57:42 +00:00
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/* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
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[ C(RESULT_MISS) ] = 0x01b7,
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2010-02-26 11:05:05 +00:00
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},
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},
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[ C(DTLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
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[ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
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[ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x0,
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[ C(RESULT_MISS) ] = 0x0,
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},
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},
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[ C(ITLB) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
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[ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
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[ C(BPU ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
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[ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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},
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},
|
2011-04-22 21:37:06 +00:00
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[ C(NODE) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = 0x01b7,
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[ C(RESULT_MISS) ] = 0x01b7,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = 0x01b7,
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[ C(RESULT_MISS) ] = 0x01b7,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = 0x01b7,
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[ C(RESULT_MISS) ] = 0x01b7,
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},
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},
|
2010-02-26 11:05:05 +00:00
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};
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|
2011-03-03 02:34:48 +00:00
|
|
|
/*
|
2011-04-22 22:57:42 +00:00
|
|
|
* Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
|
|
|
|
|
* See IA32 SDM Vol 3B 30.6.1.3
|
2011-03-03 02:34:48 +00:00
|
|
|
*/
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|
2011-04-22 22:57:42 +00:00
|
|
|
#define NHM_DMND_DATA_RD (1 << 0)
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|
|
#define NHM_DMND_RFO (1 << 1)
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|
|
#define NHM_DMND_IFETCH (1 << 2)
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|
|
#define NHM_DMND_WB (1 << 3)
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|
|
#define NHM_PF_DATA_RD (1 << 4)
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|
|
#define NHM_PF_DATA_RFO (1 << 5)
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|
|
#define NHM_PF_IFETCH (1 << 6)
|
|
|
|
|
#define NHM_OFFCORE_OTHER (1 << 7)
|
|
|
|
|
#define NHM_UNCORE_HIT (1 << 8)
|
|
|
|
|
#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
|
|
|
|
|
#define NHM_OTHER_CORE_HITM (1 << 10)
|
|
|
|
|
/* reserved */
|
|
|
|
|
#define NHM_REMOTE_CACHE_FWD (1 << 12)
|
|
|
|
|
#define NHM_REMOTE_DRAM (1 << 13)
|
|
|
|
|
#define NHM_LOCAL_DRAM (1 << 14)
|
|
|
|
|
#define NHM_NON_DRAM (1 << 15)
|
|
|
|
|
|
perf/x86: Fix local vs remote memory events for NHM/WSM
Verified using the below proglet.. before:
[root@westmere ~]# perf stat -e node-stores -e node-store-misses ./numa 0
remote write
Performance counter stats for './numa 0':
2,101,554 node-stores
2,096,931 node-store-misses
5.021546079 seconds time elapsed
[root@westmere ~]# perf stat -e node-stores -e node-store-misses ./numa 1
local write
Performance counter stats for './numa 1':
501,137 node-stores
199 node-store-misses
5.124451068 seconds time elapsed
After:
[root@westmere ~]# perf stat -e node-stores -e node-store-misses ./numa 0
remote write
Performance counter stats for './numa 0':
2,107,516 node-stores
2,097,187 node-store-misses
5.012755149 seconds time elapsed
[root@westmere ~]# perf stat -e node-stores -e node-store-misses ./numa 1
local write
Performance counter stats for './numa 1':
2,063,355 node-stores
165 node-store-misses
5.082091494 seconds time elapsed
#define _GNU_SOURCE
#include <sched.h>
#include <stdio.h>
#include <errno.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <dirent.h>
#include <signal.h>
#include <unistd.h>
#include <numaif.h>
#include <stdlib.h>
#define SIZE (32*1024*1024)
volatile int done;
void sig_done(int sig)
{
done = 1;
}
int main(int argc, char **argv)
{
cpu_set_t *mask, *mask2;
size_t size;
int i, err, t;
int nrcpus = 1024;
char *mem;
unsigned long nodemask = 0x01; /* node 0 */
DIR *node;
struct dirent *de;
int read = 0;
int local = 0;
if (argc < 2) {
printf("usage: %s [0-3]\n", argv[0]);
printf(" bit0 - local/remote\n");
printf(" bit1 - read/write\n");
exit(0);
}
switch (atoi(argv[1])) {
case 0:
printf("remote write\n");
break;
case 1:
printf("local write\n");
local = 1;
break;
case 2:
printf("remote read\n");
read = 1;
break;
case 3:
printf("local read\n");
local = 1;
read = 1;
break;
}
mask = CPU_ALLOC(nrcpus);
size = CPU_ALLOC_SIZE(nrcpus);
CPU_ZERO_S(size, mask);
node = opendir("/sys/devices/system/node/node0/");
if (!node)
perror("opendir");
while ((de = readdir(node))) {
int cpu;
if (sscanf(de->d_name, "cpu%d", &cpu) == 1)
CPU_SET_S(cpu, size, mask);
}
closedir(node);
mask2 = CPU_ALLOC(nrcpus);
CPU_ZERO_S(size, mask2);
for (i = 0; i < size; i++)
CPU_SET_S(i, size, mask2);
CPU_XOR_S(size, mask2, mask2, mask); // invert
if (!local)
mask = mask2;
err = sched_setaffinity(0, size, mask);
if (err)
perror("sched_setaffinity");
mem = mmap(0, SIZE, PROT_READ|PROT_WRITE,
MAP_PRIVATE|MAP_ANONYMOUS, -1, 0);
err = mbind(mem, SIZE, MPOL_BIND, &nodemask, 8*sizeof(nodemask), MPOL_MF_MOVE);
if (err)
perror("mbind");
signal(SIGALRM, sig_done);
alarm(5);
if (!read) {
while (!done) {
for (i = 0; i < SIZE; i++)
mem[i] = 0x01;
}
} else {
while (!done) {
for (i = 0; i < SIZE; i++)
t += *(volatile char *)(mem + i);
}
}
return 0;
}
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Stephane Eranian <eranian@google.com>
Cc: <stable@kernel.org>
Link: http://lkml.kernel.org/n/tip-tq73sxus35xmqpojf7ootxgs@git.kernel.org
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2012-03-05 22:59:25 +00:00
|
|
|
#define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
|
|
|
|
|
#define NHM_REMOTE (NHM_REMOTE_DRAM)
|
2011-04-22 22:57:42 +00:00
|
|
|
|
|
|
|
|
#define NHM_DMND_READ (NHM_DMND_DATA_RD)
|
|
|
|
|
#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
|
|
|
|
|
#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
|
|
|
|
|
|
|
|
|
|
#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
|
perf/x86: Fix local vs remote memory events for NHM/WSM
Verified using the below proglet.. before:
[root@westmere ~]# perf stat -e node-stores -e node-store-misses ./numa 0
remote write
Performance counter stats for './numa 0':
2,101,554 node-stores
2,096,931 node-store-misses
5.021546079 seconds time elapsed
[root@westmere ~]# perf stat -e node-stores -e node-store-misses ./numa 1
local write
Performance counter stats for './numa 1':
501,137 node-stores
199 node-store-misses
5.124451068 seconds time elapsed
After:
[root@westmere ~]# perf stat -e node-stores -e node-store-misses ./numa 0
remote write
Performance counter stats for './numa 0':
2,107,516 node-stores
2,097,187 node-store-misses
5.012755149 seconds time elapsed
[root@westmere ~]# perf stat -e node-stores -e node-store-misses ./numa 1
local write
Performance counter stats for './numa 1':
2,063,355 node-stores
165 node-store-misses
5.082091494 seconds time elapsed
#define _GNU_SOURCE
#include <sched.h>
#include <stdio.h>
#include <errno.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <dirent.h>
#include <signal.h>
#include <unistd.h>
#include <numaif.h>
#include <stdlib.h>
#define SIZE (32*1024*1024)
volatile int done;
void sig_done(int sig)
{
done = 1;
}
int main(int argc, char **argv)
{
cpu_set_t *mask, *mask2;
size_t size;
int i, err, t;
int nrcpus = 1024;
char *mem;
unsigned long nodemask = 0x01; /* node 0 */
DIR *node;
struct dirent *de;
int read = 0;
int local = 0;
if (argc < 2) {
printf("usage: %s [0-3]\n", argv[0]);
printf(" bit0 - local/remote\n");
printf(" bit1 - read/write\n");
exit(0);
}
switch (atoi(argv[1])) {
case 0:
printf("remote write\n");
break;
case 1:
printf("local write\n");
local = 1;
break;
case 2:
printf("remote read\n");
read = 1;
break;
case 3:
printf("local read\n");
local = 1;
read = 1;
break;
}
mask = CPU_ALLOC(nrcpus);
size = CPU_ALLOC_SIZE(nrcpus);
CPU_ZERO_S(size, mask);
node = opendir("/sys/devices/system/node/node0/");
if (!node)
perror("opendir");
while ((de = readdir(node))) {
int cpu;
if (sscanf(de->d_name, "cpu%d", &cpu) == 1)
CPU_SET_S(cpu, size, mask);
}
closedir(node);
mask2 = CPU_ALLOC(nrcpus);
CPU_ZERO_S(size, mask2);
for (i = 0; i < size; i++)
CPU_SET_S(i, size, mask2);
CPU_XOR_S(size, mask2, mask2, mask); // invert
if (!local)
mask = mask2;
err = sched_setaffinity(0, size, mask);
if (err)
perror("sched_setaffinity");
mem = mmap(0, SIZE, PROT_READ|PROT_WRITE,
MAP_PRIVATE|MAP_ANONYMOUS, -1, 0);
err = mbind(mem, SIZE, MPOL_BIND, &nodemask, 8*sizeof(nodemask), MPOL_MF_MOVE);
if (err)
perror("mbind");
signal(SIGALRM, sig_done);
alarm(5);
if (!read) {
while (!done) {
for (i = 0; i < SIZE; i++)
mem[i] = 0x01;
}
} else {
while (!done) {
for (i = 0; i < SIZE; i++)
t += *(volatile char *)(mem + i);
}
}
return 0;
}
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Stephane Eranian <eranian@google.com>
Cc: <stable@kernel.org>
Link: http://lkml.kernel.org/n/tip-tq73sxus35xmqpojf7ootxgs@git.kernel.org
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2012-03-05 22:59:25 +00:00
|
|
|
#define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
|
2011-04-22 22:57:42 +00:00
|
|
|
#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
|
2011-03-03 02:34:48 +00:00
|
|
|
|
|
|
|
|
static __initconst const u64 nehalem_hw_cache_extra_regs
|
|
|
|
|
[PERF_COUNT_HW_CACHE_MAX]
|
|
|
|
|
[PERF_COUNT_HW_CACHE_OP_MAX]
|
|
|
|
|
[PERF_COUNT_HW_CACHE_RESULT_MAX] =
|
|
|
|
|
{
|
|
|
|
|
[ C(LL ) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
2011-04-22 22:57:42 +00:00
|
|
|
[ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
|
|
|
|
|
[ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
|
2011-03-03 02:34:48 +00:00
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
2011-04-22 22:57:42 +00:00
|
|
|
[ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
|
|
|
|
|
[ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
|
2011-03-03 02:34:48 +00:00
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
2011-04-22 22:57:42 +00:00
|
|
|
[ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
|
|
|
|
|
[ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
|
2011-03-03 02:34:48 +00:00
|
|
|
},
|
2011-04-22 21:37:06 +00:00
|
|
|
},
|
|
|
|
|
[ C(NODE) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
perf/x86: Fix local vs remote memory events for NHM/WSM
Verified using the below proglet.. before:
[root@westmere ~]# perf stat -e node-stores -e node-store-misses ./numa 0
remote write
Performance counter stats for './numa 0':
2,101,554 node-stores
2,096,931 node-store-misses
5.021546079 seconds time elapsed
[root@westmere ~]# perf stat -e node-stores -e node-store-misses ./numa 1
local write
Performance counter stats for './numa 1':
501,137 node-stores
199 node-store-misses
5.124451068 seconds time elapsed
After:
[root@westmere ~]# perf stat -e node-stores -e node-store-misses ./numa 0
remote write
Performance counter stats for './numa 0':
2,107,516 node-stores
2,097,187 node-store-misses
5.012755149 seconds time elapsed
[root@westmere ~]# perf stat -e node-stores -e node-store-misses ./numa 1
local write
Performance counter stats for './numa 1':
2,063,355 node-stores
165 node-store-misses
5.082091494 seconds time elapsed
#define _GNU_SOURCE
#include <sched.h>
#include <stdio.h>
#include <errno.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <dirent.h>
#include <signal.h>
#include <unistd.h>
#include <numaif.h>
#include <stdlib.h>
#define SIZE (32*1024*1024)
volatile int done;
void sig_done(int sig)
{
done = 1;
}
int main(int argc, char **argv)
{
cpu_set_t *mask, *mask2;
size_t size;
int i, err, t;
int nrcpus = 1024;
char *mem;
unsigned long nodemask = 0x01; /* node 0 */
DIR *node;
struct dirent *de;
int read = 0;
int local = 0;
if (argc < 2) {
printf("usage: %s [0-3]\n", argv[0]);
printf(" bit0 - local/remote\n");
printf(" bit1 - read/write\n");
exit(0);
}
switch (atoi(argv[1])) {
case 0:
printf("remote write\n");
break;
case 1:
printf("local write\n");
local = 1;
break;
case 2:
printf("remote read\n");
read = 1;
break;
case 3:
printf("local read\n");
local = 1;
read = 1;
break;
}
mask = CPU_ALLOC(nrcpus);
size = CPU_ALLOC_SIZE(nrcpus);
CPU_ZERO_S(size, mask);
node = opendir("/sys/devices/system/node/node0/");
if (!node)
perror("opendir");
while ((de = readdir(node))) {
int cpu;
if (sscanf(de->d_name, "cpu%d", &cpu) == 1)
CPU_SET_S(cpu, size, mask);
}
closedir(node);
mask2 = CPU_ALLOC(nrcpus);
CPU_ZERO_S(size, mask2);
for (i = 0; i < size; i++)
CPU_SET_S(i, size, mask2);
CPU_XOR_S(size, mask2, mask2, mask); // invert
if (!local)
mask = mask2;
err = sched_setaffinity(0, size, mask);
if (err)
perror("sched_setaffinity");
mem = mmap(0, SIZE, PROT_READ|PROT_WRITE,
MAP_PRIVATE|MAP_ANONYMOUS, -1, 0);
err = mbind(mem, SIZE, MPOL_BIND, &nodemask, 8*sizeof(nodemask), MPOL_MF_MOVE);
if (err)
perror("mbind");
signal(SIGALRM, sig_done);
alarm(5);
if (!read) {
while (!done) {
for (i = 0; i < SIZE; i++)
mem[i] = 0x01;
}
} else {
while (!done) {
for (i = 0; i < SIZE; i++)
t += *(volatile char *)(mem + i);
}
}
return 0;
}
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Stephane Eranian <eranian@google.com>
Cc: <stable@kernel.org>
Link: http://lkml.kernel.org/n/tip-tq73sxus35xmqpojf7ootxgs@git.kernel.org
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2012-03-05 22:59:25 +00:00
|
|
|
[ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
|
|
|
|
|
[ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
|
2011-04-22 21:37:06 +00:00
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
perf/x86: Fix local vs remote memory events for NHM/WSM
Verified using the below proglet.. before:
[root@westmere ~]# perf stat -e node-stores -e node-store-misses ./numa 0
remote write
Performance counter stats for './numa 0':
2,101,554 node-stores
2,096,931 node-store-misses
5.021546079 seconds time elapsed
[root@westmere ~]# perf stat -e node-stores -e node-store-misses ./numa 1
local write
Performance counter stats for './numa 1':
501,137 node-stores
199 node-store-misses
5.124451068 seconds time elapsed
After:
[root@westmere ~]# perf stat -e node-stores -e node-store-misses ./numa 0
remote write
Performance counter stats for './numa 0':
2,107,516 node-stores
2,097,187 node-store-misses
5.012755149 seconds time elapsed
[root@westmere ~]# perf stat -e node-stores -e node-store-misses ./numa 1
local write
Performance counter stats for './numa 1':
2,063,355 node-stores
165 node-store-misses
5.082091494 seconds time elapsed
#define _GNU_SOURCE
#include <sched.h>
#include <stdio.h>
#include <errno.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <dirent.h>
#include <signal.h>
#include <unistd.h>
#include <numaif.h>
#include <stdlib.h>
#define SIZE (32*1024*1024)
volatile int done;
void sig_done(int sig)
{
done = 1;
}
int main(int argc, char **argv)
{
cpu_set_t *mask, *mask2;
size_t size;
int i, err, t;
int nrcpus = 1024;
char *mem;
unsigned long nodemask = 0x01; /* node 0 */
DIR *node;
struct dirent *de;
int read = 0;
int local = 0;
if (argc < 2) {
printf("usage: %s [0-3]\n", argv[0]);
printf(" bit0 - local/remote\n");
printf(" bit1 - read/write\n");
exit(0);
}
switch (atoi(argv[1])) {
case 0:
printf("remote write\n");
break;
case 1:
printf("local write\n");
local = 1;
break;
case 2:
printf("remote read\n");
read = 1;
break;
case 3:
printf("local read\n");
local = 1;
read = 1;
break;
}
mask = CPU_ALLOC(nrcpus);
size = CPU_ALLOC_SIZE(nrcpus);
CPU_ZERO_S(size, mask);
node = opendir("/sys/devices/system/node/node0/");
if (!node)
perror("opendir");
while ((de = readdir(node))) {
int cpu;
if (sscanf(de->d_name, "cpu%d", &cpu) == 1)
CPU_SET_S(cpu, size, mask);
}
closedir(node);
mask2 = CPU_ALLOC(nrcpus);
CPU_ZERO_S(size, mask2);
for (i = 0; i < size; i++)
CPU_SET_S(i, size, mask2);
CPU_XOR_S(size, mask2, mask2, mask); // invert
if (!local)
mask = mask2;
err = sched_setaffinity(0, size, mask);
if (err)
perror("sched_setaffinity");
mem = mmap(0, SIZE, PROT_READ|PROT_WRITE,
MAP_PRIVATE|MAP_ANONYMOUS, -1, 0);
err = mbind(mem, SIZE, MPOL_BIND, &nodemask, 8*sizeof(nodemask), MPOL_MF_MOVE);
if (err)
perror("mbind");
signal(SIGALRM, sig_done);
alarm(5);
if (!read) {
while (!done) {
for (i = 0; i < SIZE; i++)
mem[i] = 0x01;
}
} else {
while (!done) {
for (i = 0; i < SIZE; i++)
t += *(volatile char *)(mem + i);
}
}
return 0;
}
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Stephane Eranian <eranian@google.com>
Cc: <stable@kernel.org>
Link: http://lkml.kernel.org/n/tip-tq73sxus35xmqpojf7ootxgs@git.kernel.org
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2012-03-05 22:59:25 +00:00
|
|
|
[ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
|
|
|
|
|
[ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
|
2011-04-22 21:37:06 +00:00
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
perf/x86: Fix local vs remote memory events for NHM/WSM
Verified using the below proglet.. before:
[root@westmere ~]# perf stat -e node-stores -e node-store-misses ./numa 0
remote write
Performance counter stats for './numa 0':
2,101,554 node-stores
2,096,931 node-store-misses
5.021546079 seconds time elapsed
[root@westmere ~]# perf stat -e node-stores -e node-store-misses ./numa 1
local write
Performance counter stats for './numa 1':
501,137 node-stores
199 node-store-misses
5.124451068 seconds time elapsed
After:
[root@westmere ~]# perf stat -e node-stores -e node-store-misses ./numa 0
remote write
Performance counter stats for './numa 0':
2,107,516 node-stores
2,097,187 node-store-misses
5.012755149 seconds time elapsed
[root@westmere ~]# perf stat -e node-stores -e node-store-misses ./numa 1
local write
Performance counter stats for './numa 1':
2,063,355 node-stores
165 node-store-misses
5.082091494 seconds time elapsed
#define _GNU_SOURCE
#include <sched.h>
#include <stdio.h>
#include <errno.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <dirent.h>
#include <signal.h>
#include <unistd.h>
#include <numaif.h>
#include <stdlib.h>
#define SIZE (32*1024*1024)
volatile int done;
void sig_done(int sig)
{
done = 1;
}
int main(int argc, char **argv)
{
cpu_set_t *mask, *mask2;
size_t size;
int i, err, t;
int nrcpus = 1024;
char *mem;
unsigned long nodemask = 0x01; /* node 0 */
DIR *node;
struct dirent *de;
int read = 0;
int local = 0;
if (argc < 2) {
printf("usage: %s [0-3]\n", argv[0]);
printf(" bit0 - local/remote\n");
printf(" bit1 - read/write\n");
exit(0);
}
switch (atoi(argv[1])) {
case 0:
printf("remote write\n");
break;
case 1:
printf("local write\n");
local = 1;
break;
case 2:
printf("remote read\n");
read = 1;
break;
case 3:
printf("local read\n");
local = 1;
read = 1;
break;
}
mask = CPU_ALLOC(nrcpus);
size = CPU_ALLOC_SIZE(nrcpus);
CPU_ZERO_S(size, mask);
node = opendir("/sys/devices/system/node/node0/");
if (!node)
perror("opendir");
while ((de = readdir(node))) {
int cpu;
if (sscanf(de->d_name, "cpu%d", &cpu) == 1)
CPU_SET_S(cpu, size, mask);
}
closedir(node);
mask2 = CPU_ALLOC(nrcpus);
CPU_ZERO_S(size, mask2);
for (i = 0; i < size; i++)
CPU_SET_S(i, size, mask2);
CPU_XOR_S(size, mask2, mask2, mask); // invert
if (!local)
mask = mask2;
err = sched_setaffinity(0, size, mask);
if (err)
perror("sched_setaffinity");
mem = mmap(0, SIZE, PROT_READ|PROT_WRITE,
MAP_PRIVATE|MAP_ANONYMOUS, -1, 0);
err = mbind(mem, SIZE, MPOL_BIND, &nodemask, 8*sizeof(nodemask), MPOL_MF_MOVE);
if (err)
perror("mbind");
signal(SIGALRM, sig_done);
alarm(5);
if (!read) {
while (!done) {
for (i = 0; i < SIZE; i++)
mem[i] = 0x01;
}
} else {
while (!done) {
for (i = 0; i < SIZE; i++)
t += *(volatile char *)(mem + i);
}
}
return 0;
}
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Stephane Eranian <eranian@google.com>
Cc: <stable@kernel.org>
Link: http://lkml.kernel.org/n/tip-tq73sxus35xmqpojf7ootxgs@git.kernel.org
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2012-03-05 22:59:25 +00:00
|
|
|
[ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
|
|
|
|
|
[ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
|
2011-04-22 21:37:06 +00:00
|
|
|
},
|
|
|
|
|
},
|
2011-03-03 02:34:48 +00:00
|
|
|
};
|
|
|
|
|
|
2010-03-29 11:09:53 +00:00
|
|
|
static __initconst const u64 nehalem_hw_cache_event_ids
|
2010-02-26 11:05:05 +00:00
|
|
|
[PERF_COUNT_HW_CACHE_MAX]
|
|
|
|
|
[PERF_COUNT_HW_CACHE_OP_MAX]
|
|
|
|
|
[PERF_COUNT_HW_CACHE_RESULT_MAX] =
|
|
|
|
|
{
|
|
|
|
|
[ C(L1D) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
perf, x86: Update/fix Intel Nehalem cache events
Change the Nehalem cache events to use retired memory instruction counters
(similar to Westmere), this greatly improves the provided stats.
Using:
main ()
{
int i;
for (i = 0; i < 1000000000; i++) {
asm("mov (%%rsp), %%rbx;"
"mov %%rbx, (%%rsp);" : : : "rbx");
}
}
We find:
$ perf stat --repeat 10 -e instructions:u -e l1-dcache-loads:u -e l1-dcache-stores:u ./loop_1b_loads+stores
Performance counter stats for './loop_1b_loads+stores' (10 runs):
4,000,081,056 instructions:u # 0.000 IPC ( +- 0.000% )
4,999,502,846 l1-dcache-loads:u ( +- 0.008% )
1,000,034,832 l1-dcache-stores:u ( +- 0.000% )
1.565184942 seconds time elapsed ( +- 0.005% )
The 5b is surprising - we'd expect 1b:
$ perf stat --repeat 10 -e instructions:u -e r10b:u -e l1-dcache-stores:u ./loop_1b_loads+stores
Performance counter stats for './loop_1b_loads+stores' (10 runs):
4,000,081,054 instructions:u # 0.000 IPC ( +- 0.000% )
1,000,021,961 r10b:u ( +- 0.000% )
1,000,030,951 l1-dcache-stores:u ( +- 0.000% )
1.565055422 seconds time elapsed ( +- 0.003% )
Which this patch thus fixes.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Lin Ming <ming.m.lin@intel.com>
Cc: Cyrill Gorcunov <gorcunov@openvz.org>
Link: http://lkml.kernel.org/n/tip-q9rtru7b7840tws75xzboapv@git.kernel.org
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-04-22 11:39:56 +00:00
|
|
|
[ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
|
2010-02-26 11:05:05 +00:00
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
perf, x86: Update/fix Intel Nehalem cache events
Change the Nehalem cache events to use retired memory instruction counters
(similar to Westmere), this greatly improves the provided stats.
Using:
main ()
{
int i;
for (i = 0; i < 1000000000; i++) {
asm("mov (%%rsp), %%rbx;"
"mov %%rbx, (%%rsp);" : : : "rbx");
}
}
We find:
$ perf stat --repeat 10 -e instructions:u -e l1-dcache-loads:u -e l1-dcache-stores:u ./loop_1b_loads+stores
Performance counter stats for './loop_1b_loads+stores' (10 runs):
4,000,081,056 instructions:u # 0.000 IPC ( +- 0.000% )
4,999,502,846 l1-dcache-loads:u ( +- 0.008% )
1,000,034,832 l1-dcache-stores:u ( +- 0.000% )
1.565184942 seconds time elapsed ( +- 0.005% )
The 5b is surprising - we'd expect 1b:
$ perf stat --repeat 10 -e instructions:u -e r10b:u -e l1-dcache-stores:u ./loop_1b_loads+stores
Performance counter stats for './loop_1b_loads+stores' (10 runs):
4,000,081,054 instructions:u # 0.000 IPC ( +- 0.000% )
1,000,021,961 r10b:u ( +- 0.000% )
1,000,030,951 l1-dcache-stores:u ( +- 0.000% )
1.565055422 seconds time elapsed ( +- 0.003% )
Which this patch thus fixes.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Lin Ming <ming.m.lin@intel.com>
Cc: Cyrill Gorcunov <gorcunov@openvz.org>
Link: http://lkml.kernel.org/n/tip-q9rtru7b7840tws75xzboapv@git.kernel.org
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-04-22 11:39:56 +00:00
|
|
|
[ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
|
2010-02-26 11:05:05 +00:00
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(L1I ) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x0,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(LL ) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
2011-03-03 02:34:48 +00:00
|
|
|
/* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x01b7,
|
|
|
|
|
/* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x01b7,
|
2010-02-26 11:05:05 +00:00
|
|
|
},
|
2011-03-03 02:34:48 +00:00
|
|
|
/*
|
|
|
|
|
* Use RFO, not WRITEBACK, because a write miss would typically occur
|
|
|
|
|
* on RFO.
|
|
|
|
|
*/
|
2010-02-26 11:05:05 +00:00
|
|
|
[ C(OP_WRITE) ] = {
|
2011-03-03 02:34:48 +00:00
|
|
|
/* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x01b7,
|
|
|
|
|
/* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x01b7,
|
2010-02-26 11:05:05 +00:00
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
2011-03-03 02:34:48 +00:00
|
|
|
/* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x01b7,
|
|
|
|
|
/* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x01b7,
|
2010-02-26 11:05:05 +00:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(DTLB) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x0,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(ITLB) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(BPU ) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
},
|
2011-04-22 21:37:06 +00:00
|
|
|
[ C(NODE) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x01b7,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x01b7,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x01b7,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x01b7,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x01b7,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x01b7,
|
|
|
|
|
},
|
|
|
|
|
},
|
2010-02-26 11:05:05 +00:00
|
|
|
};
|
|
|
|
|
|
2010-03-29 11:09:53 +00:00
|
|
|
static __initconst const u64 core2_hw_cache_event_ids
|
2010-02-26 11:05:05 +00:00
|
|
|
[PERF_COUNT_HW_CACHE_MAX]
|
|
|
|
|
[PERF_COUNT_HW_CACHE_OP_MAX]
|
|
|
|
|
[PERF_COUNT_HW_CACHE_RESULT_MAX] =
|
|
|
|
|
{
|
|
|
|
|
[ C(L1D) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(L1I ) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(LL ) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(DTLB) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(ITLB) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(BPU ) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
};
|
|
|
|
|
|
2010-03-29 11:09:53 +00:00
|
|
|
static __initconst const u64 atom_hw_cache_event_ids
|
2010-02-26 11:05:05 +00:00
|
|
|
[PERF_COUNT_HW_CACHE_MAX]
|
|
|
|
|
[PERF_COUNT_HW_CACHE_OP_MAX]
|
|
|
|
|
[PERF_COUNT_HW_CACHE_RESULT_MAX] =
|
|
|
|
|
{
|
|
|
|
|
[ C(L1D) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x0,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(L1I ) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(LL ) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(DTLB) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(ITLB) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(BPU ) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
};
|
|
|
|
|
|
2013-07-18 09:02:24 +00:00
|
|
|
static struct extra_reg intel_slm_extra_regs[] __read_mostly =
|
|
|
|
|
{
|
|
|
|
|
/* must define OFFCORE_RSP_X first, see intel_fixup_er() */
|
perf/x86/intel: Fix Silvermont offcore masks
Fengguang Wu reported:
> sparse warnings: (new ones prefixed by >>)
>
> >> arch/x86/kernel/cpu/perf_event_intel.c:901:9: sparse: constant 0x768005ffff is so big it is long
> >> arch/x86/kernel/cpu/perf_event_intel.c:902:9: sparse: constant 0x768005ffff is so big it is long
>
> vim +901 arch/x86/kernel/cpu/perf_event_intel.c
>
> 895 },
> 896 };
> 897
> 898 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
> 899 {
> 900 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
> > 901 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffff, RSP_0),
> > 902 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x768005ffff, RSP_1),
> 903 EVENT_EXTRA_END
> 904 };
> 905
Extend those constants to 64 bits.
Reported-by: fengguang.wu@intel.com
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/20130909112636.GQ31370@twins.programming.kicks-ass.net
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2013-09-09 11:26:36 +00:00
|
|
|
INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
|
|
|
|
|
INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x768005ffffull, RSP_1),
|
2013-07-18 09:02:24 +00:00
|
|
|
EVENT_EXTRA_END
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#define SLM_DMND_READ SNB_DMND_DATA_RD
|
|
|
|
|
#define SLM_DMND_WRITE SNB_DMND_RFO
|
|
|
|
|
#define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
|
|
|
|
|
|
|
|
|
|
#define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
|
|
|
|
|
#define SLM_LLC_ACCESS SNB_RESP_ANY
|
|
|
|
|
#define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
|
|
|
|
|
|
|
|
|
|
static __initconst const u64 slm_hw_cache_extra_regs
|
|
|
|
|
[PERF_COUNT_HW_CACHE_MAX]
|
|
|
|
|
[PERF_COUNT_HW_CACHE_OP_MAX]
|
|
|
|
|
[PERF_COUNT_HW_CACHE_RESULT_MAX] =
|
|
|
|
|
{
|
|
|
|
|
[ C(LL ) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
|
|
|
|
|
[ C(RESULT_MISS) ] = SLM_DMND_READ|SLM_LLC_MISS,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
|
|
|
|
|
[ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
|
|
|
|
|
[ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static __initconst const u64 slm_hw_cache_event_ids
|
|
|
|
|
[PERF_COUNT_HW_CACHE_MAX]
|
|
|
|
|
[PERF_COUNT_HW_CACHE_OP_MAX]
|
|
|
|
|
[PERF_COUNT_HW_CACHE_RESULT_MAX] =
|
|
|
|
|
{
|
|
|
|
|
[ C(L1D) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(L1I ) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(LL ) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
/* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x01b7,
|
|
|
|
|
/* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x01b7,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
/* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x01b7,
|
|
|
|
|
/* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x01b7,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
/* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x01b7,
|
|
|
|
|
/* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x01b7,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(DTLB) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(ITLB) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(BPU ) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
|
|
|
|
|
[ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
};
|
|
|
|
|
|
2010-02-26 11:05:05 +00:00
|
|
|
static void intel_pmu_disable_all(void)
|
|
|
|
|
{
|
x86: Replace __get_cpu_var uses
__get_cpu_var() is used for multiple purposes in the kernel source. One of
them is address calculation via the form &__get_cpu_var(x). This calculates
the address for the instance of the percpu variable of the current processor
based on an offset.
Other use cases are for storing and retrieving data from the current
processors percpu area. __get_cpu_var() can be used as an lvalue when
writing data or on the right side of an assignment.
__get_cpu_var() is defined as :
#define __get_cpu_var(var) (*this_cpu_ptr(&(var)))
__get_cpu_var() always only does an address determination. However, store
and retrieve operations could use a segment prefix (or global register on
other platforms) to avoid the address calculation.
this_cpu_write() and this_cpu_read() can directly take an offset into a
percpu area and use optimized assembly code to read and write per cpu
variables.
This patch converts __get_cpu_var into either an explicit address
calculation using this_cpu_ptr() or into a use of this_cpu operations that
use the offset. Thereby address calculations are avoided and less registers
are used when code is generated.
Transformations done to __get_cpu_var()
1. Determine the address of the percpu instance of the current processor.
DEFINE_PER_CPU(int, y);
int *x = &__get_cpu_var(y);
Converts to
int *x = this_cpu_ptr(&y);
2. Same as #1 but this time an array structure is involved.
DEFINE_PER_CPU(int, y[20]);
int *x = __get_cpu_var(y);
Converts to
int *x = this_cpu_ptr(y);
3. Retrieve the content of the current processors instance of a per cpu
variable.
DEFINE_PER_CPU(int, y);
int x = __get_cpu_var(y)
Converts to
int x = __this_cpu_read(y);
4. Retrieve the content of a percpu struct
DEFINE_PER_CPU(struct mystruct, y);
struct mystruct x = __get_cpu_var(y);
Converts to
memcpy(&x, this_cpu_ptr(&y), sizeof(x));
5. Assignment to a per cpu variable
DEFINE_PER_CPU(int, y)
__get_cpu_var(y) = x;
Converts to
__this_cpu_write(y, x);
6. Increment/Decrement etc of a per cpu variable
DEFINE_PER_CPU(int, y);
__get_cpu_var(y)++
Converts to
__this_cpu_inc(y)
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: x86@kernel.org
Acked-by: H. Peter Anvin <hpa@linux.intel.com>
Acked-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Christoph Lameter <cl@linux.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2014-08-17 17:30:40 +00:00
|
|
|
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
|
2010-02-26 11:05:05 +00:00
|
|
|
|
|
|
|
|
wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
|
|
|
|
|
|
2012-06-20 18:46:33 +00:00
|
|
|
if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
|
2010-02-26 11:05:05 +00:00
|
|
|
intel_pmu_disable_bts();
|
perf, x86: Add PEBS infrastructure
This patch implements support for Intel Precise Event Based Sampling,
which is an alternative counter mode in which the counter triggers a
hardware assist to collect information on events. The hardware assist
takes a trap like snapshot of a subset of the machine registers.
This data is written to the Intel Debug-Store, which can be programmed
with a data threshold at which to raise a PMI.
With the PEBS hardware assist being trap like, the reported IP is always
one instruction after the actual instruction that triggered the event.
This implements a simple PEBS model that always takes a single PEBS event
at a time. This is done so that the interaction with the rest of the
system is as expected (freq adjust, period randomization, lbr,
callchains, etc.).
It adds an ABI element: perf_event_attr::precise, which indicates that we
wish to use this (constrained, but precise) mode.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100304140100.392111285@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-02 18:52:12 +00:00
|
|
|
|
|
|
|
|
intel_pmu_pebs_disable_all();
|
2010-03-03 11:02:30 +00:00
|
|
|
intel_pmu_lbr_disable_all();
|
2010-02-26 11:05:05 +00:00
|
|
|
}
|
|
|
|
|
|
2010-03-26 13:08:44 +00:00
|
|
|
static void intel_pmu_enable_all(int added)
|
2010-02-26 11:05:05 +00:00
|
|
|
{
|
x86: Replace __get_cpu_var uses
__get_cpu_var() is used for multiple purposes in the kernel source. One of
them is address calculation via the form &__get_cpu_var(x). This calculates
the address for the instance of the percpu variable of the current processor
based on an offset.
Other use cases are for storing and retrieving data from the current
processors percpu area. __get_cpu_var() can be used as an lvalue when
writing data or on the right side of an assignment.
__get_cpu_var() is defined as :
#define __get_cpu_var(var) (*this_cpu_ptr(&(var)))
__get_cpu_var() always only does an address determination. However, store
and retrieve operations could use a segment prefix (or global register on
other platforms) to avoid the address calculation.
this_cpu_write() and this_cpu_read() can directly take an offset into a
percpu area and use optimized assembly code to read and write per cpu
variables.
This patch converts __get_cpu_var into either an explicit address
calculation using this_cpu_ptr() or into a use of this_cpu operations that
use the offset. Thereby address calculations are avoided and less registers
are used when code is generated.
Transformations done to __get_cpu_var()
1. Determine the address of the percpu instance of the current processor.
DEFINE_PER_CPU(int, y);
int *x = &__get_cpu_var(y);
Converts to
int *x = this_cpu_ptr(&y);
2. Same as #1 but this time an array structure is involved.
DEFINE_PER_CPU(int, y[20]);
int *x = __get_cpu_var(y);
Converts to
int *x = this_cpu_ptr(y);
3. Retrieve the content of the current processors instance of a per cpu
variable.
DEFINE_PER_CPU(int, y);
int x = __get_cpu_var(y)
Converts to
int x = __this_cpu_read(y);
4. Retrieve the content of a percpu struct
DEFINE_PER_CPU(struct mystruct, y);
struct mystruct x = __get_cpu_var(y);
Converts to
memcpy(&x, this_cpu_ptr(&y), sizeof(x));
5. Assignment to a per cpu variable
DEFINE_PER_CPU(int, y)
__get_cpu_var(y) = x;
Converts to
__this_cpu_write(y, x);
6. Increment/Decrement etc of a per cpu variable
DEFINE_PER_CPU(int, y);
__get_cpu_var(y)++
Converts to
__this_cpu_inc(y)
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: x86@kernel.org
Acked-by: H. Peter Anvin <hpa@linux.intel.com>
Acked-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Christoph Lameter <cl@linux.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2014-08-17 17:30:40 +00:00
|
|
|
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
|
2010-02-26 11:05:05 +00:00
|
|
|
|
2010-03-08 12:57:14 +00:00
|
|
|
intel_pmu_pebs_enable_all();
|
|
|
|
|
intel_pmu_lbr_enable_all();
|
2011-10-05 12:01:21 +00:00
|
|
|
wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
|
|
|
|
|
x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
|
2010-02-26 11:05:05 +00:00
|
|
|
|
2012-06-20 18:46:33 +00:00
|
|
|
if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
|
2010-02-26 11:05:05 +00:00
|
|
|
struct perf_event *event =
|
2012-06-20 18:46:33 +00:00
|
|
|
cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
|
2010-02-26 11:05:05 +00:00
|
|
|
|
|
|
|
|
if (WARN_ON_ONCE(!event))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
intel_pmu_enable_bts(event->hw.config);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2010-03-26 13:08:44 +00:00
|
|
|
/*
|
|
|
|
|
* Workaround for:
|
|
|
|
|
* Intel Errata AAK100 (model 26)
|
|
|
|
|
* Intel Errata AAP53 (model 30)
|
2010-03-29 14:37:17 +00:00
|
|
|
* Intel Errata BD53 (model 44)
|
2010-03-26 13:08:44 +00:00
|
|
|
*
|
2010-08-06 05:39:08 +00:00
|
|
|
* The official story:
|
|
|
|
|
* These chips need to be 'reset' when adding counters by programming the
|
|
|
|
|
* magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
|
|
|
|
|
* in sequence on the same PMC or on different PMCs.
|
|
|
|
|
*
|
|
|
|
|
* In practise it appears some of these events do in fact count, and
|
|
|
|
|
* we need to programm all 4 events.
|
2010-03-26 13:08:44 +00:00
|
|
|
*/
|
2010-08-06 05:39:08 +00:00
|
|
|
static void intel_pmu_nhm_workaround(void)
|
2010-03-26 13:08:44 +00:00
|
|
|
{
|
x86: Replace __get_cpu_var uses
__get_cpu_var() is used for multiple purposes in the kernel source. One of
them is address calculation via the form &__get_cpu_var(x). This calculates
the address for the instance of the percpu variable of the current processor
based on an offset.
Other use cases are for storing and retrieving data from the current
processors percpu area. __get_cpu_var() can be used as an lvalue when
writing data or on the right side of an assignment.
__get_cpu_var() is defined as :
#define __get_cpu_var(var) (*this_cpu_ptr(&(var)))
__get_cpu_var() always only does an address determination. However, store
and retrieve operations could use a segment prefix (or global register on
other platforms) to avoid the address calculation.
this_cpu_write() and this_cpu_read() can directly take an offset into a
percpu area and use optimized assembly code to read and write per cpu
variables.
This patch converts __get_cpu_var into either an explicit address
calculation using this_cpu_ptr() or into a use of this_cpu operations that
use the offset. Thereby address calculations are avoided and less registers
are used when code is generated.
Transformations done to __get_cpu_var()
1. Determine the address of the percpu instance of the current processor.
DEFINE_PER_CPU(int, y);
int *x = &__get_cpu_var(y);
Converts to
int *x = this_cpu_ptr(&y);
2. Same as #1 but this time an array structure is involved.
DEFINE_PER_CPU(int, y[20]);
int *x = __get_cpu_var(y);
Converts to
int *x = this_cpu_ptr(y);
3. Retrieve the content of the current processors instance of a per cpu
variable.
DEFINE_PER_CPU(int, y);
int x = __get_cpu_var(y)
Converts to
int x = __this_cpu_read(y);
4. Retrieve the content of a percpu struct
DEFINE_PER_CPU(struct mystruct, y);
struct mystruct x = __get_cpu_var(y);
Converts to
memcpy(&x, this_cpu_ptr(&y), sizeof(x));
5. Assignment to a per cpu variable
DEFINE_PER_CPU(int, y)
__get_cpu_var(y) = x;
Converts to
__this_cpu_write(y, x);
6. Increment/Decrement etc of a per cpu variable
DEFINE_PER_CPU(int, y);
__get_cpu_var(y)++
Converts to
__this_cpu_inc(y)
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: x86@kernel.org
Acked-by: H. Peter Anvin <hpa@linux.intel.com>
Acked-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Christoph Lameter <cl@linux.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2014-08-17 17:30:40 +00:00
|
|
|
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
|
2010-08-06 05:39:08 +00:00
|
|
|
static const unsigned long nhm_magic[4] = {
|
|
|
|
|
0x4300B5,
|
|
|
|
|
0x4300D2,
|
|
|
|
|
0x4300B1,
|
|
|
|
|
0x4300B1
|
|
|
|
|
};
|
|
|
|
|
struct perf_event *event;
|
|
|
|
|
int i;
|
2010-03-26 13:08:44 +00:00
|
|
|
|
2010-08-06 05:39:08 +00:00
|
|
|
/*
|
|
|
|
|
* The Errata requires below steps:
|
|
|
|
|
* 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
|
|
|
|
|
* 2) Configure 4 PERFEVTSELx with the magic events and clear
|
|
|
|
|
* the corresponding PMCx;
|
|
|
|
|
* 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
|
|
|
|
|
* 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
|
|
|
|
|
* 5) Clear 4 pairs of ERFEVTSELx and PMCx;
|
|
|
|
|
*/
|
2010-03-26 13:08:44 +00:00
|
|
|
|
2010-08-06 05:39:08 +00:00
|
|
|
/*
|
|
|
|
|
* The real steps we choose are a little different from above.
|
|
|
|
|
* A) To reduce MSR operations, we don't run step 1) as they
|
|
|
|
|
* are already cleared before this function is called;
|
|
|
|
|
* B) Call x86_perf_event_update to save PMCx before configuring
|
|
|
|
|
* PERFEVTSELx with magic number;
|
|
|
|
|
* C) With step 5), we do clear only when the PERFEVTSELx is
|
|
|
|
|
* not used currently.
|
|
|
|
|
* D) Call x86_perf_event_set_period to restore PMCx;
|
|
|
|
|
*/
|
2010-03-26 13:08:44 +00:00
|
|
|
|
2010-08-06 05:39:08 +00:00
|
|
|
/* We always operate 4 pairs of PERF Counters */
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
|
event = cpuc->events[i];
|
|
|
|
|
if (event)
|
|
|
|
|
x86_perf_event_update(event);
|
|
|
|
|
}
|
2010-03-26 13:08:44 +00:00
|
|
|
|
2010-08-06 05:39:08 +00:00
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
|
wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
|
|
|
|
|
wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
|
|
|
|
|
wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
|
2010-03-26 13:08:44 +00:00
|
|
|
|
2010-08-06 05:39:08 +00:00
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
|
event = cpuc->events[i];
|
|
|
|
|
|
|
|
|
|
if (event) {
|
|
|
|
|
x86_perf_event_set_period(event);
|
2010-04-13 20:23:14 +00:00
|
|
|
__x86_pmu_enable_event(&event->hw,
|
2010-08-06 05:39:08 +00:00
|
|
|
ARCH_PERFMON_EVENTSEL_ENABLE);
|
|
|
|
|
} else
|
|
|
|
|
wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
|
2010-03-26 13:08:44 +00:00
|
|
|
}
|
2010-08-06 05:39:08 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void intel_pmu_nhm_enable_all(int added)
|
|
|
|
|
{
|
|
|
|
|
if (added)
|
|
|
|
|
intel_pmu_nhm_workaround();
|
2010-03-26 13:08:44 +00:00
|
|
|
intel_pmu_enable_all(added);
|
|
|
|
|
}
|
|
|
|
|
|
2010-02-26 11:05:05 +00:00
|
|
|
static inline u64 intel_pmu_get_status(void)
|
|
|
|
|
{
|
|
|
|
|
u64 status;
|
|
|
|
|
|
|
|
|
|
rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
|
|
|
|
|
|
|
|
|
|
return status;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void intel_pmu_ack_status(u64 ack)
|
|
|
|
|
{
|
|
|
|
|
wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
|
|
|
|
|
}
|
|
|
|
|
|
perf, x86: Add PEBS infrastructure
This patch implements support for Intel Precise Event Based Sampling,
which is an alternative counter mode in which the counter triggers a
hardware assist to collect information on events. The hardware assist
takes a trap like snapshot of a subset of the machine registers.
This data is written to the Intel Debug-Store, which can be programmed
with a data threshold at which to raise a PMI.
With the PEBS hardware assist being trap like, the reported IP is always
one instruction after the actual instruction that triggered the event.
This implements a simple PEBS model that always takes a single PEBS event
at a time. This is done so that the interaction with the rest of the
system is as expected (freq adjust, period randomization, lbr,
callchains, etc.).
It adds an ABI element: perf_event_attr::precise, which indicates that we
wish to use this (constrained, but precise) mode.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100304140100.392111285@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-02 18:52:12 +00:00
|
|
|
static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
|
2010-02-26 11:05:05 +00:00
|
|
|
{
|
2012-06-20 18:46:33 +00:00
|
|
|
int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
|
2010-02-26 11:05:05 +00:00
|
|
|
u64 ctrl_val, mask;
|
|
|
|
|
|
|
|
|
|
mask = 0xfULL << (idx * 4);
|
|
|
|
|
|
|
|
|
|
rdmsrl(hwc->config_base, ctrl_val);
|
|
|
|
|
ctrl_val &= ~mask;
|
2010-03-08 12:51:31 +00:00
|
|
|
wrmsrl(hwc->config_base, ctrl_val);
|
2010-02-26 11:05:05 +00:00
|
|
|
}
|
|
|
|
|
|
2013-09-12 10:53:44 +00:00
|
|
|
static inline bool event_is_checkpointed(struct perf_event *event)
|
|
|
|
|
{
|
|
|
|
|
return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
|
|
|
|
|
}
|
|
|
|
|
|
perf, x86: Add PEBS infrastructure
This patch implements support for Intel Precise Event Based Sampling,
which is an alternative counter mode in which the counter triggers a
hardware assist to collect information on events. The hardware assist
takes a trap like snapshot of a subset of the machine registers.
This data is written to the Intel Debug-Store, which can be programmed
with a data threshold at which to raise a PMI.
With the PEBS hardware assist being trap like, the reported IP is always
one instruction after the actual instruction that triggered the event.
This implements a simple PEBS model that always takes a single PEBS event
at a time. This is done so that the interaction with the rest of the
system is as expected (freq adjust, period randomization, lbr,
callchains, etc.).
It adds an ABI element: perf_event_attr::precise, which indicates that we
wish to use this (constrained, but precise) mode.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100304140100.392111285@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-02 18:52:12 +00:00
|
|
|
static void intel_pmu_disable_event(struct perf_event *event)
|
2010-02-26 11:05:05 +00:00
|
|
|
{
|
2010-03-02 19:32:08 +00:00
|
|
|
struct hw_perf_event *hwc = &event->hw;
|
x86: Replace __get_cpu_var uses
__get_cpu_var() is used for multiple purposes in the kernel source. One of
them is address calculation via the form &__get_cpu_var(x). This calculates
the address for the instance of the percpu variable of the current processor
based on an offset.
Other use cases are for storing and retrieving data from the current
processors percpu area. __get_cpu_var() can be used as an lvalue when
writing data or on the right side of an assignment.
__get_cpu_var() is defined as :
#define __get_cpu_var(var) (*this_cpu_ptr(&(var)))
__get_cpu_var() always only does an address determination. However, store
and retrieve operations could use a segment prefix (or global register on
other platforms) to avoid the address calculation.
this_cpu_write() and this_cpu_read() can directly take an offset into a
percpu area and use optimized assembly code to read and write per cpu
variables.
This patch converts __get_cpu_var into either an explicit address
calculation using this_cpu_ptr() or into a use of this_cpu operations that
use the offset. Thereby address calculations are avoided and less registers
are used when code is generated.
Transformations done to __get_cpu_var()
1. Determine the address of the percpu instance of the current processor.
DEFINE_PER_CPU(int, y);
int *x = &__get_cpu_var(y);
Converts to
int *x = this_cpu_ptr(&y);
2. Same as #1 but this time an array structure is involved.
DEFINE_PER_CPU(int, y[20]);
int *x = __get_cpu_var(y);
Converts to
int *x = this_cpu_ptr(y);
3. Retrieve the content of the current processors instance of a per cpu
variable.
DEFINE_PER_CPU(int, y);
int x = __get_cpu_var(y)
Converts to
int x = __this_cpu_read(y);
4. Retrieve the content of a percpu struct
DEFINE_PER_CPU(struct mystruct, y);
struct mystruct x = __get_cpu_var(y);
Converts to
memcpy(&x, this_cpu_ptr(&y), sizeof(x));
5. Assignment to a per cpu variable
DEFINE_PER_CPU(int, y)
__get_cpu_var(y) = x;
Converts to
__this_cpu_write(y, x);
6. Increment/Decrement etc of a per cpu variable
DEFINE_PER_CPU(int, y);
__get_cpu_var(y)++
Converts to
__this_cpu_inc(y)
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: x86@kernel.org
Acked-by: H. Peter Anvin <hpa@linux.intel.com>
Acked-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Christoph Lameter <cl@linux.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2014-08-17 17:30:40 +00:00
|
|
|
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
|
2010-03-02 19:32:08 +00:00
|
|
|
|
2012-06-20 18:46:33 +00:00
|
|
|
if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
|
2010-02-26 11:05:05 +00:00
|
|
|
intel_pmu_disable_bts();
|
|
|
|
|
intel_pmu_drain_bts_buffer();
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2011-10-05 12:01:21 +00:00
|
|
|
cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
|
|
|
|
|
cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
|
2013-09-12 10:53:44 +00:00
|
|
|
cpuc->intel_cp_status &= ~(1ull << hwc->idx);
|
2011-10-05 12:01:21 +00:00
|
|
|
|
2012-02-09 22:20:57 +00:00
|
|
|
/*
|
|
|
|
|
* must disable before any actual event
|
|
|
|
|
* because any event may be combined with LBR
|
|
|
|
|
*/
|
2014-11-05 02:56:06 +00:00
|
|
|
if (needs_branch_stack(event))
|
2012-02-09 22:20:57 +00:00
|
|
|
intel_pmu_lbr_disable(event);
|
|
|
|
|
|
2010-02-26 11:05:05 +00:00
|
|
|
if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
|
2010-03-02 19:32:08 +00:00
|
|
|
intel_pmu_disable_fixed(hwc);
|
2010-02-26 11:05:05 +00:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2010-03-02 19:32:08 +00:00
|
|
|
x86_pmu_disable_event(event);
|
perf, x86: Add PEBS infrastructure
This patch implements support for Intel Precise Event Based Sampling,
which is an alternative counter mode in which the counter triggers a
hardware assist to collect information on events. The hardware assist
takes a trap like snapshot of a subset of the machine registers.
This data is written to the Intel Debug-Store, which can be programmed
with a data threshold at which to raise a PMI.
With the PEBS hardware assist being trap like, the reported IP is always
one instruction after the actual instruction that triggered the event.
This implements a simple PEBS model that always takes a single PEBS event
at a time. This is done so that the interaction with the rest of the
system is as expected (freq adjust, period randomization, lbr,
callchains, etc.).
It adds an ABI element: perf_event_attr::precise, which indicates that we
wish to use this (constrained, but precise) mode.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100304140100.392111285@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-02 18:52:12 +00:00
|
|
|
|
2010-04-08 21:03:20 +00:00
|
|
|
if (unlikely(event->attr.precise_ip))
|
2010-03-03 12:12:23 +00:00
|
|
|
intel_pmu_pebs_disable(event);
|
2010-02-26 11:05:05 +00:00
|
|
|
}
|
|
|
|
|
|
perf, x86: Add PEBS infrastructure
This patch implements support for Intel Precise Event Based Sampling,
which is an alternative counter mode in which the counter triggers a
hardware assist to collect information on events. The hardware assist
takes a trap like snapshot of a subset of the machine registers.
This data is written to the Intel Debug-Store, which can be programmed
with a data threshold at which to raise a PMI.
With the PEBS hardware assist being trap like, the reported IP is always
one instruction after the actual instruction that triggered the event.
This implements a simple PEBS model that always takes a single PEBS event
at a time. This is done so that the interaction with the rest of the
system is as expected (freq adjust, period randomization, lbr,
callchains, etc.).
It adds an ABI element: perf_event_attr::precise, which indicates that we
wish to use this (constrained, but precise) mode.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100304140100.392111285@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-02 18:52:12 +00:00
|
|
|
static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
|
2010-02-26 11:05:05 +00:00
|
|
|
{
|
2012-06-20 18:46:33 +00:00
|
|
|
int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
|
2010-02-26 11:05:05 +00:00
|
|
|
u64 ctrl_val, bits, mask;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Enable IRQ generation (0x8),
|
|
|
|
|
* and enable ring-3 counting (0x2) and ring-0 counting (0x1)
|
|
|
|
|
* if requested:
|
|
|
|
|
*/
|
|
|
|
|
bits = 0x8ULL;
|
|
|
|
|
if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
|
|
|
|
|
bits |= 0x2;
|
|
|
|
|
if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
|
|
|
|
|
bits |= 0x1;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* ANY bit is supported in v3 and up
|
|
|
|
|
*/
|
|
|
|
|
if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
|
|
|
|
|
bits |= 0x4;
|
|
|
|
|
|
|
|
|
|
bits <<= (idx * 4);
|
|
|
|
|
mask = 0xfULL << (idx * 4);
|
|
|
|
|
|
|
|
|
|
rdmsrl(hwc->config_base, ctrl_val);
|
|
|
|
|
ctrl_val &= ~mask;
|
|
|
|
|
ctrl_val |= bits;
|
2010-03-08 12:51:31 +00:00
|
|
|
wrmsrl(hwc->config_base, ctrl_val);
|
2010-02-26 11:05:05 +00:00
|
|
|
}
|
|
|
|
|
|
2010-03-02 19:32:08 +00:00
|
|
|
static void intel_pmu_enable_event(struct perf_event *event)
|
2010-02-26 11:05:05 +00:00
|
|
|
{
|
2010-03-02 19:32:08 +00:00
|
|
|
struct hw_perf_event *hwc = &event->hw;
|
x86: Replace __get_cpu_var uses
__get_cpu_var() is used for multiple purposes in the kernel source. One of
them is address calculation via the form &__get_cpu_var(x). This calculates
the address for the instance of the percpu variable of the current processor
based on an offset.
Other use cases are for storing and retrieving data from the current
processors percpu area. __get_cpu_var() can be used as an lvalue when
writing data or on the right side of an assignment.
__get_cpu_var() is defined as :
#define __get_cpu_var(var) (*this_cpu_ptr(&(var)))
__get_cpu_var() always only does an address determination. However, store
and retrieve operations could use a segment prefix (or global register on
other platforms) to avoid the address calculation.
this_cpu_write() and this_cpu_read() can directly take an offset into a
percpu area and use optimized assembly code to read and write per cpu
variables.
This patch converts __get_cpu_var into either an explicit address
calculation using this_cpu_ptr() or into a use of this_cpu operations that
use the offset. Thereby address calculations are avoided and less registers
are used when code is generated.
Transformations done to __get_cpu_var()
1. Determine the address of the percpu instance of the current processor.
DEFINE_PER_CPU(int, y);
int *x = &__get_cpu_var(y);
Converts to
int *x = this_cpu_ptr(&y);
2. Same as #1 but this time an array structure is involved.
DEFINE_PER_CPU(int, y[20]);
int *x = __get_cpu_var(y);
Converts to
int *x = this_cpu_ptr(y);
3. Retrieve the content of the current processors instance of a per cpu
variable.
DEFINE_PER_CPU(int, y);
int x = __get_cpu_var(y)
Converts to
int x = __this_cpu_read(y);
4. Retrieve the content of a percpu struct
DEFINE_PER_CPU(struct mystruct, y);
struct mystruct x = __get_cpu_var(y);
Converts to
memcpy(&x, this_cpu_ptr(&y), sizeof(x));
5. Assignment to a per cpu variable
DEFINE_PER_CPU(int, y)
__get_cpu_var(y) = x;
Converts to
__this_cpu_write(y, x);
6. Increment/Decrement etc of a per cpu variable
DEFINE_PER_CPU(int, y);
__get_cpu_var(y)++
Converts to
__this_cpu_inc(y)
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: x86@kernel.org
Acked-by: H. Peter Anvin <hpa@linux.intel.com>
Acked-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Christoph Lameter <cl@linux.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2014-08-17 17:30:40 +00:00
|
|
|
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
|
2010-03-02 19:32:08 +00:00
|
|
|
|
2012-06-20 18:46:33 +00:00
|
|
|
if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
|
2010-12-18 15:28:55 +00:00
|
|
|
if (!__this_cpu_read(cpu_hw_events.enabled))
|
2010-02-26 11:05:05 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
intel_pmu_enable_bts(hwc->config);
|
|
|
|
|
return;
|
|
|
|
|
}
|
2012-02-09 22:20:57 +00:00
|
|
|
/*
|
|
|
|
|
* must enabled before any actual event
|
|
|
|
|
* because any event may be combined with LBR
|
|
|
|
|
*/
|
2014-11-05 02:56:06 +00:00
|
|
|
if (needs_branch_stack(event))
|
2012-02-09 22:20:57 +00:00
|
|
|
intel_pmu_lbr_enable(event);
|
2010-02-26 11:05:05 +00:00
|
|
|
|
2011-10-05 12:01:21 +00:00
|
|
|
if (event->attr.exclude_host)
|
|
|
|
|
cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
|
|
|
|
|
if (event->attr.exclude_guest)
|
|
|
|
|
cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
|
|
|
|
|
|
2013-09-12 10:53:44 +00:00
|
|
|
if (unlikely(event_is_checkpointed(event)))
|
|
|
|
|
cpuc->intel_cp_status |= (1ull << hwc->idx);
|
|
|
|
|
|
2010-02-26 11:05:05 +00:00
|
|
|
if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
|
2010-03-02 19:32:08 +00:00
|
|
|
intel_pmu_enable_fixed(hwc);
|
2010-02-26 11:05:05 +00:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2010-04-08 21:03:20 +00:00
|
|
|
if (unlikely(event->attr.precise_ip))
|
2010-03-03 12:12:23 +00:00
|
|
|
intel_pmu_pebs_enable(event);
|
perf, x86: Add PEBS infrastructure
This patch implements support for Intel Precise Event Based Sampling,
which is an alternative counter mode in which the counter triggers a
hardware assist to collect information on events. The hardware assist
takes a trap like snapshot of a subset of the machine registers.
This data is written to the Intel Debug-Store, which can be programmed
with a data threshold at which to raise a PMI.
With the PEBS hardware assist being trap like, the reported IP is always
one instruction after the actual instruction that triggered the event.
This implements a simple PEBS model that always takes a single PEBS event
at a time. This is done so that the interaction with the rest of the
system is as expected (freq adjust, period randomization, lbr,
callchains, etc.).
It adds an ABI element: perf_event_attr::precise, which indicates that we
wish to use this (constrained, but precise) mode.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100304140100.392111285@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-02 18:52:12 +00:00
|
|
|
|
2010-04-13 20:23:14 +00:00
|
|
|
__x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
|
2010-02-26 11:05:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Save and restart an expired event. Called by NMI contexts,
|
|
|
|
|
* so it has to be careful about preempting normal event ops:
|
|
|
|
|
*/
|
2011-08-30 23:41:05 +00:00
|
|
|
int intel_pmu_save_and_restart(struct perf_event *event)
|
2010-02-26 11:05:05 +00:00
|
|
|
{
|
2010-03-02 19:18:39 +00:00
|
|
|
x86_perf_event_update(event);
|
2013-09-06 03:37:38 +00:00
|
|
|
/*
|
|
|
|
|
* For a checkpointed counter always reset back to 0. This
|
|
|
|
|
* avoids a situation where the counter overflows, aborts the
|
|
|
|
|
* transaction and is then set back to shortly before the
|
|
|
|
|
* overflow, and overflows and aborts again.
|
|
|
|
|
*/
|
|
|
|
|
if (unlikely(event_is_checkpointed(event))) {
|
|
|
|
|
/* No race with NMIs because the counter should not be armed */
|
|
|
|
|
wrmsrl(event->hw.event_base, 0);
|
|
|
|
|
local64_set(&event->hw.prev_count, 0);
|
|
|
|
|
}
|
2010-03-02 19:18:39 +00:00
|
|
|
return x86_perf_event_set_period(event);
|
2010-02-26 11:05:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void intel_pmu_reset(void)
|
|
|
|
|
{
|
2010-12-18 15:28:55 +00:00
|
|
|
struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
|
2010-02-26 11:05:05 +00:00
|
|
|
unsigned long flags;
|
|
|
|
|
int idx;
|
|
|
|
|
|
2010-03-29 16:36:50 +00:00
|
|
|
if (!x86_pmu.num_counters)
|
2010-02-26 11:05:05 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
local_irq_save(flags);
|
|
|
|
|
|
2012-05-22 02:50:07 +00:00
|
|
|
pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
|
2010-02-26 11:05:05 +00:00
|
|
|
|
2010-03-29 16:36:50 +00:00
|
|
|
for (idx = 0; idx < x86_pmu.num_counters; idx++) {
|
2012-06-07 20:32:04 +00:00
|
|
|
wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
|
|
|
|
|
wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
|
2010-02-26 11:05:05 +00:00
|
|
|
}
|
2010-03-29 16:36:50 +00:00
|
|
|
for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
|
2012-06-07 20:32:04 +00:00
|
|
|
wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
|
2010-03-29 16:36:50 +00:00
|
|
|
|
2010-02-26 11:05:05 +00:00
|
|
|
if (ds)
|
|
|
|
|
ds->bts_index = ds->bts_buffer_base;
|
|
|
|
|
|
|
|
|
|
local_irq_restore(flags);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* This handler is triggered by the local APIC, so the APIC IRQ handling
|
|
|
|
|
* rules apply:
|
|
|
|
|
*/
|
|
|
|
|
static int intel_pmu_handle_irq(struct pt_regs *regs)
|
|
|
|
|
{
|
|
|
|
|
struct perf_sample_data data;
|
|
|
|
|
struct cpu_hw_events *cpuc;
|
|
|
|
|
int bit, loops;
|
2010-09-02 19:07:47 +00:00
|
|
|
u64 status;
|
2010-09-10 11:28:01 +00:00
|
|
|
int handled;
|
2010-02-26 11:05:05 +00:00
|
|
|
|
x86: Replace __get_cpu_var uses
__get_cpu_var() is used for multiple purposes in the kernel source. One of
them is address calculation via the form &__get_cpu_var(x). This calculates
the address for the instance of the percpu variable of the current processor
based on an offset.
Other use cases are for storing and retrieving data from the current
processors percpu area. __get_cpu_var() can be used as an lvalue when
writing data or on the right side of an assignment.
__get_cpu_var() is defined as :
#define __get_cpu_var(var) (*this_cpu_ptr(&(var)))
__get_cpu_var() always only does an address determination. However, store
and retrieve operations could use a segment prefix (or global register on
other platforms) to avoid the address calculation.
this_cpu_write() and this_cpu_read() can directly take an offset into a
percpu area and use optimized assembly code to read and write per cpu
variables.
This patch converts __get_cpu_var into either an explicit address
calculation using this_cpu_ptr() or into a use of this_cpu operations that
use the offset. Thereby address calculations are avoided and less registers
are used when code is generated.
Transformations done to __get_cpu_var()
1. Determine the address of the percpu instance of the current processor.
DEFINE_PER_CPU(int, y);
int *x = &__get_cpu_var(y);
Converts to
int *x = this_cpu_ptr(&y);
2. Same as #1 but this time an array structure is involved.
DEFINE_PER_CPU(int, y[20]);
int *x = __get_cpu_var(y);
Converts to
int *x = this_cpu_ptr(y);
3. Retrieve the content of the current processors instance of a per cpu
variable.
DEFINE_PER_CPU(int, y);
int x = __get_cpu_var(y)
Converts to
int x = __this_cpu_read(y);
4. Retrieve the content of a percpu struct
DEFINE_PER_CPU(struct mystruct, y);
struct mystruct x = __get_cpu_var(y);
Converts to
memcpy(&x, this_cpu_ptr(&y), sizeof(x));
5. Assignment to a per cpu variable
DEFINE_PER_CPU(int, y)
__get_cpu_var(y) = x;
Converts to
__this_cpu_write(y, x);
6. Increment/Decrement etc of a per cpu variable
DEFINE_PER_CPU(int, y);
__get_cpu_var(y)++
Converts to
__this_cpu_inc(y)
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: x86@kernel.org
Acked-by: H. Peter Anvin <hpa@linux.intel.com>
Acked-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Christoph Lameter <cl@linux.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2014-08-17 17:30:40 +00:00
|
|
|
cpuc = this_cpu_ptr(&cpu_hw_events);
|
2010-02-26 11:05:05 +00:00
|
|
|
|
2011-04-27 10:32:33 +00:00
|
|
|
/*
|
2013-06-18 00:36:50 +00:00
|
|
|
* No known reason to not always do late ACK,
|
|
|
|
|
* but just in case do it opt-in.
|
2011-04-27 10:32:33 +00:00
|
|
|
*/
|
2013-06-18 00:36:50 +00:00
|
|
|
if (!x86_pmu.late_ack)
|
|
|
|
|
apic_write(APIC_LVTPC, APIC_DM_NMI);
|
2010-03-08 12:51:01 +00:00
|
|
|
intel_pmu_disable_all();
|
2010-09-10 11:28:01 +00:00
|
|
|
handled = intel_pmu_drain_bts_buffer();
|
2010-02-26 11:05:05 +00:00
|
|
|
status = intel_pmu_get_status();
|
2014-02-15 00:44:08 +00:00
|
|
|
if (!status)
|
|
|
|
|
goto done;
|
2010-02-26 11:05:05 +00:00
|
|
|
|
|
|
|
|
loops = 0;
|
|
|
|
|
again:
|
2010-09-02 19:07:47 +00:00
|
|
|
intel_pmu_ack_status(status);
|
2010-02-26 11:05:05 +00:00
|
|
|
if (++loops > 100) {
|
2013-05-30 17:45:59 +00:00
|
|
|
static bool warned = false;
|
|
|
|
|
if (!warned) {
|
|
|
|
|
WARN(1, "perfevents: irq loop stuck!\n");
|
|
|
|
|
perf_event_print_debug();
|
|
|
|
|
warned = true;
|
|
|
|
|
}
|
2010-02-26 11:05:05 +00:00
|
|
|
intel_pmu_reset();
|
2010-03-08 12:51:01 +00:00
|
|
|
goto done;
|
2010-02-26 11:05:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
inc_irq_stat(apic_perf_irqs);
|
perf, x86: Add PEBS infrastructure
This patch implements support for Intel Precise Event Based Sampling,
which is an alternative counter mode in which the counter triggers a
hardware assist to collect information on events. The hardware assist
takes a trap like snapshot of a subset of the machine registers.
This data is written to the Intel Debug-Store, which can be programmed
with a data threshold at which to raise a PMI.
With the PEBS hardware assist being trap like, the reported IP is always
one instruction after the actual instruction that triggered the event.
This implements a simple PEBS model that always takes a single PEBS event
at a time. This is done so that the interaction with the rest of the
system is as expected (freq adjust, period randomization, lbr,
callchains, etc.).
It adds an ABI element: perf_event_attr::precise, which indicates that we
wish to use this (constrained, but precise) mode.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100304140100.392111285@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-02 18:52:12 +00:00
|
|
|
|
2010-03-03 11:02:30 +00:00
|
|
|
intel_pmu_lbr_read();
|
|
|
|
|
|
perf/x86/intel: ignore CondChgd bit to avoid false NMI handling
Currently, any NMI is falsely handled by a NMI handler of NMI watchdog
if CondChgd bit in MSR_CORE_PERF_GLOBAL_STATUS MSR is set.
For example, we use external NMI to make system panic to get crash
dump, but in this case, the external NMI is falsely handled do to the
issue.
This commit deals with the issue simply by ignoring CondChgd bit.
Here is explanation in detail.
On x86 NMI watchdog uses performance monitoring feature to
periodically signal NMI each time performance counter gets overflowed.
intel_pmu_handle_irq() is called as a NMI_LOCAL handler from a NMI
handler of NMI watchdog, perf_event_nmi_handler(). It identifies an
owner of a given NMI by looking at overflow status bits in
MSR_CORE_PERF_GLOBAL_STATUS MSR. If some of the bits are set, then it
handles the given NMI as its own NMI.
The problem is that the intel_pmu_handle_irq() doesn't distinguish
CondChgd bit from other bits. Unlike the other status bits, CondChgd
bit doesn't represent overflow status for performance counters. Thus,
CondChgd bit cannot be thought of as a mark indicating a given NMI is
NMI watchdog's.
As a result, if CondChgd bit is set, any NMI is falsely handled by the
NMI handler of NMI watchdog. Also, if type of the falsely handled NMI
is either NMI_UNKNOWN, NMI_SERR or NMI_IO_CHECK, the corresponding
action is never performed until CondChgd bit is cleared.
I noticed this behavior on systems with Ivy Bridge processors: Intel
Xeon CPU E5-2630 v2 and Intel Xeon CPU E7-8890 v2. On both systems,
CondChgd bit in MSR_CORE_PERF_GLOBAL_STATUS MSR has already been set
in the beginning at boot. Then the CondChgd bit is immediately cleared
by next wrmsr to MSR_CORE_PERF_GLOBAL_CTRL MSR and appears to remain
0.
On the other hand, on older processors such as Nehalem, Xeon E7540,
CondChgd bit is not set in the beginning at boot.
I'm not sure about exact behavior of CondChgd bit, in particular when
this bit is set. Although I read Intel System Programmer's Manual to
figure out that, the descriptions I found are:
In 18.9.1:
"The MSR_PERF_GLOBAL_STATUS MSR also provides a ¡sticky bit¢ to
indicate changes to the state of performancmonitoring hardware"
In Table 35-2 IA-32 Architectural MSRs
63 CondChg: status bits of this register has changed.
These are different from the bahviour I see on the actual system as I
explained above.
At least, I think ignoring CondChgd bit should be enough for NMI
watchdog perspective.
Signed-off-by: HATAYAMA Daisuke <d.hatayama@jp.fujitsu.com>
Acked-by: Don Zickus <dzickus@redhat.com>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Cc: <stable@vger.kernel.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: linux-kernel@vger.kernel.org
Link: http://lkml.kernel.org/r/20140625.103503.409316067.d.hatayama@jp.fujitsu.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2014-06-25 01:09:07 +00:00
|
|
|
/*
|
|
|
|
|
* CondChgd bit 63 doesn't mean any overflow status. Ignore
|
|
|
|
|
* and clear the bit.
|
|
|
|
|
*/
|
|
|
|
|
if (__test_and_clear_bit(63, (unsigned long *)&status)) {
|
|
|
|
|
if (!status)
|
|
|
|
|
goto done;
|
|
|
|
|
}
|
|
|
|
|
|
perf, x86: Add PEBS infrastructure
This patch implements support for Intel Precise Event Based Sampling,
which is an alternative counter mode in which the counter triggers a
hardware assist to collect information on events. The hardware assist
takes a trap like snapshot of a subset of the machine registers.
This data is written to the Intel Debug-Store, which can be programmed
with a data threshold at which to raise a PMI.
With the PEBS hardware assist being trap like, the reported IP is always
one instruction after the actual instruction that triggered the event.
This implements a simple PEBS model that always takes a single PEBS event
at a time. This is done so that the interaction with the rest of the
system is as expected (freq adjust, period randomization, lbr,
callchains, etc.).
It adds an ABI element: perf_event_attr::precise, which indicates that we
wish to use this (constrained, but precise) mode.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100304140100.392111285@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-02 18:52:12 +00:00
|
|
|
/*
|
|
|
|
|
* PEBS overflow sets bit 62 in the global status register
|
|
|
|
|
*/
|
2010-09-02 19:07:49 +00:00
|
|
|
if (__test_and_clear_bit(62, (unsigned long *)&status)) {
|
|
|
|
|
handled++;
|
perf, x86: Add PEBS infrastructure
This patch implements support for Intel Precise Event Based Sampling,
which is an alternative counter mode in which the counter triggers a
hardware assist to collect information on events. The hardware assist
takes a trap like snapshot of a subset of the machine registers.
This data is written to the Intel Debug-Store, which can be programmed
with a data threshold at which to raise a PMI.
With the PEBS hardware assist being trap like, the reported IP is always
one instruction after the actual instruction that triggered the event.
This implements a simple PEBS model that always takes a single PEBS event
at a time. This is done so that the interaction with the rest of the
system is as expected (freq adjust, period randomization, lbr,
callchains, etc.).
It adds an ABI element: perf_event_attr::precise, which indicates that we
wish to use this (constrained, but precise) mode.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100304140100.392111285@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-02 18:52:12 +00:00
|
|
|
x86_pmu.drain_pebs(regs);
|
2010-09-02 19:07:49 +00:00
|
|
|
}
|
perf, x86: Add PEBS infrastructure
This patch implements support for Intel Precise Event Based Sampling,
which is an alternative counter mode in which the counter triggers a
hardware assist to collect information on events. The hardware assist
takes a trap like snapshot of a subset of the machine registers.
This data is written to the Intel Debug-Store, which can be programmed
with a data threshold at which to raise a PMI.
With the PEBS hardware assist being trap like, the reported IP is always
one instruction after the actual instruction that triggered the event.
This implements a simple PEBS model that always takes a single PEBS event
at a time. This is done so that the interaction with the rest of the
system is as expected (freq adjust, period randomization, lbr,
callchains, etc.).
It adds an ABI element: perf_event_attr::precise, which indicates that we
wish to use this (constrained, but precise) mode.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100304140100.392111285@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-02 18:52:12 +00:00
|
|
|
|
2013-09-06 03:37:38 +00:00
|
|
|
/*
|
2013-09-12 10:53:44 +00:00
|
|
|
* Checkpointed counters can lead to 'spurious' PMIs because the
|
|
|
|
|
* rollback caused by the PMI will have cleared the overflow status
|
|
|
|
|
* bit. Therefore always force probe these counters.
|
2013-09-06 03:37:38 +00:00
|
|
|
*/
|
2013-09-12 10:53:44 +00:00
|
|
|
status |= cpuc->intel_cp_status;
|
2013-09-06 03:37:38 +00:00
|
|
|
|
2010-03-05 21:41:37 +00:00
|
|
|
for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
|
2010-02-26 11:05:05 +00:00
|
|
|
struct perf_event *event = cpuc->events[bit];
|
|
|
|
|
|
2010-09-02 19:07:49 +00:00
|
|
|
handled++;
|
|
|
|
|
|
2010-02-26 11:05:05 +00:00
|
|
|
if (!test_bit(bit, cpuc->active_mask))
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
if (!intel_pmu_save_and_restart(event))
|
|
|
|
|
continue;
|
|
|
|
|
|
2012-04-02 18:19:08 +00:00
|
|
|
perf_sample_data_init(&data, 0, event->hw.last_period);
|
2010-02-26 11:05:05 +00:00
|
|
|
|
2012-02-09 22:20:57 +00:00
|
|
|
if (has_branch_stack(event))
|
|
|
|
|
data.br_stack = &cpuc->lbr_stack;
|
|
|
|
|
|
2011-06-27 12:41:57 +00:00
|
|
|
if (perf_event_overflow(event, &data, regs))
|
perf: Rework the PMU methods
Replace pmu::{enable,disable,start,stop,unthrottle} with
pmu::{add,del,start,stop}, all of which take a flags argument.
The new interface extends the capability to stop a counter while
keeping it scheduled on the PMU. We replace the throttled state with
the generic stopped state.
This also allows us to efficiently stop/start counters over certain
code paths (like IRQ handlers).
It also allows scheduling a counter without it starting, allowing for
a generic frozen state (useful for rotating stopped counters).
The stopped state is implemented in two different ways, depending on
how the architecture implemented the throttled state:
1) We disable the counter:
a) the pmu has per-counter enable bits, we flip that
b) we program a NOP event, preserving the counter state
2) We store the counter state and ignore all read/overflow events
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: paulus <paulus@samba.org>
Cc: stephane eranian <eranian@googlemail.com>
Cc: Robert Richter <robert.richter@amd.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Cyrill Gorcunov <gorcunov@gmail.com>
Cc: Lin Ming <ming.m.lin@intel.com>
Cc: Yanmin <yanmin_zhang@linux.intel.com>
Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com>
Cc: David Miller <davem@davemloft.net>
Cc: Michael Cree <mcree@orcon.net.nz>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-06-16 12:37:10 +00:00
|
|
|
x86_pmu_stop(event, 0);
|
2010-02-26 11:05:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Repeat if there is more work to be done:
|
|
|
|
|
*/
|
|
|
|
|
status = intel_pmu_get_status();
|
|
|
|
|
if (status)
|
|
|
|
|
goto again;
|
|
|
|
|
|
2010-03-08 12:51:01 +00:00
|
|
|
done:
|
2010-03-26 13:08:44 +00:00
|
|
|
intel_pmu_enable_all(0);
|
2013-06-18 00:36:50 +00:00
|
|
|
/*
|
|
|
|
|
* Only unmask the NMI after the overflow counters
|
|
|
|
|
* have been reset. This avoids spurious NMIs on
|
|
|
|
|
* Haswell CPUs.
|
|
|
|
|
*/
|
|
|
|
|
if (x86_pmu.late_ack)
|
|
|
|
|
apic_write(APIC_LVTPC, APIC_DM_NMI);
|
2010-09-02 19:07:49 +00:00
|
|
|
return handled;
|
2010-02-26 11:05:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct event_constraint *
|
perf, x86: Add PEBS infrastructure
This patch implements support for Intel Precise Event Based Sampling,
which is an alternative counter mode in which the counter triggers a
hardware assist to collect information on events. The hardware assist
takes a trap like snapshot of a subset of the machine registers.
This data is written to the Intel Debug-Store, which can be programmed
with a data threshold at which to raise a PMI.
With the PEBS hardware assist being trap like, the reported IP is always
one instruction after the actual instruction that triggered the event.
This implements a simple PEBS model that always takes a single PEBS event
at a time. This is done so that the interaction with the rest of the
system is as expected (freq adjust, period randomization, lbr,
callchains, etc.).
It adds an ABI element: perf_event_attr::precise, which indicates that we
wish to use this (constrained, but precise) mode.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100304140100.392111285@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-02 18:52:12 +00:00
|
|
|
intel_bts_constraints(struct perf_event *event)
|
2010-02-26 11:05:05 +00:00
|
|
|
{
|
perf, x86: Add PEBS infrastructure
This patch implements support for Intel Precise Event Based Sampling,
which is an alternative counter mode in which the counter triggers a
hardware assist to collect information on events. The hardware assist
takes a trap like snapshot of a subset of the machine registers.
This data is written to the Intel Debug-Store, which can be programmed
with a data threshold at which to raise a PMI.
With the PEBS hardware assist being trap like, the reported IP is always
one instruction after the actual instruction that triggered the event.
This implements a simple PEBS model that always takes a single PEBS event
at a time. This is done so that the interaction with the rest of the
system is as expected (freq adjust, period randomization, lbr,
callchains, etc.).
It adds an ABI element: perf_event_attr::precise, which indicates that we
wish to use this (constrained, but precise) mode.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100304140100.392111285@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-02 18:52:12 +00:00
|
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
|
|
|
unsigned int hw_event, bts_event;
|
2010-02-26 11:05:05 +00:00
|
|
|
|
2011-04-26 11:24:33 +00:00
|
|
|
if (event->attr.freq)
|
|
|
|
|
return NULL;
|
|
|
|
|
|
perf, x86: Add PEBS infrastructure
This patch implements support for Intel Precise Event Based Sampling,
which is an alternative counter mode in which the counter triggers a
hardware assist to collect information on events. The hardware assist
takes a trap like snapshot of a subset of the machine registers.
This data is written to the Intel Debug-Store, which can be programmed
with a data threshold at which to raise a PMI.
With the PEBS hardware assist being trap like, the reported IP is always
one instruction after the actual instruction that triggered the event.
This implements a simple PEBS model that always takes a single PEBS event
at a time. This is done so that the interaction with the rest of the
system is as expected (freq adjust, period randomization, lbr,
callchains, etc.).
It adds an ABI element: perf_event_attr::precise, which indicates that we
wish to use this (constrained, but precise) mode.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100304140100.392111285@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-02 18:52:12 +00:00
|
|
|
hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
|
|
|
|
|
bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
|
2010-02-26 11:05:05 +00:00
|
|
|
|
perf, x86: Add PEBS infrastructure
This patch implements support for Intel Precise Event Based Sampling,
which is an alternative counter mode in which the counter triggers a
hardware assist to collect information on events. The hardware assist
takes a trap like snapshot of a subset of the machine registers.
This data is written to the Intel Debug-Store, which can be programmed
with a data threshold at which to raise a PMI.
With the PEBS hardware assist being trap like, the reported IP is always
one instruction after the actual instruction that triggered the event.
This implements a simple PEBS model that always takes a single PEBS event
at a time. This is done so that the interaction with the rest of the
system is as expected (freq adjust, period randomization, lbr,
callchains, etc.).
It adds an ABI element: perf_event_attr::precise, which indicates that we
wish to use this (constrained, but precise) mode.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100304140100.392111285@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-02 18:52:12 +00:00
|
|
|
if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
|
2010-02-26 11:05:05 +00:00
|
|
|
return &bts_constraint;
|
perf, x86: Add PEBS infrastructure
This patch implements support for Intel Precise Event Based Sampling,
which is an alternative counter mode in which the counter triggers a
hardware assist to collect information on events. The hardware assist
takes a trap like snapshot of a subset of the machine registers.
This data is written to the Intel Debug-Store, which can be programmed
with a data threshold at which to raise a PMI.
With the PEBS hardware assist being trap like, the reported IP is always
one instruction after the actual instruction that triggered the event.
This implements a simple PEBS model that always takes a single PEBS event
at a time. This is done so that the interaction with the rest of the
system is as expected (freq adjust, period randomization, lbr,
callchains, etc.).
It adds an ABI element: perf_event_attr::precise, which indicates that we
wish to use this (constrained, but precise) mode.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100304140100.392111285@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-02 18:52:12 +00:00
|
|
|
|
2010-02-26 11:05:05 +00:00
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
2012-06-05 13:30:31 +00:00
|
|
|
static int intel_alt_er(int idx)
|
2011-05-23 09:08:15 +00:00
|
|
|
{
|
|
|
|
|
if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
|
2012-06-05 13:30:31 +00:00
|
|
|
return idx;
|
2011-05-23 09:08:15 +00:00
|
|
|
|
2012-06-05 13:30:31 +00:00
|
|
|
if (idx == EXTRA_REG_RSP_0)
|
|
|
|
|
return EXTRA_REG_RSP_1;
|
|
|
|
|
|
|
|
|
|
if (idx == EXTRA_REG_RSP_1)
|
|
|
|
|
return EXTRA_REG_RSP_0;
|
|
|
|
|
|
|
|
|
|
return idx;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void intel_fixup_er(struct perf_event *event, int idx)
|
|
|
|
|
{
|
|
|
|
|
event->hw.extra_reg.idx = idx;
|
|
|
|
|
|
|
|
|
|
if (idx == EXTRA_REG_RSP_0) {
|
2011-05-23 09:08:15 +00:00
|
|
|
event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
|
2013-07-18 09:02:23 +00:00
|
|
|
event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
|
2011-05-23 09:08:15 +00:00
|
|
|
event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
|
2012-06-05 13:30:31 +00:00
|
|
|
} else if (idx == EXTRA_REG_RSP_1) {
|
|
|
|
|
event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
|
2013-07-18 09:02:23 +00:00
|
|
|
event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
|
2012-06-05 13:30:31 +00:00
|
|
|
event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
|
2011-05-23 09:08:15 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2011-06-06 14:57:03 +00:00
|
|
|
/*
|
|
|
|
|
* manage allocation of shared extra msr for certain events
|
|
|
|
|
*
|
|
|
|
|
* sharing can be:
|
|
|
|
|
* per-cpu: to be shared between the various events on a single PMU
|
|
|
|
|
* per-core: per-cpu + shared by HT threads
|
|
|
|
|
*/
|
2011-03-03 02:34:47 +00:00
|
|
|
static struct event_constraint *
|
2011-06-06 14:57:03 +00:00
|
|
|
__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
|
2012-02-09 22:20:53 +00:00
|
|
|
struct perf_event *event,
|
|
|
|
|
struct hw_perf_event_extra *reg)
|
2011-03-03 02:34:47 +00:00
|
|
|
{
|
2011-06-06 14:57:03 +00:00
|
|
|
struct event_constraint *c = &emptyconstraint;
|
2011-03-03 02:34:47 +00:00
|
|
|
struct er_account *era;
|
2011-06-06 14:57:08 +00:00
|
|
|
unsigned long flags;
|
2012-06-05 13:30:31 +00:00
|
|
|
int idx = reg->idx;
|
2011-03-03 02:34:47 +00:00
|
|
|
|
2012-06-05 13:30:31 +00:00
|
|
|
/*
|
|
|
|
|
* reg->alloc can be set due to existing state, so for fake cpuc we
|
|
|
|
|
* need to ignore this, otherwise we might fail to allocate proper fake
|
|
|
|
|
* state for this extra reg constraint. Also see the comment below.
|
|
|
|
|
*/
|
|
|
|
|
if (reg->alloc && !cpuc->is_fake)
|
2012-02-09 22:20:53 +00:00
|
|
|
return NULL; /* call x86_get_event_constraint() */
|
2011-03-03 02:34:47 +00:00
|
|
|
|
2011-05-23 09:08:15 +00:00
|
|
|
again:
|
2012-06-05 13:30:31 +00:00
|
|
|
era = &cpuc->shared_regs->regs[idx];
|
2011-06-06 14:57:08 +00:00
|
|
|
/*
|
|
|
|
|
* we use spin_lock_irqsave() to avoid lockdep issues when
|
|
|
|
|
* passing a fake cpuc
|
|
|
|
|
*/
|
|
|
|
|
raw_spin_lock_irqsave(&era->lock, flags);
|
2011-06-06 14:57:03 +00:00
|
|
|
|
|
|
|
|
if (!atomic_read(&era->ref) || era->config == reg->config) {
|
|
|
|
|
|
2012-06-05 13:30:31 +00:00
|
|
|
/*
|
|
|
|
|
* If its a fake cpuc -- as per validate_{group,event}() we
|
|
|
|
|
* shouldn't touch event state and we can avoid doing so
|
|
|
|
|
* since both will only call get_event_constraints() once
|
|
|
|
|
* on each event, this avoids the need for reg->alloc.
|
|
|
|
|
*
|
|
|
|
|
* Not doing the ER fixup will only result in era->reg being
|
|
|
|
|
* wrong, but since we won't actually try and program hardware
|
|
|
|
|
* this isn't a problem either.
|
|
|
|
|
*/
|
|
|
|
|
if (!cpuc->is_fake) {
|
|
|
|
|
if (idx != reg->idx)
|
|
|
|
|
intel_fixup_er(event, idx);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* x86_schedule_events() can call get_event_constraints()
|
|
|
|
|
* multiple times on events in the case of incremental
|
|
|
|
|
* scheduling(). reg->alloc ensures we only do the ER
|
|
|
|
|
* allocation once.
|
|
|
|
|
*/
|
|
|
|
|
reg->alloc = 1;
|
|
|
|
|
}
|
|
|
|
|
|
2011-06-06 14:57:03 +00:00
|
|
|
/* lock in msr value */
|
|
|
|
|
era->config = reg->config;
|
|
|
|
|
era->reg = reg->reg;
|
|
|
|
|
|
|
|
|
|
/* one more user */
|
|
|
|
|
atomic_inc(&era->ref);
|
|
|
|
|
|
2011-03-03 02:34:47 +00:00
|
|
|
/*
|
2012-02-09 22:20:53 +00:00
|
|
|
* need to call x86_get_event_constraint()
|
|
|
|
|
* to check if associated event has constraints
|
2011-03-03 02:34:47 +00:00
|
|
|
*/
|
2012-02-09 22:20:53 +00:00
|
|
|
c = NULL;
|
2012-06-05 13:30:31 +00:00
|
|
|
} else {
|
|
|
|
|
idx = intel_alt_er(idx);
|
|
|
|
|
if (idx != reg->idx) {
|
|
|
|
|
raw_spin_unlock_irqrestore(&era->lock, flags);
|
|
|
|
|
goto again;
|
|
|
|
|
}
|
2011-03-03 02:34:47 +00:00
|
|
|
}
|
2011-06-06 14:57:08 +00:00
|
|
|
raw_spin_unlock_irqrestore(&era->lock, flags);
|
2011-03-03 02:34:47 +00:00
|
|
|
|
2011-06-06 14:57:03 +00:00
|
|
|
return c;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
|
|
|
|
|
struct hw_perf_event_extra *reg)
|
|
|
|
|
{
|
|
|
|
|
struct er_account *era;
|
|
|
|
|
|
|
|
|
|
/*
|
2012-06-05 13:30:31 +00:00
|
|
|
* Only put constraint if extra reg was actually allocated. Also takes
|
|
|
|
|
* care of event which do not use an extra shared reg.
|
|
|
|
|
*
|
|
|
|
|
* Also, if this is a fake cpuc we shouldn't touch any event state
|
|
|
|
|
* (reg->alloc) and we don't care about leaving inconsistent cpuc state
|
|
|
|
|
* either since it'll be thrown out.
|
2011-06-06 14:57:03 +00:00
|
|
|
*/
|
2012-06-05 13:30:31 +00:00
|
|
|
if (!reg->alloc || cpuc->is_fake)
|
2011-06-06 14:57:03 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
era = &cpuc->shared_regs->regs[reg->idx];
|
|
|
|
|
|
|
|
|
|
/* one fewer user */
|
|
|
|
|
atomic_dec(&era->ref);
|
|
|
|
|
|
|
|
|
|
/* allocate again next time */
|
|
|
|
|
reg->alloc = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct event_constraint *
|
|
|
|
|
intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
|
|
|
|
|
struct perf_event *event)
|
|
|
|
|
{
|
2012-02-09 22:20:53 +00:00
|
|
|
struct event_constraint *c = NULL, *d;
|
|
|
|
|
struct hw_perf_event_extra *xreg, *breg;
|
|
|
|
|
|
|
|
|
|
xreg = &event->hw.extra_reg;
|
|
|
|
|
if (xreg->idx != EXTRA_REG_NONE) {
|
|
|
|
|
c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
|
|
|
|
|
if (c == &emptyconstraint)
|
|
|
|
|
return c;
|
|
|
|
|
}
|
|
|
|
|
breg = &event->hw.branch_reg;
|
|
|
|
|
if (breg->idx != EXTRA_REG_NONE) {
|
|
|
|
|
d = __intel_shared_reg_get_constraints(cpuc, event, breg);
|
|
|
|
|
if (d == &emptyconstraint) {
|
|
|
|
|
__intel_shared_reg_put_constraints(cpuc, xreg);
|
|
|
|
|
c = d;
|
|
|
|
|
}
|
|
|
|
|
}
|
2011-06-06 14:57:03 +00:00
|
|
|
return c;
|
2011-03-03 02:34:47 +00:00
|
|
|
}
|
|
|
|
|
|
2011-08-30 23:41:05 +00:00
|
|
|
struct event_constraint *
|
|
|
|
|
x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
|
|
|
|
|
{
|
|
|
|
|
struct event_constraint *c;
|
|
|
|
|
|
|
|
|
|
if (x86_pmu.event_constraints) {
|
|
|
|
|
for_each_event_constraint(c, x86_pmu.event_constraints) {
|
2013-01-24 15:10:27 +00:00
|
|
|
if ((event->hw.config & c->cmask) == c->code) {
|
|
|
|
|
event->hw.flags |= c->flags;
|
2011-08-30 23:41:05 +00:00
|
|
|
return c;
|
2013-01-24 15:10:27 +00:00
|
|
|
}
|
2011-08-30 23:41:05 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return &unconstrained;
|
|
|
|
|
}
|
|
|
|
|
|
2010-02-26 11:05:05 +00:00
|
|
|
static struct event_constraint *
|
|
|
|
|
intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
|
|
|
|
|
{
|
|
|
|
|
struct event_constraint *c;
|
|
|
|
|
|
perf, x86: Add PEBS infrastructure
This patch implements support for Intel Precise Event Based Sampling,
which is an alternative counter mode in which the counter triggers a
hardware assist to collect information on events. The hardware assist
takes a trap like snapshot of a subset of the machine registers.
This data is written to the Intel Debug-Store, which can be programmed
with a data threshold at which to raise a PMI.
With the PEBS hardware assist being trap like, the reported IP is always
one instruction after the actual instruction that triggered the event.
This implements a simple PEBS model that always takes a single PEBS event
at a time. This is done so that the interaction with the rest of the
system is as expected (freq adjust, period randomization, lbr,
callchains, etc.).
It adds an ABI element: perf_event_attr::precise, which indicates that we
wish to use this (constrained, but precise) mode.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100304140100.392111285@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-02 18:52:12 +00:00
|
|
|
c = intel_bts_constraints(event);
|
|
|
|
|
if (c)
|
|
|
|
|
return c;
|
|
|
|
|
|
|
|
|
|
c = intel_pebs_constraints(event);
|
2010-02-26 11:05:05 +00:00
|
|
|
if (c)
|
|
|
|
|
return c;
|
|
|
|
|
|
2011-06-06 14:57:03 +00:00
|
|
|
c = intel_shared_regs_constraints(cpuc, event);
|
2011-03-03 02:34:47 +00:00
|
|
|
if (c)
|
|
|
|
|
return c;
|
|
|
|
|
|
2010-02-26 11:05:05 +00:00
|
|
|
return x86_get_event_constraints(cpuc, event);
|
|
|
|
|
}
|
|
|
|
|
|
2011-06-06 14:57:03 +00:00
|
|
|
static void
|
|
|
|
|
intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
|
2011-03-03 02:34:47 +00:00
|
|
|
struct perf_event *event)
|
|
|
|
|
{
|
2011-06-06 14:57:03 +00:00
|
|
|
struct hw_perf_event_extra *reg;
|
2011-03-03 02:34:47 +00:00
|
|
|
|
2011-06-06 14:57:03 +00:00
|
|
|
reg = &event->hw.extra_reg;
|
|
|
|
|
if (reg->idx != EXTRA_REG_NONE)
|
|
|
|
|
__intel_shared_reg_put_constraints(cpuc, reg);
|
2012-02-09 22:20:53 +00:00
|
|
|
|
|
|
|
|
reg = &event->hw.branch_reg;
|
|
|
|
|
if (reg->idx != EXTRA_REG_NONE)
|
|
|
|
|
__intel_shared_reg_put_constraints(cpuc, reg);
|
2011-06-06 14:57:03 +00:00
|
|
|
}
|
2011-03-03 02:34:47 +00:00
|
|
|
|
2011-06-06 14:57:03 +00:00
|
|
|
static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
|
|
|
|
|
struct perf_event *event)
|
|
|
|
|
{
|
|
|
|
|
intel_put_shared_regs_event_constraints(cpuc, event);
|
2011-03-03 02:34:47 +00:00
|
|
|
}
|
|
|
|
|
|
2012-06-05 08:26:43 +00:00
|
|
|
static void intel_pebs_aliases_core2(struct perf_event *event)
|
2010-03-30 15:00:06 +00:00
|
|
|
{
|
2012-06-05 08:26:43 +00:00
|
|
|
if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
|
2010-12-14 20:26:40 +00:00
|
|
|
/*
|
|
|
|
|
* Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
|
|
|
|
|
* (0x003c) so that we can use it with PEBS.
|
|
|
|
|
*
|
|
|
|
|
* The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
|
|
|
|
|
* PEBS capable. However we can use INST_RETIRED.ANY_P
|
|
|
|
|
* (0x00c0), which is a PEBS capable event, to get the same
|
|
|
|
|
* count.
|
|
|
|
|
*
|
|
|
|
|
* INST_RETIRED.ANY_P counts the number of cycles that retires
|
|
|
|
|
* CNTMASK instructions. By setting CNTMASK to a value (16)
|
|
|
|
|
* larger than the maximum number of instructions that can be
|
|
|
|
|
* retired per cycle (4) and then inverting the condition, we
|
|
|
|
|
* count all cycles that retire 16 or less instructions, which
|
|
|
|
|
* is every cycle.
|
|
|
|
|
*
|
|
|
|
|
* Thereby we gain a PEBS capable cycle counter.
|
|
|
|
|
*/
|
2012-03-12 11:44:35 +00:00
|
|
|
u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
|
|
|
|
|
|
2012-06-05 08:26:43 +00:00
|
|
|
alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
|
|
|
|
|
event->hw.config = alt_config;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void intel_pebs_aliases_snb(struct perf_event *event)
|
|
|
|
|
{
|
|
|
|
|
if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
|
|
|
|
|
/*
|
|
|
|
|
* Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
|
|
|
|
|
* (0x003c) so that we can use it with PEBS.
|
|
|
|
|
*
|
|
|
|
|
* The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
|
|
|
|
|
* PEBS capable. However we can use UOPS_RETIRED.ALL
|
|
|
|
|
* (0x01c2), which is a PEBS capable event, to get the same
|
|
|
|
|
* count.
|
|
|
|
|
*
|
|
|
|
|
* UOPS_RETIRED.ALL counts the number of cycles that retires
|
|
|
|
|
* CNTMASK micro-ops. By setting CNTMASK to a value (16)
|
|
|
|
|
* larger than the maximum number of micro-ops that can be
|
|
|
|
|
* retired per cycle (4) and then inverting the condition, we
|
|
|
|
|
* count all cycles that retire 16 or less micro-ops, which
|
|
|
|
|
* is every cycle.
|
|
|
|
|
*
|
|
|
|
|
* Thereby we gain a PEBS capable cycle counter.
|
|
|
|
|
*/
|
|
|
|
|
u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
|
2010-12-14 20:26:40 +00:00
|
|
|
|
|
|
|
|
alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
|
|
|
|
|
event->hw.config = alt_config;
|
|
|
|
|
}
|
2012-06-05 08:26:43 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int intel_pmu_hw_config(struct perf_event *event)
|
|
|
|
|
{
|
|
|
|
|
int ret = x86_pmu_hw_config(event);
|
|
|
|
|
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
if (event->attr.precise_ip && x86_pmu.pebs_aliases)
|
|
|
|
|
x86_pmu.pebs_aliases(event);
|
2010-12-14 20:26:40 +00:00
|
|
|
|
2014-11-05 02:56:06 +00:00
|
|
|
if (needs_branch_stack(event)) {
|
2012-02-09 22:20:57 +00:00
|
|
|
ret = intel_pmu_setup_lbr_filter(event);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
2015-01-14 12:18:20 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* BTS is set up earlier in this path, so don't account twice
|
|
|
|
|
*/
|
|
|
|
|
if (!intel_pmu_has_bts(event)) {
|
|
|
|
|
/* disallow lbr if conflicting events are present */
|
|
|
|
|
if (x86_add_exclusive(x86_lbr_exclusive_lbr))
|
|
|
|
|
return -EBUSY;
|
|
|
|
|
|
|
|
|
|
event->destroy = hw_perf_lbr_event_destroy;
|
|
|
|
|
}
|
2012-02-09 22:20:57 +00:00
|
|
|
}
|
|
|
|
|
|
2010-03-30 15:00:06 +00:00
|
|
|
if (event->attr.type != PERF_TYPE_RAW)
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
if (x86_pmu.version < 3)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
|
|
|
|
|
return -EACCES;
|
|
|
|
|
|
|
|
|
|
event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2011-10-05 12:01:21 +00:00
|
|
|
struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
|
|
|
|
|
{
|
|
|
|
|
if (x86_pmu.guest_get_msrs)
|
|
|
|
|
return x86_pmu.guest_get_msrs(nr);
|
|
|
|
|
*nr = 0;
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
|
|
|
|
|
|
|
|
|
|
static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
|
|
|
|
|
{
|
x86: Replace __get_cpu_var uses
__get_cpu_var() is used for multiple purposes in the kernel source. One of
them is address calculation via the form &__get_cpu_var(x). This calculates
the address for the instance of the percpu variable of the current processor
based on an offset.
Other use cases are for storing and retrieving data from the current
processors percpu area. __get_cpu_var() can be used as an lvalue when
writing data or on the right side of an assignment.
__get_cpu_var() is defined as :
#define __get_cpu_var(var) (*this_cpu_ptr(&(var)))
__get_cpu_var() always only does an address determination. However, store
and retrieve operations could use a segment prefix (or global register on
other platforms) to avoid the address calculation.
this_cpu_write() and this_cpu_read() can directly take an offset into a
percpu area and use optimized assembly code to read and write per cpu
variables.
This patch converts __get_cpu_var into either an explicit address
calculation using this_cpu_ptr() or into a use of this_cpu operations that
use the offset. Thereby address calculations are avoided and less registers
are used when code is generated.
Transformations done to __get_cpu_var()
1. Determine the address of the percpu instance of the current processor.
DEFINE_PER_CPU(int, y);
int *x = &__get_cpu_var(y);
Converts to
int *x = this_cpu_ptr(&y);
2. Same as #1 but this time an array structure is involved.
DEFINE_PER_CPU(int, y[20]);
int *x = __get_cpu_var(y);
Converts to
int *x = this_cpu_ptr(y);
3. Retrieve the content of the current processors instance of a per cpu
variable.
DEFINE_PER_CPU(int, y);
int x = __get_cpu_var(y)
Converts to
int x = __this_cpu_read(y);
4. Retrieve the content of a percpu struct
DEFINE_PER_CPU(struct mystruct, y);
struct mystruct x = __get_cpu_var(y);
Converts to
memcpy(&x, this_cpu_ptr(&y), sizeof(x));
5. Assignment to a per cpu variable
DEFINE_PER_CPU(int, y)
__get_cpu_var(y) = x;
Converts to
__this_cpu_write(y, x);
6. Increment/Decrement etc of a per cpu variable
DEFINE_PER_CPU(int, y);
__get_cpu_var(y)++
Converts to
__this_cpu_inc(y)
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: x86@kernel.org
Acked-by: H. Peter Anvin <hpa@linux.intel.com>
Acked-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Christoph Lameter <cl@linux.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2014-08-17 17:30:40 +00:00
|
|
|
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
|
2011-10-05 12:01:21 +00:00
|
|
|
struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
|
|
|
|
|
|
|
|
|
|
arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
|
|
|
|
|
arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
|
|
|
|
|
arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
|
2012-08-09 08:52:34 +00:00
|
|
|
/*
|
|
|
|
|
* If PMU counter has PEBS enabled it is not enough to disable counter
|
|
|
|
|
* on a guest entry since PEBS memory write can overshoot guest entry
|
|
|
|
|
* and corrupt guest memory. Disabling PEBS solves the problem.
|
|
|
|
|
*/
|
|
|
|
|
arr[1].msr = MSR_IA32_PEBS_ENABLE;
|
|
|
|
|
arr[1].host = cpuc->pebs_enabled;
|
|
|
|
|
arr[1].guest = 0;
|
2011-10-05 12:01:21 +00:00
|
|
|
|
2012-08-09 08:52:34 +00:00
|
|
|
*nr = 2;
|
2011-10-05 12:01:21 +00:00
|
|
|
return arr;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
|
|
|
|
|
{
|
x86: Replace __get_cpu_var uses
__get_cpu_var() is used for multiple purposes in the kernel source. One of
them is address calculation via the form &__get_cpu_var(x). This calculates
the address for the instance of the percpu variable of the current processor
based on an offset.
Other use cases are for storing and retrieving data from the current
processors percpu area. __get_cpu_var() can be used as an lvalue when
writing data or on the right side of an assignment.
__get_cpu_var() is defined as :
#define __get_cpu_var(var) (*this_cpu_ptr(&(var)))
__get_cpu_var() always only does an address determination. However, store
and retrieve operations could use a segment prefix (or global register on
other platforms) to avoid the address calculation.
this_cpu_write() and this_cpu_read() can directly take an offset into a
percpu area and use optimized assembly code to read and write per cpu
variables.
This patch converts __get_cpu_var into either an explicit address
calculation using this_cpu_ptr() or into a use of this_cpu operations that
use the offset. Thereby address calculations are avoided and less registers
are used when code is generated.
Transformations done to __get_cpu_var()
1. Determine the address of the percpu instance of the current processor.
DEFINE_PER_CPU(int, y);
int *x = &__get_cpu_var(y);
Converts to
int *x = this_cpu_ptr(&y);
2. Same as #1 but this time an array structure is involved.
DEFINE_PER_CPU(int, y[20]);
int *x = __get_cpu_var(y);
Converts to
int *x = this_cpu_ptr(y);
3. Retrieve the content of the current processors instance of a per cpu
variable.
DEFINE_PER_CPU(int, y);
int x = __get_cpu_var(y)
Converts to
int x = __this_cpu_read(y);
4. Retrieve the content of a percpu struct
DEFINE_PER_CPU(struct mystruct, y);
struct mystruct x = __get_cpu_var(y);
Converts to
memcpy(&x, this_cpu_ptr(&y), sizeof(x));
5. Assignment to a per cpu variable
DEFINE_PER_CPU(int, y)
__get_cpu_var(y) = x;
Converts to
__this_cpu_write(y, x);
6. Increment/Decrement etc of a per cpu variable
DEFINE_PER_CPU(int, y);
__get_cpu_var(y)++
Converts to
__this_cpu_inc(y)
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: x86@kernel.org
Acked-by: H. Peter Anvin <hpa@linux.intel.com>
Acked-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Christoph Lameter <cl@linux.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2014-08-17 17:30:40 +00:00
|
|
|
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
|
2011-10-05 12:01:21 +00:00
|
|
|
struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
|
|
|
|
|
int idx;
|
|
|
|
|
|
|
|
|
|
for (idx = 0; idx < x86_pmu.num_counters; idx++) {
|
|
|
|
|
struct perf_event *event = cpuc->events[idx];
|
|
|
|
|
|
|
|
|
|
arr[idx].msr = x86_pmu_config_addr(idx);
|
|
|
|
|
arr[idx].host = arr[idx].guest = 0;
|
|
|
|
|
|
|
|
|
|
if (!test_bit(idx, cpuc->active_mask))
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
arr[idx].host = arr[idx].guest =
|
|
|
|
|
event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
|
|
|
|
|
|
|
|
|
|
if (event->attr.exclude_host)
|
|
|
|
|
arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
|
|
|
|
|
else if (event->attr.exclude_guest)
|
|
|
|
|
arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
*nr = x86_pmu.num_counters;
|
|
|
|
|
return arr;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void core_pmu_enable_event(struct perf_event *event)
|
|
|
|
|
{
|
|
|
|
|
if (!event->attr.exclude_host)
|
|
|
|
|
x86_pmu_enable_event(event);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void core_pmu_enable_all(int added)
|
|
|
|
|
{
|
x86: Replace __get_cpu_var uses
__get_cpu_var() is used for multiple purposes in the kernel source. One of
them is address calculation via the form &__get_cpu_var(x). This calculates
the address for the instance of the percpu variable of the current processor
based on an offset.
Other use cases are for storing and retrieving data from the current
processors percpu area. __get_cpu_var() can be used as an lvalue when
writing data or on the right side of an assignment.
__get_cpu_var() is defined as :
#define __get_cpu_var(var) (*this_cpu_ptr(&(var)))
__get_cpu_var() always only does an address determination. However, store
and retrieve operations could use a segment prefix (or global register on
other platforms) to avoid the address calculation.
this_cpu_write() and this_cpu_read() can directly take an offset into a
percpu area and use optimized assembly code to read and write per cpu
variables.
This patch converts __get_cpu_var into either an explicit address
calculation using this_cpu_ptr() or into a use of this_cpu operations that
use the offset. Thereby address calculations are avoided and less registers
are used when code is generated.
Transformations done to __get_cpu_var()
1. Determine the address of the percpu instance of the current processor.
DEFINE_PER_CPU(int, y);
int *x = &__get_cpu_var(y);
Converts to
int *x = this_cpu_ptr(&y);
2. Same as #1 but this time an array structure is involved.
DEFINE_PER_CPU(int, y[20]);
int *x = __get_cpu_var(y);
Converts to
int *x = this_cpu_ptr(y);
3. Retrieve the content of the current processors instance of a per cpu
variable.
DEFINE_PER_CPU(int, y);
int x = __get_cpu_var(y)
Converts to
int x = __this_cpu_read(y);
4. Retrieve the content of a percpu struct
DEFINE_PER_CPU(struct mystruct, y);
struct mystruct x = __get_cpu_var(y);
Converts to
memcpy(&x, this_cpu_ptr(&y), sizeof(x));
5. Assignment to a per cpu variable
DEFINE_PER_CPU(int, y)
__get_cpu_var(y) = x;
Converts to
__this_cpu_write(y, x);
6. Increment/Decrement etc of a per cpu variable
DEFINE_PER_CPU(int, y);
__get_cpu_var(y)++
Converts to
__this_cpu_inc(y)
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: x86@kernel.org
Acked-by: H. Peter Anvin <hpa@linux.intel.com>
Acked-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Christoph Lameter <cl@linux.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
2014-08-17 17:30:40 +00:00
|
|
|
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
|
2011-10-05 12:01:21 +00:00
|
|
|
int idx;
|
|
|
|
|
|
|
|
|
|
for (idx = 0; idx < x86_pmu.num_counters; idx++) {
|
|
|
|
|
struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
|
|
|
|
|
|
|
|
|
|
if (!test_bit(idx, cpuc->active_mask) ||
|
|
|
|
|
cpuc->events[idx]->attr.exclude_host)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
__x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2013-06-18 00:36:48 +00:00
|
|
|
static int hsw_hw_config(struct perf_event *event)
|
|
|
|
|
{
|
|
|
|
|
int ret = intel_pmu_hw_config(event);
|
|
|
|
|
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
|
|
|
|
|
return 0;
|
|
|
|
|
event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
|
|
|
|
|
* PEBS or in ANY thread mode. Since the results are non-sensical forbid
|
|
|
|
|
* this combination.
|
|
|
|
|
*/
|
|
|
|
|
if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
|
|
|
|
|
((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
|
|
|
|
|
event->attr.precise_ip > 0))
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
|
2013-09-06 03:37:38 +00:00
|
|
|
if (event_is_checkpointed(event)) {
|
|
|
|
|
/*
|
|
|
|
|
* Sampling of checkpointed events can cause situations where
|
|
|
|
|
* the CPU constantly aborts because of a overflow, which is
|
|
|
|
|
* then checkpointed back and ignored. Forbid checkpointing
|
|
|
|
|
* for sampling.
|
|
|
|
|
*
|
|
|
|
|
* But still allow a long sampling period, so that perf stat
|
|
|
|
|
* from KVM works.
|
|
|
|
|
*/
|
|
|
|
|
if (event->attr.sample_period > 0 &&
|
|
|
|
|
event->attr.sample_period < 0x7fffffff)
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
2013-06-18 00:36:48 +00:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct event_constraint counter2_constraint =
|
|
|
|
|
EVENT_CONSTRAINT(0, 0x4, 0);
|
|
|
|
|
|
|
|
|
|
static struct event_constraint *
|
|
|
|
|
hsw_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
|
|
|
|
|
{
|
|
|
|
|
struct event_constraint *c = intel_get_event_constraints(cpuc, event);
|
|
|
|
|
|
|
|
|
|
/* Handle special quirk on in_tx_checkpointed only in counter 2 */
|
|
|
|
|
if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
|
|
|
|
|
if (c->idxmsk64 & (1U << 2))
|
|
|
|
|
return &counter2_constraint;
|
|
|
|
|
return &emptyconstraint;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return c;
|
|
|
|
|
}
|
|
|
|
|
|
perf/x86/intel: Add INST_RETIRED.ALL workarounds
On Broadwell INST_RETIRED.ALL cannot be used with any period
that doesn't have the lowest 6 bits cleared. And the period
should not be smaller than 128.
This is erratum BDM11 and BDM55:
http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/5th-gen-core-family-spec-update.pdf
BDM11: When using a period < 100; we may get incorrect PEBS/PMI
interrupts and/or an invalid counter state.
BDM55: When bit0-5 of the period are !0 we may get redundant PEBS
records on overflow.
Add a new callback to enforce this, and set it for Broadwell.
How does this handle the case when an app requests a specific
period with some of the bottom bits set?
Short answer:
Any useful instruction sampling period needs to be 4-6 orders
of magnitude larger than 128, as an PMI every 128 instructions
would instantly overwhelm the system and be throttled.
So the +-64 error from this is really small compared to the
period, much smaller than normal system jitter.
Long answer (by Peterz):
IFF we guarantee perf_event_attr::sample_period >= 128.
Suppose we start out with sample_period=192; then we'll set period_left
to 192, we'll end up with left = 128 (we truncate the lower bits). We
get an interrupt, find that period_left = 64 (>0 so we return 0 and
don't get an overflow handler), up that to 128. Then we trigger again,
at n=256. Then we find period_left = -64 (<=0 so we return 1 and do get
an overflow). We increment with sample_period so we get left = 128. We
fire again, at n=384, period_left = 0 (<=0 so we return 1 and get an
overflow). And on and on.
So while the individual interrupts are 'wrong' we get then with
interval=256,128 in exactly the right ratio to average out at 192. And
this works for everything >=128.
So the num_samples*fixed_period thing is still entirely correct +- 127,
which is good enough I'd say, as you already have that error anyhow.
So no need to 'fix' the tools, al we need to do is refuse to create
INST_RETIRED:ALL events with sample_period < 128.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
[ Updated comments and changelog a bit. ]
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1424225886-18652-3-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-02-18 02:18:06 +00:00
|
|
|
/*
|
|
|
|
|
* Broadwell:
|
|
|
|
|
*
|
|
|
|
|
* The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
|
|
|
|
|
* (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
|
|
|
|
|
* the two to enforce a minimum period of 128 (the smallest value that has bits
|
|
|
|
|
* 0-5 cleared and >= 100).
|
|
|
|
|
*
|
|
|
|
|
* Because of how the code in x86_perf_event_set_period() works, the truncation
|
|
|
|
|
* of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
|
|
|
|
|
* to make up for the 'lost' events due to carrying the 'error' in period_left.
|
|
|
|
|
*
|
|
|
|
|
* Therefore the effective (average) period matches the requested period,
|
|
|
|
|
* despite coarser hardware granularity.
|
|
|
|
|
*/
|
|
|
|
|
static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
|
|
|
|
|
{
|
|
|
|
|
if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
|
|
|
|
|
X86_CONFIG(.event=0xc0, .umask=0x01)) {
|
|
|
|
|
if (left < 128)
|
|
|
|
|
left = 128;
|
|
|
|
|
left &= ~0x3fu;
|
|
|
|
|
}
|
|
|
|
|
return left;
|
|
|
|
|
}
|
|
|
|
|
|
2012-03-15 19:09:14 +00:00
|
|
|
PMU_FORMAT_ATTR(event, "config:0-7" );
|
|
|
|
|
PMU_FORMAT_ATTR(umask, "config:8-15" );
|
|
|
|
|
PMU_FORMAT_ATTR(edge, "config:18" );
|
|
|
|
|
PMU_FORMAT_ATTR(pc, "config:19" );
|
|
|
|
|
PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
|
|
|
|
|
PMU_FORMAT_ATTR(inv, "config:23" );
|
|
|
|
|
PMU_FORMAT_ATTR(cmask, "config:24-31" );
|
2013-06-18 00:36:48 +00:00
|
|
|
PMU_FORMAT_ATTR(in_tx, "config:32");
|
|
|
|
|
PMU_FORMAT_ATTR(in_tx_cp, "config:33");
|
2012-03-15 19:09:14 +00:00
|
|
|
|
|
|
|
|
static struct attribute *intel_arch_formats_attr[] = {
|
|
|
|
|
&format_attr_event.attr,
|
|
|
|
|
&format_attr_umask.attr,
|
|
|
|
|
&format_attr_edge.attr,
|
|
|
|
|
&format_attr_pc.attr,
|
|
|
|
|
&format_attr_inv.attr,
|
|
|
|
|
&format_attr_cmask.attr,
|
|
|
|
|
NULL,
|
|
|
|
|
};
|
|
|
|
|
|
2012-10-10 12:53:14 +00:00
|
|
|
ssize_t intel_event_sysfs_show(char *page, u64 config)
|
|
|
|
|
{
|
|
|
|
|
u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
|
|
|
|
|
|
|
|
|
|
return x86_event_sysfs_show(page, config, event);
|
|
|
|
|
}
|
|
|
|
|
|
2010-03-29 11:09:53 +00:00
|
|
|
static __initconst const struct x86_pmu core_pmu = {
|
2010-02-26 11:05:05 +00:00
|
|
|
.name = "core",
|
|
|
|
|
.handle_irq = x86_pmu_handle_irq,
|
|
|
|
|
.disable_all = x86_pmu_disable_all,
|
2011-10-05 12:01:21 +00:00
|
|
|
.enable_all = core_pmu_enable_all,
|
|
|
|
|
.enable = core_pmu_enable_event,
|
2010-02-26 11:05:05 +00:00
|
|
|
.disable = x86_pmu_disable_event,
|
2010-03-30 15:00:06 +00:00
|
|
|
.hw_config = x86_pmu_hw_config,
|
2010-03-11 16:54:39 +00:00
|
|
|
.schedule_events = x86_schedule_events,
|
2010-02-26 11:05:05 +00:00
|
|
|
.eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
|
|
|
|
|
.perfctr = MSR_ARCH_PERFMON_PERFCTR0,
|
|
|
|
|
.event_map = intel_pmu_event_map,
|
|
|
|
|
.max_events = ARRAY_SIZE(intel_perfmon_event_map),
|
|
|
|
|
.apic = 1,
|
|
|
|
|
/*
|
|
|
|
|
* Intel PMCs cannot be accessed sanely above 32 bit width,
|
|
|
|
|
* so we install an artificial 1<<31 period regardless of
|
|
|
|
|
* the generic event period:
|
|
|
|
|
*/
|
|
|
|
|
.max_period = (1ULL << 31) - 1,
|
|
|
|
|
.get_event_constraints = intel_get_event_constraints,
|
2011-03-03 02:34:47 +00:00
|
|
|
.put_event_constraints = intel_put_event_constraints,
|
2010-02-26 11:05:05 +00:00
|
|
|
.event_constraints = intel_core_event_constraints,
|
2011-10-05 12:01:21 +00:00
|
|
|
.guest_get_msrs = core_guest_get_msrs,
|
2012-03-15 19:09:14 +00:00
|
|
|
.format_attrs = intel_arch_formats_attr,
|
2012-10-10 12:53:14 +00:00
|
|
|
.events_sysfs_show = intel_event_sysfs_show,
|
2010-02-26 11:05:05 +00:00
|
|
|
};
|
|
|
|
|
|
2011-08-30 23:41:05 +00:00
|
|
|
struct intel_shared_regs *allocate_shared_regs(int cpu)
|
2011-06-06 14:57:03 +00:00
|
|
|
{
|
|
|
|
|
struct intel_shared_regs *regs;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
regs = kzalloc_node(sizeof(struct intel_shared_regs),
|
|
|
|
|
GFP_KERNEL, cpu_to_node(cpu));
|
|
|
|
|
if (regs) {
|
|
|
|
|
/*
|
|
|
|
|
* initialize the locks to keep lockdep happy
|
|
|
|
|
*/
|
|
|
|
|
for (i = 0; i < EXTRA_REG_MAX; i++)
|
|
|
|
|
raw_spin_lock_init(®s->regs[i].lock);
|
|
|
|
|
|
|
|
|
|
regs->core_id = -1;
|
|
|
|
|
}
|
|
|
|
|
return regs;
|
|
|
|
|
}
|
|
|
|
|
|
2011-03-03 02:34:47 +00:00
|
|
|
static int intel_pmu_cpu_prepare(int cpu)
|
|
|
|
|
{
|
|
|
|
|
struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
|
|
|
|
|
|
2012-02-09 22:20:53 +00:00
|
|
|
if (!(x86_pmu.extra_regs || x86_pmu.lbr_sel_map))
|
2011-03-03 02:34:50 +00:00
|
|
|
return NOTIFY_OK;
|
|
|
|
|
|
2011-06-06 14:57:03 +00:00
|
|
|
cpuc->shared_regs = allocate_shared_regs(cpu);
|
|
|
|
|
if (!cpuc->shared_regs)
|
2011-03-03 02:34:47 +00:00
|
|
|
return NOTIFY_BAD;
|
|
|
|
|
|
|
|
|
|
return NOTIFY_OK;
|
|
|
|
|
}
|
|
|
|
|
|
2010-03-05 12:49:35 +00:00
|
|
|
static void intel_pmu_cpu_starting(int cpu)
|
|
|
|
|
{
|
2011-03-03 02:34:47 +00:00
|
|
|
struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
|
|
|
|
|
int core_id = topology_core_id(cpu);
|
|
|
|
|
int i;
|
|
|
|
|
|
2011-03-03 02:34:50 +00:00
|
|
|
init_debug_store_on_cpu(cpu);
|
|
|
|
|
/*
|
|
|
|
|
* Deal with CPUs that don't clear their LBRs on power-up.
|
|
|
|
|
*/
|
|
|
|
|
intel_pmu_lbr_reset();
|
|
|
|
|
|
2012-02-09 22:20:53 +00:00
|
|
|
cpuc->lbr_sel = NULL;
|
|
|
|
|
|
|
|
|
|
if (!cpuc->shared_regs)
|
2011-03-03 02:34:50 +00:00
|
|
|
return;
|
|
|
|
|
|
2012-02-09 22:20:53 +00:00
|
|
|
if (!(x86_pmu.er_flags & ERF_NO_HT_SHARING)) {
|
|
|
|
|
for_each_cpu(i, topology_thread_cpumask(cpu)) {
|
|
|
|
|
struct intel_shared_regs *pc;
|
2011-03-03 02:34:47 +00:00
|
|
|
|
2012-02-09 22:20:53 +00:00
|
|
|
pc = per_cpu(cpu_hw_events, i).shared_regs;
|
|
|
|
|
if (pc && pc->core_id == core_id) {
|
|
|
|
|
cpuc->kfree_on_online = cpuc->shared_regs;
|
|
|
|
|
cpuc->shared_regs = pc;
|
|
|
|
|
break;
|
|
|
|
|
}
|
2011-03-03 02:34:47 +00:00
|
|
|
}
|
2012-02-09 22:20:53 +00:00
|
|
|
cpuc->shared_regs->core_id = core_id;
|
|
|
|
|
cpuc->shared_regs->refcnt++;
|
2011-03-03 02:34:47 +00:00
|
|
|
}
|
|
|
|
|
|
2012-02-09 22:20:53 +00:00
|
|
|
if (x86_pmu.lbr_sel_map)
|
|
|
|
|
cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
|
2010-03-05 12:49:35 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void intel_pmu_cpu_dying(int cpu)
|
|
|
|
|
{
|
2011-03-03 02:34:47 +00:00
|
|
|
struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
|
2011-06-06 14:57:03 +00:00
|
|
|
struct intel_shared_regs *pc;
|
2011-03-03 02:34:47 +00:00
|
|
|
|
2011-06-06 14:57:03 +00:00
|
|
|
pc = cpuc->shared_regs;
|
2011-03-03 02:34:47 +00:00
|
|
|
if (pc) {
|
|
|
|
|
if (pc->core_id == -1 || --pc->refcnt == 0)
|
|
|
|
|
kfree(pc);
|
2011-06-06 14:57:03 +00:00
|
|
|
cpuc->shared_regs = NULL;
|
2011-03-03 02:34:47 +00:00
|
|
|
}
|
|
|
|
|
|
2010-03-05 12:49:35 +00:00
|
|
|
fini_debug_store_on_cpu(cpu);
|
|
|
|
|
}
|
|
|
|
|
|
2012-03-15 19:09:14 +00:00
|
|
|
PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
|
|
|
|
|
|
2013-01-24 15:10:33 +00:00
|
|
|
PMU_FORMAT_ATTR(ldlat, "config1:0-15");
|
|
|
|
|
|
2012-03-15 19:09:14 +00:00
|
|
|
static struct attribute *intel_arch3_formats_attr[] = {
|
|
|
|
|
&format_attr_event.attr,
|
|
|
|
|
&format_attr_umask.attr,
|
|
|
|
|
&format_attr_edge.attr,
|
|
|
|
|
&format_attr_pc.attr,
|
|
|
|
|
&format_attr_any.attr,
|
|
|
|
|
&format_attr_inv.attr,
|
|
|
|
|
&format_attr_cmask.attr,
|
2013-06-18 00:36:48 +00:00
|
|
|
&format_attr_in_tx.attr,
|
|
|
|
|
&format_attr_in_tx_cp.attr,
|
2012-03-15 19:09:14 +00:00
|
|
|
|
|
|
|
|
&format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
|
2013-01-24 15:10:33 +00:00
|
|
|
&format_attr_ldlat.attr, /* PEBS load latency */
|
2012-03-15 19:09:14 +00:00
|
|
|
NULL,
|
|
|
|
|
};
|
|
|
|
|
|
2010-03-29 11:09:53 +00:00
|
|
|
static __initconst const struct x86_pmu intel_pmu = {
|
2010-02-26 11:05:05 +00:00
|
|
|
.name = "Intel",
|
|
|
|
|
.handle_irq = intel_pmu_handle_irq,
|
|
|
|
|
.disable_all = intel_pmu_disable_all,
|
|
|
|
|
.enable_all = intel_pmu_enable_all,
|
|
|
|
|
.enable = intel_pmu_enable_event,
|
|
|
|
|
.disable = intel_pmu_disable_event,
|
2010-03-30 15:00:06 +00:00
|
|
|
.hw_config = intel_pmu_hw_config,
|
2010-03-11 16:54:39 +00:00
|
|
|
.schedule_events = x86_schedule_events,
|
2010-02-26 11:05:05 +00:00
|
|
|
.eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
|
|
|
|
|
.perfctr = MSR_ARCH_PERFMON_PERFCTR0,
|
|
|
|
|
.event_map = intel_pmu_event_map,
|
|
|
|
|
.max_events = ARRAY_SIZE(intel_perfmon_event_map),
|
|
|
|
|
.apic = 1,
|
|
|
|
|
/*
|
|
|
|
|
* Intel PMCs cannot be accessed sanely above 32 bit width,
|
|
|
|
|
* so we install an artificial 1<<31 period regardless of
|
|
|
|
|
* the generic event period:
|
|
|
|
|
*/
|
|
|
|
|
.max_period = (1ULL << 31) - 1,
|
2010-03-05 12:01:18 +00:00
|
|
|
.get_event_constraints = intel_get_event_constraints,
|
2011-03-03 02:34:47 +00:00
|
|
|
.put_event_constraints = intel_put_event_constraints,
|
2012-06-05 08:26:43 +00:00
|
|
|
.pebs_aliases = intel_pebs_aliases_core2,
|
2010-03-05 12:01:18 +00:00
|
|
|
|
2012-03-15 19:09:14 +00:00
|
|
|
.format_attrs = intel_arch3_formats_attr,
|
2012-10-10 12:53:14 +00:00
|
|
|
.events_sysfs_show = intel_event_sysfs_show,
|
2012-03-15 19:09:14 +00:00
|
|
|
|
2011-03-03 02:34:47 +00:00
|
|
|
.cpu_prepare = intel_pmu_cpu_prepare,
|
2010-03-05 12:49:35 +00:00
|
|
|
.cpu_starting = intel_pmu_cpu_starting,
|
|
|
|
|
.cpu_dying = intel_pmu_cpu_dying,
|
2011-10-05 12:01:21 +00:00
|
|
|
.guest_get_msrs = intel_guest_get_msrs,
|
2014-11-05 02:55:59 +00:00
|
|
|
.sched_task = intel_pmu_lbr_sched_task,
|
2010-02-26 11:05:05 +00:00
|
|
|
};
|
|
|
|
|
|
2011-12-06 13:07:15 +00:00
|
|
|
static __init void intel_clovertown_quirk(void)
|
2010-03-04 20:49:01 +00:00
|
|
|
{
|
|
|
|
|
/*
|
|
|
|
|
* PEBS is unreliable due to:
|
|
|
|
|
*
|
|
|
|
|
* AJ67 - PEBS may experience CPL leaks
|
|
|
|
|
* AJ68 - PEBS PMI may be delayed by one event
|
|
|
|
|
* AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
|
|
|
|
|
* AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
|
|
|
|
|
*
|
|
|
|
|
* AJ67 could be worked around by restricting the OS/USR flags.
|
|
|
|
|
* AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
|
|
|
|
|
*
|
|
|
|
|
* AJ106 could possibly be worked around by not allowing LBR
|
|
|
|
|
* usage from PEBS, including the fixup.
|
|
|
|
|
* AJ68 could possibly be worked around by always programming
|
2011-04-27 09:51:41 +00:00
|
|
|
* a pebs_event_reset[0] value and coping with the lost events.
|
2010-03-04 20:49:01 +00:00
|
|
|
*
|
|
|
|
|
* But taken together it might just make sense to not enable PEBS on
|
|
|
|
|
* these chips.
|
|
|
|
|
*/
|
2012-05-22 02:50:07 +00:00
|
|
|
pr_warn("PEBS disabled due to CPU errata\n");
|
2010-03-04 20:49:01 +00:00
|
|
|
x86_pmu.pebs = 0;
|
|
|
|
|
x86_pmu.pebs_constraints = NULL;
|
|
|
|
|
}
|
|
|
|
|
|
2012-06-08 12:50:50 +00:00
|
|
|
static int intel_snb_pebs_broken(int cpu)
|
|
|
|
|
{
|
|
|
|
|
u32 rev = UINT_MAX; /* default to broken for unknown models */
|
|
|
|
|
|
|
|
|
|
switch (cpu_data(cpu).x86_model) {
|
|
|
|
|
case 42: /* SNB */
|
|
|
|
|
rev = 0x28;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 45: /* SNB-EP */
|
|
|
|
|
switch (cpu_data(cpu).x86_mask) {
|
|
|
|
|
case 6: rev = 0x618; break;
|
|
|
|
|
case 7: rev = 0x70c; break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return (cpu_data(cpu).microcode < rev);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void intel_snb_check_microcode(void)
|
|
|
|
|
{
|
|
|
|
|
int pebs_broken = 0;
|
|
|
|
|
int cpu;
|
|
|
|
|
|
|
|
|
|
get_online_cpus();
|
|
|
|
|
for_each_online_cpu(cpu) {
|
|
|
|
|
if ((pebs_broken = intel_snb_pebs_broken(cpu)))
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
put_online_cpus();
|
|
|
|
|
|
|
|
|
|
if (pebs_broken == x86_pmu.pebs_broken)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Serialized by the microcode lock..
|
|
|
|
|
*/
|
|
|
|
|
if (x86_pmu.pebs_broken) {
|
|
|
|
|
pr_info("PEBS enabled due to microcode update\n");
|
|
|
|
|
x86_pmu.pebs_broken = 0;
|
|
|
|
|
} else {
|
|
|
|
|
pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
|
|
|
|
|
x86_pmu.pebs_broken = 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2014-07-14 19:25:56 +00:00
|
|
|
/*
|
|
|
|
|
* Under certain circumstances, access certain MSR may cause #GP.
|
|
|
|
|
* The function tests if the input MSR can be safely accessed.
|
|
|
|
|
*/
|
|
|
|
|
static bool check_msr(unsigned long msr, u64 mask)
|
|
|
|
|
{
|
|
|
|
|
u64 val_old, val_new, val_tmp;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Read the current value, change it and read it back to see if it
|
|
|
|
|
* matches, this is needed to detect certain hardware emulators
|
|
|
|
|
* (qemu/kvm) that don't trap on the MSR access and always return 0s.
|
|
|
|
|
*/
|
|
|
|
|
if (rdmsrl_safe(msr, &val_old))
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Only change the bits which can be updated by wrmsrl.
|
|
|
|
|
*/
|
|
|
|
|
val_tmp = val_old ^ mask;
|
|
|
|
|
if (wrmsrl_safe(msr, val_tmp) ||
|
|
|
|
|
rdmsrl_safe(msr, &val_new))
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
if (val_new != val_tmp)
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
/* Here it's sure that the MSR can be safely accessed.
|
|
|
|
|
* Restore the old value and return.
|
|
|
|
|
*/
|
|
|
|
|
wrmsrl(msr, val_old);
|
|
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
2011-12-06 13:07:15 +00:00
|
|
|
static __init void intel_sandybridge_quirk(void)
|
2011-11-15 09:51:15 +00:00
|
|
|
{
|
2012-06-08 12:50:50 +00:00
|
|
|
x86_pmu.check_microcode = intel_snb_check_microcode;
|
|
|
|
|
intel_snb_check_microcode();
|
2011-11-15 09:51:15 +00:00
|
|
|
}
|
|
|
|
|
|
2011-12-06 13:07:15 +00:00
|
|
|
static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
|
|
|
|
|
{ PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
|
|
|
|
|
{ PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
|
|
|
|
|
{ PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
|
|
|
|
|
{ PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
|
|
|
|
|
{ PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
|
|
|
|
|
{ PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
|
|
|
|
|
{ PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
|
2011-11-10 12:57:26 +00:00
|
|
|
};
|
|
|
|
|
|
2011-12-06 13:07:15 +00:00
|
|
|
static __init void intel_arch_events_quirk(void)
|
|
|
|
|
{
|
|
|
|
|
int bit;
|
|
|
|
|
|
|
|
|
|
/* disable event that reported as not presend by cpuid */
|
|
|
|
|
for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
|
|
|
|
|
intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
|
2012-05-22 02:50:07 +00:00
|
|
|
pr_warn("CPUID marked event: \'%s\' unavailable\n",
|
|
|
|
|
intel_arch_events_map[bit].name);
|
2011-12-06 13:07:15 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __init void intel_nehalem_quirk(void)
|
|
|
|
|
{
|
|
|
|
|
union cpuid10_ebx ebx;
|
|
|
|
|
|
|
|
|
|
ebx.full = x86_pmu.events_maskl;
|
|
|
|
|
if (ebx.split.no_branch_misses_retired) {
|
|
|
|
|
/*
|
|
|
|
|
* Erratum AAJ80 detected, we work it around by using
|
|
|
|
|
* the BR_MISP_EXEC.ANY event. This will over-count
|
|
|
|
|
* branch-misses, but it's still much better than the
|
|
|
|
|
* architectural event which is often completely bogus:
|
|
|
|
|
*/
|
|
|
|
|
intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
|
|
|
|
|
ebx.split.no_branch_misses_retired = 0;
|
|
|
|
|
x86_pmu.events_maskl = ebx.full;
|
2012-05-22 02:50:07 +00:00
|
|
|
pr_info("CPU erratum AAJ80 worked around\n");
|
2011-12-06 13:07:15 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2013-09-12 17:17:00 +00:00
|
|
|
EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
|
|
|
|
|
EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
|
2013-06-18 00:36:52 +00:00
|
|
|
|
2013-09-06 03:37:40 +00:00
|
|
|
/* Haswell special events */
|
2013-09-12 17:17:00 +00:00
|
|
|
EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
|
|
|
|
|
EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
|
|
|
|
|
EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
|
|
|
|
|
EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
|
|
|
|
|
EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
|
|
|
|
|
EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
|
|
|
|
|
EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
|
|
|
|
|
EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
|
|
|
|
|
EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
|
|
|
|
|
EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
|
|
|
|
|
EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
|
|
|
|
|
EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
|
2013-09-06 03:37:40 +00:00
|
|
|
|
2013-06-18 00:36:52 +00:00
|
|
|
static struct attribute *hsw_events_attrs[] = {
|
2013-09-06 03:37:40 +00:00
|
|
|
EVENT_PTR(tx_start),
|
|
|
|
|
EVENT_PTR(tx_commit),
|
|
|
|
|
EVENT_PTR(tx_abort),
|
|
|
|
|
EVENT_PTR(tx_capacity),
|
|
|
|
|
EVENT_PTR(tx_conflict),
|
|
|
|
|
EVENT_PTR(el_start),
|
|
|
|
|
EVENT_PTR(el_commit),
|
|
|
|
|
EVENT_PTR(el_abort),
|
|
|
|
|
EVENT_PTR(el_capacity),
|
|
|
|
|
EVENT_PTR(el_conflict),
|
|
|
|
|
EVENT_PTR(cycles_t),
|
|
|
|
|
EVENT_PTR(cycles_ct),
|
2013-06-18 00:36:52 +00:00
|
|
|
EVENT_PTR(mem_ld_hsw),
|
|
|
|
|
EVENT_PTR(mem_st_hsw),
|
|
|
|
|
NULL
|
|
|
|
|
};
|
|
|
|
|
|
2011-08-30 23:41:05 +00:00
|
|
|
__init int intel_pmu_init(void)
|
2010-02-26 11:05:05 +00:00
|
|
|
{
|
|
|
|
|
union cpuid10_edx edx;
|
|
|
|
|
union cpuid10_eax eax;
|
2011-11-10 12:57:26 +00:00
|
|
|
union cpuid10_ebx ebx;
|
2012-06-20 18:46:34 +00:00
|
|
|
struct event_constraint *c;
|
2010-02-26 11:05:05 +00:00
|
|
|
unsigned int unused;
|
2014-07-14 19:25:56 +00:00
|
|
|
struct extra_reg *er;
|
|
|
|
|
int version, i;
|
2010-02-26 11:05:05 +00:00
|
|
|
|
|
|
|
|
if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
|
2010-03-11 16:54:39 +00:00
|
|
|
switch (boot_cpu_data.x86) {
|
|
|
|
|
case 0x6:
|
|
|
|
|
return p6_pmu_init();
|
2012-09-26 18:12:52 +00:00
|
|
|
case 0xb:
|
|
|
|
|
return knc_pmu_init();
|
2010-03-11 16:54:39 +00:00
|
|
|
case 0xf:
|
|
|
|
|
return p4_pmu_init();
|
|
|
|
|
}
|
2010-02-26 11:05:05 +00:00
|
|
|
return -ENODEV;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Check whether the Architectural PerfMon supports
|
|
|
|
|
* Branch Misses Retired hw_event or not.
|
|
|
|
|
*/
|
2011-11-10 12:57:26 +00:00
|
|
|
cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
|
|
|
|
|
if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
|
2010-02-26 11:05:05 +00:00
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
|
|
version = eax.split.version_id;
|
|
|
|
|
if (version < 2)
|
|
|
|
|
x86_pmu = core_pmu;
|
|
|
|
|
else
|
|
|
|
|
x86_pmu = intel_pmu;
|
|
|
|
|
|
|
|
|
|
x86_pmu.version = version;
|
2010-03-29 16:36:50 +00:00
|
|
|
x86_pmu.num_counters = eax.split.num_counters;
|
|
|
|
|
x86_pmu.cntval_bits = eax.split.bit_width;
|
|
|
|
|
x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
|
2010-02-26 11:05:05 +00:00
|
|
|
|
2011-12-06 13:07:15 +00:00
|
|
|
x86_pmu.events_maskl = ebx.full;
|
|
|
|
|
x86_pmu.events_mask_len = eax.split.mask_length;
|
|
|
|
|
|
2012-06-06 00:56:48 +00:00
|
|
|
x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
|
|
|
|
|
|
2010-02-26 11:05:05 +00:00
|
|
|
/*
|
|
|
|
|
* Quirk: v2 perfmon does not report fixed-purpose events, so
|
|
|
|
|
* assume at least 3 events:
|
|
|
|
|
*/
|
|
|
|
|
if (version > 1)
|
2010-03-29 16:36:50 +00:00
|
|
|
x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
|
2010-02-26 11:05:05 +00:00
|
|
|
|
2014-02-03 13:29:03 +00:00
|
|
|
if (boot_cpu_has(X86_FEATURE_PDCM)) {
|
2010-03-03 16:07:40 +00:00
|
|
|
u64 capabilities;
|
|
|
|
|
|
|
|
|
|
rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
|
|
|
|
|
x86_pmu.intel_cap.capabilities = capabilities;
|
|
|
|
|
}
|
|
|
|
|
|
perf, x86: Add PEBS infrastructure
This patch implements support for Intel Precise Event Based Sampling,
which is an alternative counter mode in which the counter triggers a
hardware assist to collect information on events. The hardware assist
takes a trap like snapshot of a subset of the machine registers.
This data is written to the Intel Debug-Store, which can be programmed
with a data threshold at which to raise a PMI.
With the PEBS hardware assist being trap like, the reported IP is always
one instruction after the actual instruction that triggered the event.
This implements a simple PEBS model that always takes a single PEBS event
at a time. This is done so that the interaction with the rest of the
system is as expected (freq adjust, period randomization, lbr,
callchains, etc.).
It adds an ABI element: perf_event_attr::precise, which indicates that we
wish to use this (constrained, but precise) mode.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100304140100.392111285@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-03-02 18:52:12 +00:00
|
|
|
intel_ds_init();
|
|
|
|
|
|
2011-12-06 13:07:15 +00:00
|
|
|
x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
|
|
|
|
|
|
2010-02-26 11:05:05 +00:00
|
|
|
/*
|
|
|
|
|
* Install the hw-cache-events table:
|
|
|
|
|
*/
|
|
|
|
|
switch (boot_cpu_data.x86_model) {
|
2014-07-30 10:08:56 +00:00
|
|
|
case 14: /* 65nm Core "Yonah" */
|
2010-02-26 11:05:05 +00:00
|
|
|
pr_cont("Core events, ");
|
|
|
|
|
break;
|
|
|
|
|
|
2014-07-30 10:08:56 +00:00
|
|
|
case 15: /* 65nm Core2 "Merom" */
|
2011-12-06 13:07:15 +00:00
|
|
|
x86_add_quirk(intel_clovertown_quirk);
|
2014-07-30 10:08:56 +00:00
|
|
|
case 22: /* 65nm Core2 "Merom-L" */
|
|
|
|
|
case 23: /* 45nm Core2 "Penryn" */
|
|
|
|
|
case 29: /* 45nm Core2 "Dunnington (MP) */
|
2010-02-26 11:05:05 +00:00
|
|
|
memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
|
|
|
|
|
sizeof(hw_cache_event_ids));
|
|
|
|
|
|
2010-03-03 11:02:30 +00:00
|
|
|
intel_pmu_lbr_init_core();
|
|
|
|
|
|
2010-02-26 11:05:05 +00:00
|
|
|
x86_pmu.event_constraints = intel_core2_event_constraints;
|
2011-03-02 15:05:01 +00:00
|
|
|
x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
|
2010-02-26 11:05:05 +00:00
|
|
|
pr_cont("Core2 events, ");
|
|
|
|
|
break;
|
|
|
|
|
|
2014-07-30 10:08:56 +00:00
|
|
|
case 30: /* 45nm Nehalem */
|
|
|
|
|
case 26: /* 45nm Nehalem-EP */
|
|
|
|
|
case 46: /* 45nm Nehalem-EX */
|
2010-02-26 11:05:05 +00:00
|
|
|
memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
|
|
|
|
|
sizeof(hw_cache_event_ids));
|
2011-03-03 02:34:48 +00:00
|
|
|
memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
|
|
|
|
|
sizeof(hw_cache_extra_regs));
|
2010-02-26 11:05:05 +00:00
|
|
|
|
2010-03-03 11:02:30 +00:00
|
|
|
intel_pmu_lbr_init_nhm();
|
|
|
|
|
|
2010-02-26 11:05:05 +00:00
|
|
|
x86_pmu.event_constraints = intel_nehalem_event_constraints;
|
2011-03-02 15:05:01 +00:00
|
|
|
x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
|
2010-03-26 13:08:44 +00:00
|
|
|
x86_pmu.enable_all = intel_pmu_nhm_enable_all;
|
2011-03-03 02:34:47 +00:00
|
|
|
x86_pmu.extra_regs = intel_nehalem_extra_regs;
|
2011-04-27 09:51:41 +00:00
|
|
|
|
2013-01-24 15:10:32 +00:00
|
|
|
x86_pmu.cpu_events = nhm_events_attrs;
|
|
|
|
|
|
2011-04-29 12:17:19 +00:00
|
|
|
/* UOPS_ISSUED.STALLED_CYCLES */
|
2012-03-12 11:44:35 +00:00
|
|
|
intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
|
|
|
|
|
X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
|
2011-04-29 12:17:19 +00:00
|
|
|
/* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
|
2012-03-12 11:44:35 +00:00
|
|
|
intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
|
|
|
|
|
X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
|
2011-04-24 06:18:31 +00:00
|
|
|
|
2011-12-06 13:07:15 +00:00
|
|
|
x86_add_quirk(intel_nehalem_quirk);
|
2011-04-27 09:51:41 +00:00
|
|
|
|
2010-03-26 13:08:44 +00:00
|
|
|
pr_cont("Nehalem events, ");
|
2010-02-26 11:05:05 +00:00
|
|
|
break;
|
2010-03-03 11:02:30 +00:00
|
|
|
|
2014-07-30 10:08:56 +00:00
|
|
|
case 28: /* 45nm Atom "Pineview" */
|
|
|
|
|
case 38: /* 45nm Atom "Lincroft" */
|
|
|
|
|
case 39: /* 32nm Atom "Penwell" */
|
|
|
|
|
case 53: /* 32nm Atom "Cloverview" */
|
|
|
|
|
case 54: /* 32nm Atom "Cedarview" */
|
2010-02-26 11:05:05 +00:00
|
|
|
memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
|
|
|
|
|
sizeof(hw_cache_event_ids));
|
|
|
|
|
|
2010-03-03 11:02:30 +00:00
|
|
|
intel_pmu_lbr_init_atom();
|
|
|
|
|
|
2010-02-26 11:05:05 +00:00
|
|
|
x86_pmu.event_constraints = intel_gen_event_constraints;
|
2011-03-02 15:05:01 +00:00
|
|
|
x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
|
2010-02-26 11:05:05 +00:00
|
|
|
pr_cont("Atom events, ");
|
|
|
|
|
break;
|
|
|
|
|
|
2014-07-30 10:08:56 +00:00
|
|
|
case 55: /* 22nm Atom "Silvermont" */
|
2015-01-22 07:50:53 +00:00
|
|
|
case 76: /* 14nm Atom "Airmont" */
|
2014-07-30 10:08:56 +00:00
|
|
|
case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
|
2013-07-18 09:02:24 +00:00
|
|
|
memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
|
|
|
|
|
sizeof(hw_cache_event_ids));
|
|
|
|
|
memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
|
|
|
|
|
sizeof(hw_cache_extra_regs));
|
|
|
|
|
|
|
|
|
|
intel_pmu_lbr_init_atom();
|
|
|
|
|
|
|
|
|
|
x86_pmu.event_constraints = intel_slm_event_constraints;
|
|
|
|
|
x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
|
|
|
|
|
x86_pmu.extra_regs = intel_slm_extra_regs;
|
|
|
|
|
x86_pmu.er_flags |= ERF_HAS_RSP_1;
|
|
|
|
|
pr_cont("Silvermont events, ");
|
|
|
|
|
break;
|
|
|
|
|
|
2014-07-30 10:08:56 +00:00
|
|
|
case 37: /* 32nm Westmere */
|
|
|
|
|
case 44: /* 32nm Westmere-EP */
|
|
|
|
|
case 47: /* 32nm Westmere-EX */
|
2010-02-26 11:05:05 +00:00
|
|
|
memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
|
|
|
|
|
sizeof(hw_cache_event_ids));
|
2011-03-03 02:34:48 +00:00
|
|
|
memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
|
|
|
|
|
sizeof(hw_cache_extra_regs));
|
2010-02-26 11:05:05 +00:00
|
|
|
|
2010-03-03 11:02:30 +00:00
|
|
|
intel_pmu_lbr_init_nhm();
|
|
|
|
|
|
2010-02-26 11:05:05 +00:00
|
|
|
x86_pmu.event_constraints = intel_westmere_event_constraints;
|
2010-03-29 14:37:17 +00:00
|
|
|
x86_pmu.enable_all = intel_pmu_nhm_enable_all;
|
2011-03-02 15:05:01 +00:00
|
|
|
x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
|
2011-03-03 02:34:47 +00:00
|
|
|
x86_pmu.extra_regs = intel_westmere_extra_regs;
|
2011-05-23 09:08:15 +00:00
|
|
|
x86_pmu.er_flags |= ERF_HAS_RSP_1;
|
2011-04-30 07:14:54 +00:00
|
|
|
|
2013-01-24 15:10:32 +00:00
|
|
|
x86_pmu.cpu_events = nhm_events_attrs;
|
|
|
|
|
|
2011-04-30 07:14:54 +00:00
|
|
|
/* UOPS_ISSUED.STALLED_CYCLES */
|
2012-03-12 11:44:35 +00:00
|
|
|
intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
|
|
|
|
|
X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
|
2011-04-30 07:14:54 +00:00
|
|
|
/* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
|
2012-03-12 11:44:35 +00:00
|
|
|
intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
|
|
|
|
|
X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
|
2011-04-30 07:14:54 +00:00
|
|
|
|
2010-02-26 11:05:05 +00:00
|
|
|
pr_cont("Westmere events, ");
|
|
|
|
|
break;
|
2010-02-01 14:36:30 +00:00
|
|
|
|
2014-07-30 10:08:56 +00:00
|
|
|
case 42: /* 32nm SandyBridge */
|
|
|
|
|
case 45: /* 32nm SandyBridge-E/EN/EP */
|
2012-06-05 08:26:43 +00:00
|
|
|
x86_add_quirk(intel_sandybridge_quirk);
|
2011-03-02 13:27:04 +00:00
|
|
|
memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
|
|
|
|
|
sizeof(hw_cache_event_ids));
|
2012-07-17 09:27:55 +00:00
|
|
|
memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
|
|
|
|
|
sizeof(hw_cache_extra_regs));
|
2011-03-02 13:27:04 +00:00
|
|
|
|
2012-02-09 22:20:55 +00:00
|
|
|
intel_pmu_lbr_init_snb();
|
2011-03-02 13:27:04 +00:00
|
|
|
|
|
|
|
|
x86_pmu.event_constraints = intel_snb_event_constraints;
|
2011-08-30 23:41:05 +00:00
|
|
|
x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
|
2012-06-05 08:26:43 +00:00
|
|
|
x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
|
2013-04-16 11:51:43 +00:00
|
|
|
if (boot_cpu_data.x86_model == 45)
|
|
|
|
|
x86_pmu.extra_regs = intel_snbep_extra_regs;
|
|
|
|
|
else
|
|
|
|
|
x86_pmu.extra_regs = intel_snb_extra_regs;
|
2011-06-06 14:57:12 +00:00
|
|
|
/* all extra regs are per-cpu when HT is on */
|
2011-05-23 09:08:15 +00:00
|
|
|
x86_pmu.er_flags |= ERF_HAS_RSP_1;
|
|
|
|
|
x86_pmu.er_flags |= ERF_NO_HT_SHARING;
|
2011-05-06 07:14:02 +00:00
|
|
|
|
2013-01-24 15:10:32 +00:00
|
|
|
x86_pmu.cpu_events = snb_events_attrs;
|
|
|
|
|
|
2011-05-06 07:14:02 +00:00
|
|
|
/* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
|
2012-03-12 11:44:35 +00:00
|
|
|
intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
|
|
|
|
|
X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
|
2011-05-06 07:14:02 +00:00
|
|
|
/* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
|
2012-03-12 11:44:35 +00:00
|
|
|
intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
|
|
|
|
|
X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
|
2011-05-06 07:14:02 +00:00
|
|
|
|
2011-03-02 13:27:04 +00:00
|
|
|
pr_cont("SandyBridge events, ");
|
|
|
|
|
break;
|
2014-07-30 10:08:56 +00:00
|
|
|
|
|
|
|
|
case 58: /* 22nm IvyBridge */
|
|
|
|
|
case 62: /* 22nm IvyBridge-EP/EX */
|
2012-09-10 23:07:01 +00:00
|
|
|
memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
|
|
|
|
|
sizeof(hw_cache_event_ids));
|
2014-07-14 19:33:25 +00:00
|
|
|
/* dTLB-load-misses on IVB is different than SNB */
|
|
|
|
|
hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
|
|
|
|
|
|
2012-09-10 23:07:01 +00:00
|
|
|
memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
|
|
|
|
|
sizeof(hw_cache_extra_regs));
|
|
|
|
|
|
|
|
|
|
intel_pmu_lbr_init_snb();
|
|
|
|
|
|
2013-02-20 10:15:12 +00:00
|
|
|
x86_pmu.event_constraints = intel_ivb_event_constraints;
|
2012-09-10 23:07:01 +00:00
|
|
|
x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
|
|
|
|
|
x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
|
2013-04-16 11:51:43 +00:00
|
|
|
if (boot_cpu_data.x86_model == 62)
|
|
|
|
|
x86_pmu.extra_regs = intel_snbep_extra_regs;
|
|
|
|
|
else
|
|
|
|
|
x86_pmu.extra_regs = intel_snb_extra_regs;
|
2012-09-10 23:07:01 +00:00
|
|
|
/* all extra regs are per-cpu when HT is on */
|
|
|
|
|
x86_pmu.er_flags |= ERF_HAS_RSP_1;
|
|
|
|
|
x86_pmu.er_flags |= ERF_NO_HT_SHARING;
|
|
|
|
|
|
2013-01-24 15:10:32 +00:00
|
|
|
x86_pmu.cpu_events = snb_events_attrs;
|
|
|
|
|
|
2012-09-10 23:07:01 +00:00
|
|
|
/* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
|
|
|
|
|
intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
|
|
|
|
|
X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
|
|
|
|
|
|
|
|
|
|
pr_cont("IvyBridge events, ");
|
|
|
|
|
break;
|
|
|
|
|
|
2011-03-02 13:27:04 +00:00
|
|
|
|
2014-09-02 18:44:12 +00:00
|
|
|
case 60: /* 22nm Haswell Core */
|
|
|
|
|
case 63: /* 22nm Haswell Server */
|
|
|
|
|
case 69: /* 22nm Haswell ULT */
|
|
|
|
|
case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
|
2013-06-18 00:36:50 +00:00
|
|
|
x86_pmu.late_ack = true;
|
2015-02-18 02:18:04 +00:00
|
|
|
memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
|
|
|
|
|
memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
|
2013-06-18 00:36:48 +00:00
|
|
|
|
perf/x86/intel: Add basic Haswell LBR call stack support
Haswell has a new feature that utilizes the existing LBR facility to
record call chains. To enable this feature, bits (JCC, NEAR_IND_JMP,
NEAR_REL_JMP, FAR_BRANCH, EN_CALLSTACK) in LBR_SELECT must be set to 1,
bits (NEAR_REL_CALL, NEAR-IND_CALL, NEAR_RET) must be cleared. Due to
a hardware bug of Haswell, this feature doesn't work well with
FREEZE_LBRS_ON_PMI.
When the call stack feature is enabled, the LBR stack will capture
unfiltered call data normally, but as return instructions are executed,
the last captured branch record is flushed from the on-chip registers
in a last-in first-out (LIFO) manner. Thus, branch information relative
to leaf functions will not be captured, while preserving the call stack
information of the main line execution path.
This patch defines a separate lbr_sel map for Haswell. The map contains
a new entry for the call stack feature.
Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com>
Signed-off-by: Kan Liang <kan.liang@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: eranian@google.com
Cc: jolsa@redhat.com
Link: http://lkml.kernel.org/r/1415156173-10035-5-git-send-email-kan.liang@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2014-11-05 02:56:00 +00:00
|
|
|
intel_pmu_lbr_init_hsw();
|
2013-06-18 00:36:48 +00:00
|
|
|
|
|
|
|
|
x86_pmu.event_constraints = intel_hsw_event_constraints;
|
2013-06-18 00:36:49 +00:00
|
|
|
x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
|
2014-07-31 21:05:22 +00:00
|
|
|
x86_pmu.extra_regs = intel_snbep_extra_regs;
|
2013-06-18 00:36:49 +00:00
|
|
|
x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
|
2013-06-18 00:36:48 +00:00
|
|
|
/* all extra regs are per-cpu when HT is on */
|
|
|
|
|
x86_pmu.er_flags |= ERF_HAS_RSP_1;
|
|
|
|
|
x86_pmu.er_flags |= ERF_NO_HT_SHARING;
|
|
|
|
|
|
|
|
|
|
x86_pmu.hw_config = hsw_hw_config;
|
|
|
|
|
x86_pmu.get_event_constraints = hsw_get_event_constraints;
|
2013-06-18 00:36:52 +00:00
|
|
|
x86_pmu.cpu_events = hsw_events_attrs;
|
2013-09-20 14:40:44 +00:00
|
|
|
x86_pmu.lbr_double_abort = true;
|
2013-06-18 00:36:48 +00:00
|
|
|
pr_cont("Haswell events, ");
|
|
|
|
|
break;
|
|
|
|
|
|
2015-02-18 02:18:05 +00:00
|
|
|
case 61: /* 14nm Broadwell Core-M */
|
|
|
|
|
case 86: /* 14nm Broadwell Xeon D */
|
|
|
|
|
x86_pmu.late_ack = true;
|
|
|
|
|
memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
|
|
|
|
|
memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
|
|
|
|
|
|
|
|
|
|
/* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
|
|
|
|
|
hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
|
|
|
|
|
BDW_L3_MISS|HSW_SNOOP_DRAM;
|
|
|
|
|
hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
|
|
|
|
|
HSW_SNOOP_DRAM;
|
|
|
|
|
hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
|
|
|
|
|
BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
|
|
|
|
|
hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
|
|
|
|
|
BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
|
|
|
|
|
|
|
|
|
|
intel_pmu_lbr_init_snb();
|
|
|
|
|
|
|
|
|
|
x86_pmu.event_constraints = intel_bdw_event_constraints;
|
|
|
|
|
x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
|
|
|
|
|
x86_pmu.extra_regs = intel_snbep_extra_regs;
|
|
|
|
|
x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
|
|
|
|
|
/* all extra regs are per-cpu when HT is on */
|
|
|
|
|
x86_pmu.er_flags |= ERF_HAS_RSP_1;
|
|
|
|
|
x86_pmu.er_flags |= ERF_NO_HT_SHARING;
|
|
|
|
|
|
|
|
|
|
x86_pmu.hw_config = hsw_hw_config;
|
|
|
|
|
x86_pmu.get_event_constraints = hsw_get_event_constraints;
|
|
|
|
|
x86_pmu.cpu_events = hsw_events_attrs;
|
perf/x86/intel: Add INST_RETIRED.ALL workarounds
On Broadwell INST_RETIRED.ALL cannot be used with any period
that doesn't have the lowest 6 bits cleared. And the period
should not be smaller than 128.
This is erratum BDM11 and BDM55:
http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/5th-gen-core-family-spec-update.pdf
BDM11: When using a period < 100; we may get incorrect PEBS/PMI
interrupts and/or an invalid counter state.
BDM55: When bit0-5 of the period are !0 we may get redundant PEBS
records on overflow.
Add a new callback to enforce this, and set it for Broadwell.
How does this handle the case when an app requests a specific
period with some of the bottom bits set?
Short answer:
Any useful instruction sampling period needs to be 4-6 orders
of magnitude larger than 128, as an PMI every 128 instructions
would instantly overwhelm the system and be throttled.
So the +-64 error from this is really small compared to the
period, much smaller than normal system jitter.
Long answer (by Peterz):
IFF we guarantee perf_event_attr::sample_period >= 128.
Suppose we start out with sample_period=192; then we'll set period_left
to 192, we'll end up with left = 128 (we truncate the lower bits). We
get an interrupt, find that period_left = 64 (>0 so we return 0 and
don't get an overflow handler), up that to 128. Then we trigger again,
at n=256. Then we find period_left = -64 (<=0 so we return 1 and do get
an overflow). We increment with sample_period so we get left = 128. We
fire again, at n=384, period_left = 0 (<=0 so we return 1 and get an
overflow). And on and on.
So while the individual interrupts are 'wrong' we get then with
interval=256,128 in exactly the right ratio to average out at 192. And
this works for everything >=128.
So the num_samples*fixed_period thing is still entirely correct +- 127,
which is good enough I'd say, as you already have that error anyhow.
So no need to 'fix' the tools, al we need to do is refuse to create
INST_RETIRED:ALL events with sample_period < 128.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
[ Updated comments and changelog a bit. ]
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1424225886-18652-3-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-02-18 02:18:06 +00:00
|
|
|
x86_pmu.limit_period = bdw_limit_period;
|
2015-02-18 02:18:05 +00:00
|
|
|
pr_cont("Broadwell events, ");
|
|
|
|
|
break;
|
|
|
|
|
|
2010-02-26 11:05:05 +00:00
|
|
|
default:
|
2011-06-29 15:42:36 +00:00
|
|
|
switch (x86_pmu.version) {
|
|
|
|
|
case 1:
|
|
|
|
|
x86_pmu.event_constraints = intel_v1_event_constraints;
|
|
|
|
|
pr_cont("generic architected perfmon v1, ");
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
/*
|
|
|
|
|
* default constraints for v2 and up
|
|
|
|
|
*/
|
|
|
|
|
x86_pmu.event_constraints = intel_gen_event_constraints;
|
|
|
|
|
pr_cont("generic architected perfmon, ");
|
|
|
|
|
break;
|
|
|
|
|
}
|
2010-02-26 11:05:05 +00:00
|
|
|
}
|
2011-11-10 12:57:26 +00:00
|
|
|
|
2012-06-20 18:46:34 +00:00
|
|
|
if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
|
|
|
|
|
WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
|
|
|
|
|
x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
|
|
|
|
|
x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
|
|
|
|
|
}
|
|
|
|
|
x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
|
|
|
|
|
|
|
|
|
|
if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
|
|
|
|
|
WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
|
|
|
|
|
x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
|
|
|
|
|
x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
x86_pmu.intel_ctrl |=
|
|
|
|
|
((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
|
|
|
|
|
|
|
|
|
|
if (x86_pmu.event_constraints) {
|
|
|
|
|
/*
|
|
|
|
|
* event on fixed counter2 (REF_CYCLES) only works on this
|
|
|
|
|
* counter, so do not extend mask to generic counters
|
|
|
|
|
*/
|
|
|
|
|
for_each_event_constraint(c, x86_pmu.event_constraints) {
|
2013-06-18 00:36:48 +00:00
|
|
|
if (c->cmask != FIXED_EVENT_FLAGS
|
2012-06-20 18:46:34 +00:00
|
|
|
|| c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
|
|
|
|
|
c->weight += x86_pmu.num_counters;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2014-07-14 19:25:56 +00:00
|
|
|
/*
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|
|
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|
* Access LBR MSR may cause #GP under certain circumstances.
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|
|
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|
* E.g. KVM doesn't support LBR MSR
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|
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|
* Check all LBT MSR here.
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|
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* Disable LBR access if any LBR MSRs can not be accessed.
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|
|
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*/
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|
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if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
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x86_pmu.lbr_nr = 0;
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for (i = 0; i < x86_pmu.lbr_nr; i++) {
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|
if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
|
|
|
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|
check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
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|
x86_pmu.lbr_nr = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Access extra MSR may cause #GP under certain circumstances.
|
|
|
|
|
* E.g. KVM doesn't support offcore event
|
|
|
|
|
* Check all extra_regs here.
|
|
|
|
|
*/
|
|
|
|
|
if (x86_pmu.extra_regs) {
|
|
|
|
|
for (er = x86_pmu.extra_regs; er->msr; er++) {
|
|
|
|
|
er->extra_msr_access = check_msr(er->msr, 0x1ffUL);
|
|
|
|
|
/* Disable LBR select mapping */
|
|
|
|
|
if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
|
|
|
|
|
x86_pmu.lbr_sel_map = NULL;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2013-06-25 15:12:33 +00:00
|
|
|
/* Support full width counters using alternative MSR range */
|
|
|
|
|
if (x86_pmu.intel_cap.full_width_write) {
|
|
|
|
|
x86_pmu.max_period = x86_pmu.cntval_mask;
|
|
|
|
|
x86_pmu.perfctr = MSR_IA32_PMC0;
|
|
|
|
|
pr_cont("full-width counters, ");
|
|
|
|
|
}
|
|
|
|
|
|
2010-02-26 11:05:05 +00:00
|
|
|
return 0;
|
|
|
|
|
}
|