2019-06-01 08:08:33 +00:00
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// SPDX-License-Identifier: GPL-2.0-only
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2010-05-28 09:10:52 +00:00
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/*
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* PCI-E support for CNS3xxx
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*
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* Copyright 2008 Cavium Networks
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* Richard Liu <richard.liu@caviumnetworks.com>
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* Copyright 2010 MontaVista Software, LLC.
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* Anton Vorontsov <avorontsov@mvista.com>
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/bug.h>
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#include <linux/pci.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/ptrace.h>
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#include <asm/mach/map.h>
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2013-03-13 12:15:25 +00:00
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#include "cns3xxx.h"
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2010-05-28 09:10:52 +00:00
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#include "core.h"
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struct cns3xxx_pcie {
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2014-03-04 07:37:10 +00:00
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void __iomem *host_regs; /* PCI config registers for host bridge */
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void __iomem *cfg0_regs; /* PCI Type 0 config registers */
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void __iomem *cfg1_regs; /* PCI Type 1 config registers */
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2010-05-28 09:10:52 +00:00
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unsigned int irqs[2];
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struct resource res_io;
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struct resource res_mem;
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2014-11-21 11:29:25 +00:00
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int port;
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2010-05-28 09:10:52 +00:00
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bool linked;
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};
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static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
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{
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struct pci_sys_data *root = sysdata;
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2014-11-21 11:29:25 +00:00
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return root->private_data;
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2010-05-28 09:10:52 +00:00
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}
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2011-09-09 19:18:00 +00:00
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static struct cns3xxx_pcie *pdev_to_cnspci(const struct pci_dev *dev)
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2010-05-28 09:10:52 +00:00
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{
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return sysdata_to_cnspci(dev->sysdata);
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}
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static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus)
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{
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return sysdata_to_cnspci(bus->sysdata);
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}
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2015-01-10 02:34:40 +00:00
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static void __iomem *cns3xxx_pci_map_bus(struct pci_bus *bus,
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unsigned int devfn, int where)
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2010-05-28 09:10:52 +00:00
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{
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struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
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int busno = bus->number;
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int slot = PCI_SLOT(devfn);
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void __iomem *base;
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/* If there is no link, just show the CNS PCI bridge. */
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2014-09-16 10:36:32 +00:00
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if (!cnspci->linked && busno > 0)
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2010-05-28 09:10:52 +00:00
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return NULL;
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/*
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* The CNS PCI bridge doesn't fit into the PCI hierarchy, though
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ARM: cns3xxx: pci: avoid potential stack overflow
The cns3xxx_pcie_hw_init function uses excessive kernel
stack space because of a hack that puts a fake struct
pci_sys_data and struct pci_bus on the stack in order to
call the generic pci_bus_read_config accessors, which causes
a warning in ARM allmodconfig builds:
arch/arm/mach-cns3xxx/pcie.c:266:1: warning: the frame size of 1080 bytes is larger than 1024 bytes
I've spent a few hours trying to find out what exactly this
code is wants to achieve here. The obvious part is setting
up the host_regs using config space accessors, and this can
simply be changed to use direct MMIO accesses, as I do
in this patch.
The second part is how the driver sets up the Max_Read_Request_Size
value for the first device/function on bus 1, i.e. the device
plugged directly into the PCIe root port.
For all I can tell, this is in fact incomplete, as it does not
perform the same setting on devices attached to a PCIe switch,
or multi-function devices.
The solution for this part fortunately is even easier: if we
just set the global pcie_bus_config variable to PCIE_BUS_PEER2PEER,
all PCIe devices in the system are limited to 128 byte MPS, which
in turn limits the MRRS to 128 bytes for all devices, and we
no longer even need to touch any devices.
With those two changes in place, we no longer need the fake
pci_sys_data/pci_bus structures for faking config space writes,
and the stack usage goes down as well.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Krzysztof Halasa <khalasa@piap.pl>
2015-10-07 20:05:49 +00:00
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* we still want to access it.
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* We place the host bridge on bus 0, and the directly connected
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* device on bus 1, slot 0.
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2010-05-28 09:10:52 +00:00
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*/
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2014-09-16 10:36:32 +00:00
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if (busno == 0) { /* internal PCIe bus, host bridge device */
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if (devfn == 0) /* device# and function# are ignored by hw */
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2014-03-04 07:37:10 +00:00
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base = cnspci->host_regs;
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2014-09-16 10:36:32 +00:00
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else
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return NULL; /* no such device */
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} else if (busno == 1) { /* directly connected PCIe device */
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if (slot == 0) /* device# is ignored by hw */
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2014-03-04 07:37:10 +00:00
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base = cnspci->cfg0_regs;
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2014-09-16 10:36:32 +00:00
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else
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2014-03-04 07:37:10 +00:00
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return NULL; /* no such device */
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} else /* remote PCI bus */
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2014-09-16 10:36:32 +00:00
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base = cnspci->cfg1_regs + ((busno & 0xf) << 20);
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2010-05-28 09:10:52 +00:00
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2019-01-31 21:00:01 +00:00
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return base + where + (devfn << 12);
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2010-05-28 09:10:52 +00:00
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}
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static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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2015-01-10 02:34:40 +00:00
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int ret;
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2010-05-28 09:10:52 +00:00
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u32 mask = (0x1ull << (size * 8)) - 1;
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int shift = (where % 4) * 8;
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2019-01-31 21:00:11 +00:00
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ret = pci_generic_config_read(bus, devfn, where, size, val);
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2010-05-28 09:10:52 +00:00
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2015-01-10 02:34:40 +00:00
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if (ret == PCIBIOS_SUCCESSFUL && !bus->number && !devfn &&
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(where & 0xffc) == PCI_CLASS_REVISION)
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2010-05-28 09:10:52 +00:00
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/*
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* RC's class is 0xb, but Linux PCI driver needs 0x604
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* for a PCIe bridge. So we must fixup the class code
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* to 0x604 here.
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*/
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2015-01-10 02:34:40 +00:00
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*val = ((((*val << shift) & 0xff) | (0x604 << 16)) >> shift) & mask;
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2010-05-28 09:10:52 +00:00
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2015-01-10 02:34:40 +00:00
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return ret;
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2010-05-28 09:10:52 +00:00
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}
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static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
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{
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struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
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struct resource *res_io = &cnspci->res_io;
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struct resource *res_mem = &cnspci->res_mem;
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BUG_ON(request_resource(&iomem_resource, res_io) ||
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request_resource(&iomem_resource, res_mem));
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2012-02-24 03:19:01 +00:00
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pci_add_resource_offset(&sys->resources, res_io, sys->io_offset);
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pci_add_resource_offset(&sys->resources, res_mem, sys->mem_offset);
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2010-05-28 09:10:52 +00:00
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return 1;
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}
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static struct pci_ops cns3xxx_pcie_ops = {
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2015-01-10 02:34:40 +00:00
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.map_bus = cns3xxx_pci_map_bus,
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2010-05-28 09:10:52 +00:00
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.read = cns3xxx_pci_read_config,
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2015-01-10 02:34:40 +00:00
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.write = pci_generic_config_write,
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2010-05-28 09:10:52 +00:00
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};
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2011-06-10 14:30:21 +00:00
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static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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2010-05-28 09:10:52 +00:00
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{
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struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
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2014-09-16 10:36:32 +00:00
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int irq = cnspci->irqs[!!dev->bus->number];
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2010-05-28 09:10:52 +00:00
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pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
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pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
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PCI_FUNC(dev->devfn), slot, pin, irq);
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return irq;
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}
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static struct cns3xxx_pcie cns3xxx_pcie[] = {
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[0] = {
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2014-03-04 07:37:10 +00:00
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.host_regs = (void __iomem *)CNS3XXX_PCIE0_HOST_BASE_VIRT,
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.cfg0_regs = (void __iomem *)CNS3XXX_PCIE0_CFG0_BASE_VIRT,
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.cfg1_regs = (void __iomem *)CNS3XXX_PCIE0_CFG1_BASE_VIRT,
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2010-05-28 09:10:52 +00:00
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.res_io = {
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.name = "PCIe0 I/O space",
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.start = CNS3XXX_PCIE0_IO_BASE,
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2014-03-04 07:37:10 +00:00
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.end = CNS3XXX_PCIE0_CFG0_BASE - 1, /* 16 MiB */
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2010-05-28 09:10:52 +00:00
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.flags = IORESOURCE_IO,
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},
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.res_mem = {
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.name = "PCIe0 non-prefetchable",
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.start = CNS3XXX_PCIE0_MEM_BASE,
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2014-03-04 07:37:10 +00:00
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.end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */
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2010-05-28 09:10:52 +00:00
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.flags = IORESOURCE_MEM,
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},
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.irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
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2014-11-21 11:29:25 +00:00
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.port = 0,
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2010-05-28 09:10:52 +00:00
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},
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[1] = {
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2014-03-04 07:37:10 +00:00
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.host_regs = (void __iomem *)CNS3XXX_PCIE1_HOST_BASE_VIRT,
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.cfg0_regs = (void __iomem *)CNS3XXX_PCIE1_CFG0_BASE_VIRT,
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.cfg1_regs = (void __iomem *)CNS3XXX_PCIE1_CFG1_BASE_VIRT,
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2010-05-28 09:10:52 +00:00
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.res_io = {
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.name = "PCIe1 I/O space",
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.start = CNS3XXX_PCIE1_IO_BASE,
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2014-03-04 07:37:10 +00:00
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.end = CNS3XXX_PCIE1_CFG0_BASE - 1, /* 16 MiB */
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2010-05-28 09:10:52 +00:00
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.flags = IORESOURCE_IO,
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},
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.res_mem = {
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.name = "PCIe1 non-prefetchable",
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.start = CNS3XXX_PCIE1_MEM_BASE,
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2014-03-04 07:37:10 +00:00
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.end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */
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2010-05-28 09:10:52 +00:00
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.flags = IORESOURCE_MEM,
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},
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.irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
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2014-11-21 11:29:25 +00:00
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.port = 1,
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2010-05-28 09:10:52 +00:00
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},
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};
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static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
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{
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2014-11-21 11:29:25 +00:00
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int port = cnspci->port;
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2010-05-28 09:10:52 +00:00
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u32 reg;
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unsigned long time;
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reg = __raw_readl(MISC_PCIE_CTRL(port));
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/*
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* Enable Application Request to 1, it will exit L1 automatically,
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* but when chip back, it will use another clock, still can use 0x1.
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*/
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reg |= 0x3;
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__raw_writel(reg, MISC_PCIE_CTRL(port));
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pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port);
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pr_info("PCIe: Port[%d] Check data link layer...", port);
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time = jiffies;
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while (1) {
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reg = __raw_readl(MISC_PCIE_PM_DEBUG(port));
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if (reg & 0x1) {
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pr_info("Link up.\n");
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cnspci->linked = 1;
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break;
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} else if (time_after(jiffies, time + 50)) {
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pr_info("Device not found.\n");
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break;
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}
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}
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}
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ARM: cns3xxx: pci: avoid potential stack overflow
The cns3xxx_pcie_hw_init function uses excessive kernel
stack space because of a hack that puts a fake struct
pci_sys_data and struct pci_bus on the stack in order to
call the generic pci_bus_read_config accessors, which causes
a warning in ARM allmodconfig builds:
arch/arm/mach-cns3xxx/pcie.c:266:1: warning: the frame size of 1080 bytes is larger than 1024 bytes
I've spent a few hours trying to find out what exactly this
code is wants to achieve here. The obvious part is setting
up the host_regs using config space accessors, and this can
simply be changed to use direct MMIO accesses, as I do
in this patch.
The second part is how the driver sets up the Max_Read_Request_Size
value for the first device/function on bus 1, i.e. the device
plugged directly into the PCIe root port.
For all I can tell, this is in fact incomplete, as it does not
perform the same setting on devices attached to a PCIe switch,
or multi-function devices.
The solution for this part fortunately is even easier: if we
just set the global pcie_bus_config variable to PCIE_BUS_PEER2PEER,
all PCIe devices in the system are limited to 128 byte MPS, which
in turn limits the MRRS to 128 bytes for all devices, and we
no longer even need to touch any devices.
With those two changes in place, we no longer need the fake
pci_sys_data/pci_bus structures for faking config space writes,
and the stack usage goes down as well.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Krzysztof Halasa <khalasa@piap.pl>
2015-10-07 20:05:49 +00:00
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static void cns3xxx_write_config(struct cns3xxx_pcie *cnspci,
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int where, int size, u32 val)
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{
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void __iomem *base = cnspci->host_regs + (where & 0xffc);
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u32 v;
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u32 mask = (0x1ull << (size * 8)) - 1;
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int shift = (where % 4) * 8;
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2016-03-11 11:32:14 +00:00
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v = readl_relaxed(base);
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ARM: cns3xxx: pci: avoid potential stack overflow
The cns3xxx_pcie_hw_init function uses excessive kernel
stack space because of a hack that puts a fake struct
pci_sys_data and struct pci_bus on the stack in order to
call the generic pci_bus_read_config accessors, which causes
a warning in ARM allmodconfig builds:
arch/arm/mach-cns3xxx/pcie.c:266:1: warning: the frame size of 1080 bytes is larger than 1024 bytes
I've spent a few hours trying to find out what exactly this
code is wants to achieve here. The obvious part is setting
up the host_regs using config space accessors, and this can
simply be changed to use direct MMIO accesses, as I do
in this patch.
The second part is how the driver sets up the Max_Read_Request_Size
value for the first device/function on bus 1, i.e. the device
plugged directly into the PCIe root port.
For all I can tell, this is in fact incomplete, as it does not
perform the same setting on devices attached to a PCIe switch,
or multi-function devices.
The solution for this part fortunately is even easier: if we
just set the global pcie_bus_config variable to PCIE_BUS_PEER2PEER,
all PCIe devices in the system are limited to 128 byte MPS, which
in turn limits the MRRS to 128 bytes for all devices, and we
no longer even need to touch any devices.
With those two changes in place, we no longer need the fake
pci_sys_data/pci_bus structures for faking config space writes,
and the stack usage goes down as well.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Krzysztof Halasa <khalasa@piap.pl>
2015-10-07 20:05:49 +00:00
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v &= ~(mask << shift);
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v |= (val & mask) << shift;
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2016-03-11 11:32:14 +00:00
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writel_relaxed(v, base);
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readl_relaxed(base);
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ARM: cns3xxx: pci: avoid potential stack overflow
The cns3xxx_pcie_hw_init function uses excessive kernel
stack space because of a hack that puts a fake struct
pci_sys_data and struct pci_bus on the stack in order to
call the generic pci_bus_read_config accessors, which causes
a warning in ARM allmodconfig builds:
arch/arm/mach-cns3xxx/pcie.c:266:1: warning: the frame size of 1080 bytes is larger than 1024 bytes
I've spent a few hours trying to find out what exactly this
code is wants to achieve here. The obvious part is setting
up the host_regs using config space accessors, and this can
simply be changed to use direct MMIO accesses, as I do
in this patch.
The second part is how the driver sets up the Max_Read_Request_Size
value for the first device/function on bus 1, i.e. the device
plugged directly into the PCIe root port.
For all I can tell, this is in fact incomplete, as it does not
perform the same setting on devices attached to a PCIe switch,
or multi-function devices.
The solution for this part fortunately is even easier: if we
just set the global pcie_bus_config variable to PCIE_BUS_PEER2PEER,
all PCIe devices in the system are limited to 128 byte MPS, which
in turn limits the MRRS to 128 bytes for all devices, and we
no longer even need to touch any devices.
With those two changes in place, we no longer need the fake
pci_sys_data/pci_bus structures for faking config space writes,
and the stack usage goes down as well.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Krzysztof Halasa <khalasa@piap.pl>
2015-10-07 20:05:49 +00:00
|
|
|
}
|
|
|
|
|
2010-05-28 09:10:52 +00:00
|
|
|
static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
|
|
|
|
{
|
2014-03-04 07:37:10 +00:00
|
|
|
u16 mem_base = cnspci->res_mem.start >> 16;
|
|
|
|
u16 mem_limit = cnspci->res_mem.end >> 16;
|
|
|
|
u16 io_base = cnspci->res_io.start >> 16;
|
|
|
|
u16 io_limit = cnspci->res_io.end >> 16;
|
2010-05-28 09:10:52 +00:00
|
|
|
|
ARM: cns3xxx: pci: avoid potential stack overflow
The cns3xxx_pcie_hw_init function uses excessive kernel
stack space because of a hack that puts a fake struct
pci_sys_data and struct pci_bus on the stack in order to
call the generic pci_bus_read_config accessors, which causes
a warning in ARM allmodconfig builds:
arch/arm/mach-cns3xxx/pcie.c:266:1: warning: the frame size of 1080 bytes is larger than 1024 bytes
I've spent a few hours trying to find out what exactly this
code is wants to achieve here. The obvious part is setting
up the host_regs using config space accessors, and this can
simply be changed to use direct MMIO accesses, as I do
in this patch.
The second part is how the driver sets up the Max_Read_Request_Size
value for the first device/function on bus 1, i.e. the device
plugged directly into the PCIe root port.
For all I can tell, this is in fact incomplete, as it does not
perform the same setting on devices attached to a PCIe switch,
or multi-function devices.
The solution for this part fortunately is even easier: if we
just set the global pcie_bus_config variable to PCIE_BUS_PEER2PEER,
all PCIe devices in the system are limited to 128 byte MPS, which
in turn limits the MRRS to 128 bytes for all devices, and we
no longer even need to touch any devices.
With those two changes in place, we no longer need the fake
pci_sys_data/pci_bus structures for faking config space writes,
and the stack usage goes down as well.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Krzysztof Halasa <khalasa@piap.pl>
2015-10-07 20:05:49 +00:00
|
|
|
cns3xxx_write_config(cnspci, PCI_PRIMARY_BUS, 1, 0);
|
|
|
|
cns3xxx_write_config(cnspci, PCI_SECONDARY_BUS, 1, 1);
|
|
|
|
cns3xxx_write_config(cnspci, PCI_SUBORDINATE_BUS, 1, 1);
|
|
|
|
cns3xxx_write_config(cnspci, PCI_MEMORY_BASE, 2, mem_base);
|
|
|
|
cns3xxx_write_config(cnspci, PCI_MEMORY_LIMIT, 2, mem_limit);
|
|
|
|
cns3xxx_write_config(cnspci, PCI_IO_BASE_UPPER16, 2, io_base);
|
|
|
|
cns3xxx_write_config(cnspci, PCI_IO_LIMIT_UPPER16, 2, io_limit);
|
2010-05-28 09:10:52 +00:00
|
|
|
|
|
|
|
if (!cnspci->linked)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* Set Device Max_Read_Request_Size to 128 byte */
|
ARM: cns3xxx: pci: avoid potential stack overflow
The cns3xxx_pcie_hw_init function uses excessive kernel
stack space because of a hack that puts a fake struct
pci_sys_data and struct pci_bus on the stack in order to
call the generic pci_bus_read_config accessors, which causes
a warning in ARM allmodconfig builds:
arch/arm/mach-cns3xxx/pcie.c:266:1: warning: the frame size of 1080 bytes is larger than 1024 bytes
I've spent a few hours trying to find out what exactly this
code is wants to achieve here. The obvious part is setting
up the host_regs using config space accessors, and this can
simply be changed to use direct MMIO accesses, as I do
in this patch.
The second part is how the driver sets up the Max_Read_Request_Size
value for the first device/function on bus 1, i.e. the device
plugged directly into the PCIe root port.
For all I can tell, this is in fact incomplete, as it does not
perform the same setting on devices attached to a PCIe switch,
or multi-function devices.
The solution for this part fortunately is even easier: if we
just set the global pcie_bus_config variable to PCIE_BUS_PEER2PEER,
all PCIe devices in the system are limited to 128 byte MPS, which
in turn limits the MRRS to 128 bytes for all devices, and we
no longer even need to touch any devices.
With those two changes in place, we no longer need the fake
pci_sys_data/pci_bus structures for faking config space writes,
and the stack usage goes down as well.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Krzysztof Halasa <khalasa@piap.pl>
2015-10-07 20:05:49 +00:00
|
|
|
pcie_bus_config = PCIE_BUS_PEER2PEER;
|
|
|
|
|
2010-05-28 09:10:52 +00:00
|
|
|
/* Disable PCIe0 Interrupt Mask INTA to INTD */
|
ARM: cns3xxx: pci: avoid potential stack overflow
The cns3xxx_pcie_hw_init function uses excessive kernel
stack space because of a hack that puts a fake struct
pci_sys_data and struct pci_bus on the stack in order to
call the generic pci_bus_read_config accessors, which causes
a warning in ARM allmodconfig builds:
arch/arm/mach-cns3xxx/pcie.c:266:1: warning: the frame size of 1080 bytes is larger than 1024 bytes
I've spent a few hours trying to find out what exactly this
code is wants to achieve here. The obvious part is setting
up the host_regs using config space accessors, and this can
simply be changed to use direct MMIO accesses, as I do
in this patch.
The second part is how the driver sets up the Max_Read_Request_Size
value for the first device/function on bus 1, i.e. the device
plugged directly into the PCIe root port.
For all I can tell, this is in fact incomplete, as it does not
perform the same setting on devices attached to a PCIe switch,
or multi-function devices.
The solution for this part fortunately is even easier: if we
just set the global pcie_bus_config variable to PCIE_BUS_PEER2PEER,
all PCIe devices in the system are limited to 128 byte MPS, which
in turn limits the MRRS to 128 bytes for all devices, and we
no longer even need to touch any devices.
With those two changes in place, we no longer need the fake
pci_sys_data/pci_bus structures for faking config space writes,
and the stack usage goes down as well.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Krzysztof Halasa <khalasa@piap.pl>
2015-10-07 20:05:49 +00:00
|
|
|
__raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(cnspci->port));
|
2010-05-28 09:10:52 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
|
|
|
|
struct pt_regs *regs)
|
|
|
|
{
|
|
|
|
if (fsr & (1 << 10))
|
|
|
|
regs->ARM_pc += 4;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-09-03 13:18:12 +00:00
|
|
|
void __init cns3xxx_pcie_init_late(void)
|
2010-05-28 09:10:52 +00:00
|
|
|
{
|
|
|
|
int i;
|
2014-11-21 11:29:25 +00:00
|
|
|
void *private_data;
|
|
|
|
struct hw_pci hw_pci = {
|
|
|
|
.nr_controllers = 1,
|
|
|
|
.ops = &cns3xxx_pcie_ops,
|
|
|
|
.setup = cns3xxx_pci_setup,
|
|
|
|
.map_irq = cns3xxx_pcie_map_irq,
|
|
|
|
.private_data = &private_data,
|
|
|
|
};
|
2010-05-28 09:10:52 +00:00
|
|
|
|
2011-06-29 02:16:13 +00:00
|
|
|
pcibios_min_io = 0;
|
|
|
|
pcibios_min_mem = 0;
|
|
|
|
|
2010-11-29 15:46:22 +00:00
|
|
|
hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0,
|
2010-05-28 09:10:52 +00:00
|
|
|
"imprecise external abort");
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
|
|
|
|
cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
|
|
|
|
cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
|
|
|
|
cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
|
|
|
|
cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
|
2014-11-21 11:29:25 +00:00
|
|
|
private_data = &cns3xxx_pcie[i];
|
|
|
|
pci_common_init(&hw_pci);
|
2010-05-28 09:10:52 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
pci_assign_unassigned_resources();
|
|
|
|
}
|