2020-01-29 13:28:17 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Serial Port driver for Tegra devices
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*
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* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/acpi.h>
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#include <linux/clk.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include "8250.h"
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struct tegra_uart {
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struct clk *clk;
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struct reset_control *rst;
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int line;
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};
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static void tegra_uart_handle_break(struct uart_port *p)
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{
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unsigned int status, tmout = 10000;
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2021-01-05 12:02:33 +00:00
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while (1) {
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2020-01-29 13:28:17 +00:00
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status = p->serial_in(p, UART_LSR);
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2021-01-05 12:02:33 +00:00
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if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)))
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2020-01-29 13:28:17 +00:00
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break;
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2021-01-05 12:02:33 +00:00
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p->serial_in(p, UART_RX);
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2020-01-29 13:28:17 +00:00
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if (--tmout == 0)
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break;
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udelay(1);
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2021-01-05 12:02:33 +00:00
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}
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2020-01-29 13:28:17 +00:00
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}
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static int tegra_uart_probe(struct platform_device *pdev)
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{
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struct uart_8250_port port8250;
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struct tegra_uart *uart;
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struct uart_port *port;
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struct resource *res;
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int ret;
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uart = devm_kzalloc(&pdev->dev, sizeof(*uart), GFP_KERNEL);
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if (!uart)
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return -ENOMEM;
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memset(&port8250, 0, sizeof(port8250));
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port = &port8250.port;
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spin_lock_init(&port->lock);
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port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT |
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UPF_FIXED_TYPE;
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port->iotype = UPIO_MEM32;
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port->regshift = 2;
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port->type = PORT_TEGRA;
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port->irqflags |= IRQF_SHARED;
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port->dev = &pdev->dev;
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port->handle_break = tegra_uart_handle_break;
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ret = of_alias_get_id(pdev->dev.of_node, "serial");
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if (ret >= 0)
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port->line = ret;
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ret = platform_get_irq(pdev, 0);
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if (ret < 0)
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return ret;
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port->irq = ret;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENODEV;
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port->membase = devm_ioremap(&pdev->dev, res->start,
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resource_size(res));
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if (!port->membase)
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return -ENOMEM;
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port->mapbase = res->start;
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port->mapsize = resource_size(res);
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uart->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
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if (IS_ERR(uart->rst))
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return PTR_ERR(uart->rst);
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if (device_property_read_u32(&pdev->dev, "clock-frequency",
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&port->uartclk)) {
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uart->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(uart->clk)) {
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dev_err(&pdev->dev, "failed to get clock!\n");
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return -ENODEV;
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}
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ret = clk_prepare_enable(uart->clk);
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if (ret < 0)
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return ret;
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port->uartclk = clk_get_rate(uart->clk);
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}
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ret = reset_control_deassert(uart->rst);
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if (ret)
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goto err_clkdisable;
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ret = serial8250_register_8250_port(&port8250);
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if (ret < 0)
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goto err_clkdisable;
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platform_set_drvdata(pdev, uart);
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uart->line = ret;
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return 0;
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err_clkdisable:
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clk_disable_unprepare(uart->clk);
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return ret;
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}
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static int tegra_uart_remove(struct platform_device *pdev)
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{
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struct tegra_uart *uart = platform_get_drvdata(pdev);
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serial8250_unregister_port(uart->line);
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reset_control_assert(uart->rst);
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clk_disable_unprepare(uart->clk);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int tegra_uart_suspend(struct device *dev)
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{
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struct tegra_uart *uart = dev_get_drvdata(dev);
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struct uart_8250_port *port8250 = serial8250_get_port(uart->line);
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struct uart_port *port = &port8250->port;
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serial8250_suspend_port(uart->line);
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if (!uart_console(port) || console_suspend_enabled)
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clk_disable_unprepare(uart->clk);
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return 0;
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}
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static int tegra_uart_resume(struct device *dev)
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{
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struct tegra_uart *uart = dev_get_drvdata(dev);
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struct uart_8250_port *port8250 = serial8250_get_port(uart->line);
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struct uart_port *port = &port8250->port;
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if (!uart_console(port) || console_suspend_enabled)
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clk_prepare_enable(uart->clk);
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serial8250_resume_port(uart->line);
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return 0;
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}
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#endif
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static SIMPLE_DEV_PM_OPS(tegra_uart_pm_ops, tegra_uart_suspend,
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tegra_uart_resume);
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static const struct of_device_id tegra_uart_of_match[] = {
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{ .compatible = "nvidia,tegra20-uart", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
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static const struct acpi_device_id tegra_uart_acpi_match[] = {
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{ "NVDA0100", 0 },
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{ },
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};
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MODULE_DEVICE_TABLE(acpi, tegra_uart_acpi_match);
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static struct platform_driver tegra_uart_driver = {
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.driver = {
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.name = "tegra-uart",
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.pm = &tegra_uart_pm_ops,
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.of_match_table = tegra_uart_of_match,
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.acpi_match_table = ACPI_PTR(tegra_uart_acpi_match),
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},
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.probe = tegra_uart_probe,
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.remove = tegra_uart_remove,
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};
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module_platform_driver(tegra_uart_driver);
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MODULE_AUTHOR("Jeff Brasen <jbrasen@nvidia.com>");
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MODULE_DESCRIPTION("NVIDIA Tegra 8250 Driver");
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MODULE_LICENSE("GPL v2");
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