2017-12-18 15:53:03 +00:00
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/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu_ids.h"
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#include <linux/idr.h>
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#include <linux/dma-fence-array.h>
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#include <drm/drmP.h>
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#include "amdgpu.h"
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#include "amdgpu_trace.h"
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/*
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* PASID manager
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*
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* PASIDs are global address space identifiers that can be shared
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* between the GPU, an IOMMU and the driver. VMs on different devices
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* may use the same PASID if they share the same address
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* space. Therefore PASIDs are allocated using a global IDA. VMs are
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* looked up from the PASID per amdgpu_device.
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*/
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static DEFINE_IDA(amdgpu_pasid_ida);
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2018-01-05 10:16:22 +00:00
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/* Helper to free pasid from a fence callback */
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struct amdgpu_pasid_cb {
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struct dma_fence_cb cb;
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unsigned int pasid;
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};
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2017-12-18 15:53:03 +00:00
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/**
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* amdgpu_pasid_alloc - Allocate a PASID
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* @bits: Maximum width of the PASID in bits, must be at least 1
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*
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* Allocates a PASID of the given width while keeping smaller PASIDs
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* available if possible.
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*
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* Returns a positive integer on success. Returns %-EINVAL if bits==0.
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* Returns %-ENOSPC if no PASID was available. Returns %-ENOMEM on
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* memory allocation failure.
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*/
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int amdgpu_pasid_alloc(unsigned int bits)
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{
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int pasid = -EINVAL;
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for (bits = min(bits, 31U); bits > 0; bits--) {
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pasid = ida_simple_get(&amdgpu_pasid_ida,
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1U << (bits - 1), 1U << bits,
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GFP_KERNEL);
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if (pasid != -ENOSPC)
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break;
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}
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2018-01-09 18:32:58 +00:00
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if (pasid >= 0)
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trace_amdgpu_pasid_allocated(pasid);
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2017-12-18 15:53:03 +00:00
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return pasid;
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}
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/**
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* amdgpu_pasid_free - Free a PASID
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* @pasid: PASID to free
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*/
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void amdgpu_pasid_free(unsigned int pasid)
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{
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2018-01-09 18:32:58 +00:00
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trace_amdgpu_pasid_freed(pasid);
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2017-12-18 15:53:03 +00:00
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ida_simple_remove(&amdgpu_pasid_ida, pasid);
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}
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2018-01-05 10:16:22 +00:00
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static void amdgpu_pasid_free_cb(struct dma_fence *fence,
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struct dma_fence_cb *_cb)
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{
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struct amdgpu_pasid_cb *cb =
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container_of(_cb, struct amdgpu_pasid_cb, cb);
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amdgpu_pasid_free(cb->pasid);
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dma_fence_put(fence);
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kfree(cb);
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}
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/**
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* amdgpu_pasid_free_delayed - free pasid when fences signal
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*
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* @resv: reservation object with the fences to wait for
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* @pasid: pasid to free
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*
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* Free the pasid only after all the fences in resv are signaled.
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*/
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void amdgpu_pasid_free_delayed(struct reservation_object *resv,
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unsigned int pasid)
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{
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struct dma_fence *fence, **fences;
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struct amdgpu_pasid_cb *cb;
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unsigned count;
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int r;
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r = reservation_object_get_fences_rcu(resv, NULL, &count, &fences);
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if (r)
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goto fallback;
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if (count == 0) {
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amdgpu_pasid_free(pasid);
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return;
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}
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if (count == 1) {
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fence = fences[0];
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kfree(fences);
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} else {
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uint64_t context = dma_fence_context_alloc(1);
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struct dma_fence_array *array;
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array = dma_fence_array_create(count, fences, context,
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1, false);
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if (!array) {
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kfree(fences);
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goto fallback;
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}
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fence = &array->base;
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}
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cb = kmalloc(sizeof(*cb), GFP_KERNEL);
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if (!cb) {
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/* Last resort when we are OOM */
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dma_fence_wait(fence, false);
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dma_fence_put(fence);
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amdgpu_pasid_free(pasid);
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} else {
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cb->pasid = pasid;
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if (dma_fence_add_callback(fence, &cb->cb,
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amdgpu_pasid_free_cb))
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amdgpu_pasid_free_cb(fence, &cb->cb);
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}
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return;
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fallback:
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/* Not enough memory for the delayed delete, as last resort
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* block for all the fences to complete.
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*/
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reservation_object_wait_timeout_rcu(resv, true, false,
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MAX_SCHEDULE_TIMEOUT);
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amdgpu_pasid_free(pasid);
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}
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2017-12-18 15:53:03 +00:00
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/*
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* VMID manager
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*
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* VMIDs are a per VMHUB identifier for page tables handling.
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*/
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/**
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* amdgpu_vmid_had_gpu_reset - check if reset occured since last use
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*
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* @adev: amdgpu_device pointer
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* @id: VMID structure
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*
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* Check if GPU reset occured since last use of the VMID.
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*/
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bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev,
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struct amdgpu_vmid *id)
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{
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return id->current_gpu_reset_count !=
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atomic_read(&adev->gpu_reset_counter);
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}
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/* idr_mgr->lock must be held */
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static int amdgpu_vmid_grab_reserved_locked(struct amdgpu_vm *vm,
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struct amdgpu_ring *ring,
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struct amdgpu_sync *sync,
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struct dma_fence *fence,
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struct amdgpu_job *job)
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{
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struct amdgpu_device *adev = ring->adev;
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unsigned vmhub = ring->funcs->vmhub;
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uint64_t fence_context = adev->fence_context + ring->idx;
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struct amdgpu_vmid *id = vm->reserved_vmid[vmhub];
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struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
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struct dma_fence *updates = sync->last_vm_update;
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int r = 0;
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struct dma_fence *flushed, *tmp;
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bool needs_flush = vm->use_cpu_for_update;
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flushed = id->flushed_updates;
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if ((amdgpu_vmid_had_gpu_reset(adev, id)) ||
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2017-12-18 16:10:01 +00:00
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(atomic64_read(&id->owner) != vm->entity.fence_context) ||
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2017-12-18 15:53:03 +00:00
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(job->vm_pd_addr != id->pd_gpu_addr) ||
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(updates && (!flushed || updates->context != flushed->context ||
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dma_fence_is_later(updates, flushed))) ||
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(!id->last_flush || (id->last_flush->context != fence_context &&
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!dma_fence_is_signaled(id->last_flush)))) {
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needs_flush = true;
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/* to prevent one context starved by another context */
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id->pd_gpu_addr = 0;
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tmp = amdgpu_sync_peek_fence(&id->active, ring);
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if (tmp) {
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r = amdgpu_sync_fence(adev, sync, tmp, false);
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return r;
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}
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}
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/* Good we can use this VMID. Remember this submission as
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* user of the VMID.
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*/
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r = amdgpu_sync_fence(ring->adev, &id->active, fence, false);
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if (r)
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goto out;
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if (updates && (!flushed || updates->context != flushed->context ||
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dma_fence_is_later(updates, flushed))) {
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dma_fence_put(id->flushed_updates);
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id->flushed_updates = dma_fence_get(updates);
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}
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id->pd_gpu_addr = job->vm_pd_addr;
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2017-12-18 16:10:01 +00:00
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atomic64_set(&id->owner, vm->entity.fence_context);
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2017-12-18 15:53:03 +00:00
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job->vm_needs_flush = needs_flush;
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if (needs_flush) {
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dma_fence_put(id->last_flush);
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id->last_flush = NULL;
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}
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2017-12-18 16:08:25 +00:00
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job->vmid = id - id_mgr->ids;
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2018-01-08 13:48:11 +00:00
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job->pasid = vm->pasid;
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2017-12-18 15:53:03 +00:00
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trace_amdgpu_vm_grab_id(vm, ring, job);
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out:
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return r;
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}
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/**
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* amdgpu_vm_grab_id - allocate the next free VMID
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*
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* @vm: vm to allocate id for
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* @ring: ring we want to submit job to
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* @sync: sync object where we add dependencies
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* @fence: fence protecting ID from reuse
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*
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* Allocate an id for the vm, adding fences to the sync obj as necessary.
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*/
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int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
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struct amdgpu_sync *sync, struct dma_fence *fence,
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struct amdgpu_job *job)
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{
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struct amdgpu_device *adev = ring->adev;
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unsigned vmhub = ring->funcs->vmhub;
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struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
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uint64_t fence_context = adev->fence_context + ring->idx;
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struct dma_fence *updates = sync->last_vm_update;
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struct amdgpu_vmid *id, *idle;
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struct dma_fence **fences;
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unsigned i;
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int r = 0;
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mutex_lock(&id_mgr->lock);
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if (vm->reserved_vmid[vmhub]) {
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r = amdgpu_vmid_grab_reserved_locked(vm, ring, sync, fence, job);
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mutex_unlock(&id_mgr->lock);
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return r;
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}
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fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL);
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if (!fences) {
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mutex_unlock(&id_mgr->lock);
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return -ENOMEM;
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}
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/* Check if we have an idle VMID */
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i = 0;
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list_for_each_entry(idle, &id_mgr->ids_lru, list) {
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fences[i] = amdgpu_sync_peek_fence(&idle->active, ring);
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if (!fences[i])
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break;
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++i;
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}
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/* If we can't find a idle VMID to use, wait till one becomes available */
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if (&idle->list == &id_mgr->ids_lru) {
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u64 fence_context = adev->vm_manager.fence_context + ring->idx;
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unsigned seqno = ++adev->vm_manager.seqno[ring->idx];
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struct dma_fence_array *array;
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unsigned j;
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for (j = 0; j < i; ++j)
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dma_fence_get(fences[j]);
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array = dma_fence_array_create(i, fences, fence_context,
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seqno, true);
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if (!array) {
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for (j = 0; j < i; ++j)
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dma_fence_put(fences[j]);
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kfree(fences);
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r = -ENOMEM;
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goto error;
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}
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r = amdgpu_sync_fence(ring->adev, sync, &array->base, false);
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dma_fence_put(&array->base);
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if (r)
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goto error;
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mutex_unlock(&id_mgr->lock);
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return 0;
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}
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kfree(fences);
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job->vm_needs_flush = vm->use_cpu_for_update;
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/* Check if we can use a VMID already assigned to this VM */
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list_for_each_entry_reverse(id, &id_mgr->ids_lru, list) {
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struct dma_fence *flushed;
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bool needs_flush = vm->use_cpu_for_update;
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/* Check all the prerequisites to using this VMID */
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if (amdgpu_vmid_had_gpu_reset(adev, id))
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continue;
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2017-12-18 16:10:01 +00:00
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if (atomic64_read(&id->owner) != vm->entity.fence_context)
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2017-12-18 15:53:03 +00:00
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continue;
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if (job->vm_pd_addr != id->pd_gpu_addr)
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continue;
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if (!id->last_flush ||
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(id->last_flush->context != fence_context &&
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!dma_fence_is_signaled(id->last_flush)))
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needs_flush = true;
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flushed = id->flushed_updates;
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if (updates && (!flushed || dma_fence_is_later(updates, flushed)))
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needs_flush = true;
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/* Concurrent flushes are only possible starting with Vega10 */
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|
|
if (adev->asic_type < CHIP_VEGA10 && needs_flush)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* Good we can use this VMID. Remember this submission as
|
|
|
|
* user of the VMID.
|
|
|
|
*/
|
|
|
|
r = amdgpu_sync_fence(ring->adev, &id->active, fence, false);
|
|
|
|
if (r)
|
|
|
|
goto error;
|
|
|
|
|
|
|
|
if (updates && (!flushed || dma_fence_is_later(updates, flushed))) {
|
|
|
|
dma_fence_put(id->flushed_updates);
|
|
|
|
id->flushed_updates = dma_fence_get(updates);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (needs_flush)
|
|
|
|
goto needs_flush;
|
|
|
|
else
|
|
|
|
goto no_flush_needed;
|
|
|
|
|
2018-01-04 23:06:46 +00:00
|
|
|
}
|
2017-12-18 15:53:03 +00:00
|
|
|
|
|
|
|
/* Still no ID to use? Then use the idle one found earlier */
|
|
|
|
id = idle;
|
|
|
|
|
|
|
|
/* Remember this submission as user of the VMID */
|
|
|
|
r = amdgpu_sync_fence(ring->adev, &id->active, fence, false);
|
|
|
|
if (r)
|
|
|
|
goto error;
|
|
|
|
|
|
|
|
id->pd_gpu_addr = job->vm_pd_addr;
|
|
|
|
dma_fence_put(id->flushed_updates);
|
|
|
|
id->flushed_updates = dma_fence_get(updates);
|
2017-12-18 16:10:01 +00:00
|
|
|
atomic64_set(&id->owner, vm->entity.fence_context);
|
2017-12-18 15:53:03 +00:00
|
|
|
|
|
|
|
needs_flush:
|
|
|
|
job->vm_needs_flush = true;
|
|
|
|
dma_fence_put(id->last_flush);
|
|
|
|
id->last_flush = NULL;
|
|
|
|
|
|
|
|
no_flush_needed:
|
|
|
|
list_move_tail(&id->list, &id_mgr->ids_lru);
|
|
|
|
|
2017-12-18 16:08:25 +00:00
|
|
|
job->vmid = id - id_mgr->ids;
|
2018-01-08 13:48:11 +00:00
|
|
|
job->pasid = vm->pasid;
|
2017-12-18 15:53:03 +00:00
|
|
|
trace_amdgpu_vm_grab_id(vm, ring, job);
|
|
|
|
|
|
|
|
error:
|
|
|
|
mutex_unlock(&id_mgr->lock);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev,
|
|
|
|
struct amdgpu_vm *vm,
|
|
|
|
unsigned vmhub)
|
|
|
|
{
|
|
|
|
struct amdgpu_vmid_mgr *id_mgr;
|
|
|
|
struct amdgpu_vmid *idle;
|
|
|
|
int r = 0;
|
|
|
|
|
|
|
|
id_mgr = &adev->vm_manager.id_mgr[vmhub];
|
|
|
|
mutex_lock(&id_mgr->lock);
|
|
|
|
if (vm->reserved_vmid[vmhub])
|
|
|
|
goto unlock;
|
|
|
|
if (atomic_inc_return(&id_mgr->reserved_vmid_num) >
|
|
|
|
AMDGPU_VM_MAX_RESERVED_VMID) {
|
|
|
|
DRM_ERROR("Over limitation of reserved vmid\n");
|
|
|
|
atomic_dec(&id_mgr->reserved_vmid_num);
|
|
|
|
r = -EINVAL;
|
|
|
|
goto unlock;
|
|
|
|
}
|
|
|
|
/* Select the first entry VMID */
|
|
|
|
idle = list_first_entry(&id_mgr->ids_lru, struct amdgpu_vmid, list);
|
|
|
|
list_del_init(&idle->list);
|
|
|
|
vm->reserved_vmid[vmhub] = idle;
|
|
|
|
mutex_unlock(&id_mgr->lock);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
unlock:
|
|
|
|
mutex_unlock(&id_mgr->lock);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
void amdgpu_vmid_free_reserved(struct amdgpu_device *adev,
|
|
|
|
struct amdgpu_vm *vm,
|
|
|
|
unsigned vmhub)
|
|
|
|
{
|
|
|
|
struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
|
|
|
|
|
|
|
|
mutex_lock(&id_mgr->lock);
|
|
|
|
if (vm->reserved_vmid[vmhub]) {
|
|
|
|
list_add(&vm->reserved_vmid[vmhub]->list,
|
|
|
|
&id_mgr->ids_lru);
|
|
|
|
vm->reserved_vmid[vmhub] = NULL;
|
|
|
|
atomic_dec(&id_mgr->reserved_vmid_num);
|
|
|
|
}
|
|
|
|
mutex_unlock(&id_mgr->lock);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_vmid_reset - reset VMID to zero
|
|
|
|
*
|
|
|
|
* @adev: amdgpu device structure
|
2017-12-18 16:08:25 +00:00
|
|
|
* @vmid: vmid number to use
|
2017-12-18 15:53:03 +00:00
|
|
|
*
|
|
|
|
* Reset saved GDW, GWS and OA to force switch on next flush.
|
|
|
|
*/
|
|
|
|
void amdgpu_vmid_reset(struct amdgpu_device *adev, unsigned vmhub,
|
|
|
|
unsigned vmid)
|
|
|
|
{
|
|
|
|
struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
|
|
|
|
struct amdgpu_vmid *id = &id_mgr->ids[vmid];
|
|
|
|
|
|
|
|
atomic64_set(&id->owner, 0);
|
|
|
|
id->gds_base = 0;
|
|
|
|
id->gds_size = 0;
|
|
|
|
id->gws_base = 0;
|
|
|
|
id->gws_size = 0;
|
|
|
|
id->oa_base = 0;
|
|
|
|
id->oa_size = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_vmid_reset_all - reset VMID to zero
|
|
|
|
*
|
|
|
|
* @adev: amdgpu device structure
|
|
|
|
*
|
|
|
|
* Reset VMID to force flush on next use
|
|
|
|
*/
|
|
|
|
void amdgpu_vmid_reset_all(struct amdgpu_device *adev)
|
|
|
|
{
|
|
|
|
unsigned i, j;
|
|
|
|
|
|
|
|
for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
|
|
|
|
struct amdgpu_vmid_mgr *id_mgr =
|
|
|
|
&adev->vm_manager.id_mgr[i];
|
|
|
|
|
|
|
|
for (j = 1; j < id_mgr->num_ids; ++j)
|
|
|
|
amdgpu_vmid_reset(adev, i, j);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_vmid_mgr_init - init the VMID manager
|
|
|
|
*
|
|
|
|
* @adev: amdgpu_device pointer
|
|
|
|
*
|
|
|
|
* Initialize the VM manager structures
|
|
|
|
*/
|
|
|
|
void amdgpu_vmid_mgr_init(struct amdgpu_device *adev)
|
|
|
|
{
|
|
|
|
unsigned i, j;
|
|
|
|
|
|
|
|
for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
|
|
|
|
struct amdgpu_vmid_mgr *id_mgr =
|
|
|
|
&adev->vm_manager.id_mgr[i];
|
|
|
|
|
|
|
|
mutex_init(&id_mgr->lock);
|
|
|
|
INIT_LIST_HEAD(&id_mgr->ids_lru);
|
|
|
|
atomic_set(&id_mgr->reserved_vmid_num, 0);
|
|
|
|
|
|
|
|
/* skip over VMID 0, since it is the system VM */
|
|
|
|
for (j = 1; j < id_mgr->num_ids; ++j) {
|
|
|
|
amdgpu_vmid_reset(adev, i, j);
|
|
|
|
amdgpu_sync_create(&id_mgr->ids[i].active);
|
|
|
|
list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
adev->vm_manager.fence_context =
|
|
|
|
dma_fence_context_alloc(AMDGPU_MAX_RINGS);
|
|
|
|
for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
|
|
|
|
adev->vm_manager.seqno[i] = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* amdgpu_vmid_mgr_fini - cleanup VM manager
|
|
|
|
*
|
|
|
|
* @adev: amdgpu_device pointer
|
|
|
|
*
|
|
|
|
* Cleanup the VM manager and free resources.
|
|
|
|
*/
|
|
|
|
void amdgpu_vmid_mgr_fini(struct amdgpu_device *adev)
|
|
|
|
{
|
|
|
|
unsigned i, j;
|
|
|
|
|
|
|
|
for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
|
|
|
|
struct amdgpu_vmid_mgr *id_mgr =
|
|
|
|
&adev->vm_manager.id_mgr[i];
|
|
|
|
|
|
|
|
mutex_destroy(&id_mgr->lock);
|
|
|
|
for (j = 0; j < AMDGPU_NUM_VMID; ++j) {
|
|
|
|
struct amdgpu_vmid *id = &id_mgr->ids[j];
|
|
|
|
|
|
|
|
amdgpu_sync_free(&id->active);
|
|
|
|
dma_fence_put(id->flushed_updates);
|
|
|
|
dma_fence_put(id->last_flush);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|