2017-02-16 05:47:32 +00:00
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/*
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* Copyright 2017 Valve Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Andres Rodriguez
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*/
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#include "amdgpu.h"
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#include "amdgpu_ring.h"
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static int amdgpu_queue_mapper_init(struct amdgpu_queue_mapper *mapper,
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int hw_ip)
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{
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if (!mapper)
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return -EINVAL;
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if (hw_ip > AMDGPU_MAX_IP_NUM)
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return -EINVAL;
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mapper->hw_ip = hw_ip;
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mutex_init(&mapper->lock);
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memset(mapper->queue_map, 0, sizeof(mapper->queue_map));
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return 0;
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}
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static struct amdgpu_ring *amdgpu_get_cached_map(struct amdgpu_queue_mapper *mapper,
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int ring)
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{
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return mapper->queue_map[ring];
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}
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static int amdgpu_update_cached_map(struct amdgpu_queue_mapper *mapper,
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int ring, struct amdgpu_ring *pring)
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{
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if (WARN_ON(mapper->queue_map[ring])) {
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DRM_ERROR("Un-expected ring re-map\n");
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return -EINVAL;
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}
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mapper->queue_map[ring] = pring;
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return 0;
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}
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static int amdgpu_identity_map(struct amdgpu_device *adev,
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struct amdgpu_queue_mapper *mapper,
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2017-11-22 14:55:21 +00:00
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u32 ring,
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2017-02-16 05:47:32 +00:00
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struct amdgpu_ring **out_ring)
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{
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switch (mapper->hw_ip) {
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case AMDGPU_HW_IP_GFX:
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*out_ring = &adev->gfx.gfx_ring[ring];
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break;
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case AMDGPU_HW_IP_COMPUTE:
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*out_ring = &adev->gfx.compute_ring[ring];
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break;
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case AMDGPU_HW_IP_DMA:
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*out_ring = &adev->sdma.instance[ring].ring;
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break;
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case AMDGPU_HW_IP_UVD:
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*out_ring = &adev->uvd.ring;
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break;
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case AMDGPU_HW_IP_VCE:
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*out_ring = &adev->vce.ring[ring];
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break;
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case AMDGPU_HW_IP_UVD_ENC:
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*out_ring = &adev->uvd.ring_enc[ring];
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break;
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case AMDGPU_HW_IP_VCN_DEC:
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*out_ring = &adev->vcn.ring_dec;
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break;
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case AMDGPU_HW_IP_VCN_ENC:
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*out_ring = &adev->vcn.ring_enc[ring];
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break;
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default:
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*out_ring = NULL;
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DRM_ERROR("unknown HW IP type: %d\n", mapper->hw_ip);
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return -EINVAL;
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}
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return amdgpu_update_cached_map(mapper, ring, *out_ring);
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}
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2017-03-06 21:27:55 +00:00
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static enum amdgpu_ring_type amdgpu_hw_ip_to_ring_type(int hw_ip)
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{
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switch (hw_ip) {
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case AMDGPU_HW_IP_GFX:
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return AMDGPU_RING_TYPE_GFX;
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case AMDGPU_HW_IP_COMPUTE:
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return AMDGPU_RING_TYPE_COMPUTE;
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case AMDGPU_HW_IP_DMA:
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return AMDGPU_RING_TYPE_SDMA;
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case AMDGPU_HW_IP_UVD:
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return AMDGPU_RING_TYPE_UVD;
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case AMDGPU_HW_IP_VCE:
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return AMDGPU_RING_TYPE_VCE;
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default:
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DRM_ERROR("Invalid HW IP specified %d\n", hw_ip);
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return -1;
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}
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}
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static int amdgpu_lru_map(struct amdgpu_device *adev,
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struct amdgpu_queue_mapper *mapper,
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2017-11-22 14:55:21 +00:00
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u32 user_ring, bool lru_pipe_order,
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2017-03-06 21:27:55 +00:00
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struct amdgpu_ring **out_ring)
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{
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2017-03-17 18:30:15 +00:00
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int r, i, j;
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2017-03-06 21:27:55 +00:00
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int ring_type = amdgpu_hw_ip_to_ring_type(mapper->hw_ip);
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2017-03-17 18:30:15 +00:00
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int ring_blacklist[AMDGPU_MAX_RINGS];
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struct amdgpu_ring *ring;
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2017-03-06 21:27:55 +00:00
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2017-03-17 18:30:15 +00:00
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/* 0 is a valid ring index, so initialize to -1 */
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memset(ring_blacklist, 0xff, sizeof(ring_blacklist));
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for (i = 0, j = 0; i < AMDGPU_MAX_RINGS; i++) {
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ring = mapper->queue_map[i];
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if (ring)
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ring_blacklist[j++] = ring->idx;
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}
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r = amdgpu_ring_lru_get(adev, ring_type, ring_blacklist,
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2017-09-26 21:43:14 +00:00
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j, lru_pipe_order, out_ring);
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2017-03-06 21:27:55 +00:00
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if (r)
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return r;
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return amdgpu_update_cached_map(mapper, user_ring, *out_ring);
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}
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2017-02-16 05:47:32 +00:00
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/**
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* amdgpu_queue_mgr_init - init an amdgpu_queue_mgr struct
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*
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* @adev: amdgpu_device pointer
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* @mgr: amdgpu_queue_mgr structure holding queue information
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*
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* Initialize the the selected @mgr (all asics).
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*
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* Returns 0 on success, error on failure.
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*/
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int amdgpu_queue_mgr_init(struct amdgpu_device *adev,
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struct amdgpu_queue_mgr *mgr)
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{
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int i, r;
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if (!adev || !mgr)
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return -EINVAL;
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memset(mgr, 0, sizeof(*mgr));
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for (i = 0; i < AMDGPU_MAX_IP_NUM; ++i) {
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r = amdgpu_queue_mapper_init(&mgr->mapper[i], i);
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if (r)
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return r;
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}
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return 0;
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}
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/**
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* amdgpu_queue_mgr_fini - de-initialize an amdgpu_queue_mgr struct
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*
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* @adev: amdgpu_device pointer
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* @mgr: amdgpu_queue_mgr structure holding queue information
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*
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* De-initialize the the selected @mgr (all asics).
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*
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* Returns 0 on success, error on failure.
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*/
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int amdgpu_queue_mgr_fini(struct amdgpu_device *adev,
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struct amdgpu_queue_mgr *mgr)
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{
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return 0;
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}
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/**
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* amdgpu_queue_mgr_map - Map a userspace ring id to an amdgpu_ring
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*
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* @adev: amdgpu_device pointer
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* @mgr: amdgpu_queue_mgr structure holding queue information
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* @hw_ip: HW IP enum
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* @instance: HW instance
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* @ring: user ring id
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* @our_ring: pointer to mapped amdgpu_ring
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*
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* Map a userspace ring id to an appropriate kernel ring. Different
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* policies are configurable at a HW IP level.
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*
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* Returns 0 on success, error on failure.
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*/
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int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
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struct amdgpu_queue_mgr *mgr,
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2017-11-22 14:55:21 +00:00
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u32 hw_ip, u32 instance, u32 ring,
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2017-02-16 05:47:32 +00:00
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struct amdgpu_ring **out_ring)
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{
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int r, ip_num_rings;
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struct amdgpu_queue_mapper *mapper = &mgr->mapper[hw_ip];
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if (!adev || !mgr || !out_ring)
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return -EINVAL;
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if (hw_ip >= AMDGPU_MAX_IP_NUM)
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return -EINVAL;
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if (ring >= AMDGPU_MAX_RINGS)
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return -EINVAL;
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/* Right now all IPs have only one instance - multiple rings. */
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if (instance != 0) {
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2017-11-22 14:55:21 +00:00
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DRM_DEBUG("invalid ip instance: %d\n", instance);
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2017-02-16 05:47:32 +00:00
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return -EINVAL;
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}
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switch (hw_ip) {
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case AMDGPU_HW_IP_GFX:
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ip_num_rings = adev->gfx.num_gfx_rings;
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break;
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case AMDGPU_HW_IP_COMPUTE:
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ip_num_rings = adev->gfx.num_compute_rings;
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break;
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case AMDGPU_HW_IP_DMA:
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ip_num_rings = adev->sdma.num_instances;
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break;
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case AMDGPU_HW_IP_UVD:
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ip_num_rings = 1;
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break;
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case AMDGPU_HW_IP_VCE:
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ip_num_rings = adev->vce.num_rings;
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break;
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case AMDGPU_HW_IP_UVD_ENC:
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ip_num_rings = adev->uvd.num_enc_rings;
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break;
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case AMDGPU_HW_IP_VCN_DEC:
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ip_num_rings = 1;
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break;
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case AMDGPU_HW_IP_VCN_ENC:
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ip_num_rings = adev->vcn.num_enc_rings;
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break;
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default:
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2017-11-22 14:55:21 +00:00
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DRM_DEBUG("unknown ip type: %d\n", hw_ip);
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2017-02-16 05:47:32 +00:00
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return -EINVAL;
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}
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if (ring >= ip_num_rings) {
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2017-11-22 14:55:21 +00:00
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DRM_DEBUG("Ring index:%d exceeds maximum:%d for ip:%d\n",
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ring, ip_num_rings, hw_ip);
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2017-02-16 05:47:32 +00:00
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return -EINVAL;
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}
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mutex_lock(&mapper->lock);
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*out_ring = amdgpu_get_cached_map(mapper, ring);
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if (*out_ring) {
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/* cache hit */
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r = 0;
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goto out_unlock;
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}
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switch (mapper->hw_ip) {
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case AMDGPU_HW_IP_GFX:
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case AMDGPU_HW_IP_UVD:
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case AMDGPU_HW_IP_VCE:
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case AMDGPU_HW_IP_UVD_ENC:
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case AMDGPU_HW_IP_VCN_DEC:
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case AMDGPU_HW_IP_VCN_ENC:
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r = amdgpu_identity_map(adev, mapper, ring, out_ring);
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break;
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2017-03-17 18:41:21 +00:00
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case AMDGPU_HW_IP_DMA:
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2017-09-26 21:43:14 +00:00
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r = amdgpu_lru_map(adev, mapper, ring, false, out_ring);
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break;
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2017-03-06 21:27:55 +00:00
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case AMDGPU_HW_IP_COMPUTE:
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2017-09-26 21:43:14 +00:00
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r = amdgpu_lru_map(adev, mapper, ring, true, out_ring);
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2017-03-06 21:27:55 +00:00
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break;
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2017-02-16 05:47:32 +00:00
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default:
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*out_ring = NULL;
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r = -EINVAL;
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2017-11-22 14:55:21 +00:00
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DRM_DEBUG("unknown HW IP type: %d\n", mapper->hw_ip);
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2017-02-16 05:47:32 +00:00
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}
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out_unlock:
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mutex_unlock(&mapper->lock);
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return r;
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}
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