2020-06-25 13:14:15 +00:00
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#include <hyp/debug-sr.h>
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#include <linux/compiler.h>
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#include <linux/kvm_host.h>
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#include <asm/debug-monitors.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_hyp.h>
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#include <asm/kvm_mmu.h>
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2020-06-25 13:14:19 +00:00
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static void __debug_save_spe(u64 *pmscr_el1)
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2020-06-25 13:14:15 +00:00
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{
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u64 reg;
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/* Clear pmscr in case of early return */
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*pmscr_el1 = 0;
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2021-04-05 16:42:53 +00:00
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/*
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* At this point, we know that this CPU implements
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* SPE and is available to the host.
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* Check if the host is actually using it ?
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*/
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2020-06-25 13:14:15 +00:00
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reg = read_sysreg_s(SYS_PMBLIMITR_EL1);
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2023-01-09 19:26:18 +00:00
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if (!(reg & BIT(PMBLIMITR_EL1_E_SHIFT)))
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2020-06-25 13:14:15 +00:00
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return;
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/* Yes; save the control register and disable data generation */
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2024-02-29 14:54:17 +00:00
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*pmscr_el1 = read_sysreg_el1(SYS_PMSCR);
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write_sysreg_el1(0, SYS_PMSCR);
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2020-06-25 13:14:15 +00:00
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isb();
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/* Now drain all buffered data to memory */
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psb_csync();
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}
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2020-06-25 13:14:19 +00:00
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static void __debug_restore_spe(u64 pmscr_el1)
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2020-06-25 13:14:15 +00:00
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{
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if (!pmscr_el1)
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return;
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/* The host page table is installed, but not yet synchronised */
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isb();
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/* Re-enable data generation */
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2024-02-29 14:54:17 +00:00
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write_sysreg_el1(pmscr_el1, SYS_PMSCR);
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2020-06-25 13:14:15 +00:00
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}
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2021-04-05 16:42:54 +00:00
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static void __debug_save_trace(u64 *trfcr_el1)
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{
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*trfcr_el1 = 0;
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/* Check if the TRBE is enabled */
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2023-06-14 06:59:36 +00:00
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if (!(read_sysreg_s(SYS_TRBLIMITR_EL1) & TRBLIMITR_EL1_E))
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2021-04-05 16:42:54 +00:00
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return;
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/*
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* Prohibit trace generation while we are in guest.
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* Since access to TRFCR_EL1 is trapped, the guest can't
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* modify the filtering set by the host.
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*/
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2024-02-29 14:54:17 +00:00
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*trfcr_el1 = read_sysreg_el1(SYS_TRFCR);
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write_sysreg_el1(0, SYS_TRFCR);
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2021-04-05 16:42:54 +00:00
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isb();
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/* Drain the trace buffer to memory */
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tsb_csync();
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}
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static void __debug_restore_trace(u64 trfcr_el1)
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{
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if (!trfcr_el1)
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return;
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/* Restore trace filter controls */
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2024-02-29 14:54:17 +00:00
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write_sysreg_el1(trfcr_el1, SYS_TRFCR);
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2021-04-05 16:42:54 +00:00
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}
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2021-03-05 18:52:47 +00:00
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void __debug_save_host_buffers_nvhe(struct kvm_vcpu *vcpu)
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2020-06-25 13:14:15 +00:00
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{
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/* Disable and flush SPE data generation */
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2022-05-28 11:38:19 +00:00
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if (vcpu_get_flag(vcpu, DEBUG_STATE_SAVE_SPE))
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2021-04-05 16:42:53 +00:00
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__debug_save_spe(&vcpu->arch.host_debug_state.pmscr_el1);
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2021-04-05 16:42:54 +00:00
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/* Disable and flush Self-Hosted Trace generation */
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2022-05-28 11:38:19 +00:00
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if (vcpu_get_flag(vcpu, DEBUG_STATE_SAVE_TRBE))
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2021-04-05 16:42:54 +00:00
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__debug_save_trace(&vcpu->arch.host_debug_state.trfcr_el1);
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2021-03-05 18:52:47 +00:00
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}
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void __debug_switch_to_guest(struct kvm_vcpu *vcpu)
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{
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2020-06-25 13:14:15 +00:00
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__debug_switch_to_guest_common(vcpu);
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}
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2021-03-05 18:52:47 +00:00
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void __debug_restore_host_buffers_nvhe(struct kvm_vcpu *vcpu)
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2020-06-25 13:14:15 +00:00
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{
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2022-05-28 11:38:19 +00:00
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if (vcpu_get_flag(vcpu, DEBUG_STATE_SAVE_SPE))
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2021-04-05 16:42:53 +00:00
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__debug_restore_spe(vcpu->arch.host_debug_state.pmscr_el1);
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2022-05-28 11:38:19 +00:00
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if (vcpu_get_flag(vcpu, DEBUG_STATE_SAVE_TRBE))
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2021-04-05 16:42:54 +00:00
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__debug_restore_trace(vcpu->arch.host_debug_state.trfcr_el1);
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2021-03-05 18:52:47 +00:00
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}
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void __debug_switch_to_host(struct kvm_vcpu *vcpu)
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{
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2020-06-25 13:14:15 +00:00
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__debug_switch_to_host_common(vcpu);
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}
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2021-08-17 08:11:22 +00:00
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u64 __kvm_get_mdcr_el2(void)
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2020-06-25 13:14:15 +00:00
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{
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return read_sysreg(mdcr_el2);
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}
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